UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_______________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_______________
`
`APPLE INC.,
`Petitioner
`
`v.
`
`LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.,
`Patent Owner
`_______________
`
`Case IPR2015-01933
`Patent No. 6,831,865
`
`_______________
`
`
`
`
`
`PATENT OWNER LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.
`AND EXCLUSIVE LICENSEE LONGITUDE LICENSING LTD.’S
`PRELIMINARY RESPONSE
`
`
`
`
`
`

`
`TABLE OF CONTENTS
`
`
`Introduction ...................................................................................................... 1
`I.
`II. Background ....................................................................................................... 3
`A. About U.S. Patent No. 6,831,865 (the “‘865 patent” or “Chang”) .................. 3
`B. The ‘865 Claims .............................................................................................10
`C. Petitioner’s Grounds of Challenge .................................................................12
`III. Argument ........................................................................................................17
`A. The Petition Fails to Comply with the Board’s Rules for Particularity .........18
`B. The Proposed Grounds of Rejection Fail .......................................................20
`1. Claim Construction ......................................................................................20
`2. Challenge #1: U.S. Patent No. 5,485,595 (“Assar”) Fails to
`Anticipate Claims 1-3, 5, 18, and 25-27 ...................................................23
`3. Challenge #2: Apple Fails to Establish that Dependent Claims 8, 24,
`and 29, are Obvious over Assar in view of the Knowledge of a
`POSITA .....................................................................................................29
`4. Challenge #3: Apple Has Not Shown Dependent Claims 4-5 and 28
`to be Obvious over Assar in view of Estakhri ..........................................30
`5. Challenge #4: Lin Fails to Anticipate Claim 18..........................................31
`6. Challenge #5: Apple Fails to Establish that Dependent Claim 24 is
`Obvious over Lin in view of the Knowledge of a POSITA ......................33
`7. Challenge #6: Apple Fails to Establish that Claims 1-3, 8, 18, 24-27,
`and 29 are Obvious over Kim in view of the Linux Publication and
`the Knowledge of POSITA .......................................................................34
`8. Challenge #7: Apple Fails to Establish that Claims 4, 5, 24, and 28
`are Obvious over Kim in view of Lin .......................................................41
`IV. Conclusion ......................................................................................................41
`
`
`
`
`i
`
`

`
`Cases
`
`TABLE OF AUTHORITIES
`
`Apple Inc. v. ContentGuard Holdings, LLC,
`Case No. IPR2015-00446 (PTAB July 10, 2015) (Paper 11) .................. 18, 19, 20
`Cisco Sys., Inc. v. C-Cation Techs., LLC,
`Case No. IPR2014-00454 (PTAB Aug. 29, 2014) (Paper 12) .............................19
`Fresenius USA, Inc. v. Baxter Intern., Inc.,
`582 F.3d 1288 (Fed. Cir. 2009) ............................................................................26
`Hughes Network Sys., LLC v. Cal. Inst. of Tech.,
`Case No. IPR2015-00060 (PTAB Nov. 6, 2015) (Paper 20) ...............................36
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................21
`Microsoft Corp v. Biscotti Inc.,
`Case No. IPR2014-01457 (PTAB. Mar. 19, 2015) (Paper 9) ...............................36
`Panduit Corp. v. Dennison Mfg. Co.,
`810 F.2d 1561 (Fed. Cir. 1987) ............................................................................36
`SRI Int'l, Inc. v. Internet Sec. Sys., Inc.,
`511 F.3d 1186 (Fed. Cir. 2008) ............................................................................36
`Statutes
`
`35 U.S.C. § 102(g) ...................................................................................................35
`35 U.S.C. § 314(a) .................................................................................... 1, 2, 17, 41
`35 U.S.C. § 325(d) ...................................................................................................35
`Other Authorities
`
`MPEP § 2182 .................................................................................................... 27, 33
`Office Patent Trial Practice Guide,
`77 Fed. Reg. 48756 (Aug. 14, 2012) ....................................................................20
`Rules
`
`37 C.F.R. §a42.6(a)(3) .........................................................................................1, 19
`37 C.F.R. §b42.22(a)(2) .......................................................................................1, 19
`37 C.F.R. §c42.24(a)(1)(i) .......................................................................................19
`37 C.F.R. §e42.100(b) ..............................................................................................20
`
`
`
`ii
`
`

`
`37 C.F.R. §g42.104(b)(4) ........................................................................................... 1
`37 C.F.R. §g42.104(b)(4) ......................................................................................... ..1
`37 C.F.R. §h42.104(b)(5) ........................................................................................... 1
`37 C.F.R. §h42.104(b)(5) ......................................................................................... ..1
`
`
`
`
`
`iii
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`iii
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`

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`LIST OF EXHIBITS
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`
`
`Description
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`None
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`
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`
`
`iv
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`
`
`Exhibit
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`N/A
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`

`
`I.
`
`Introduction
`
`Apple’s Petition for inter partes review of U.S. Patent No. 6,831,865 (“the
`
`‘865 patent”) should be denied and no trial instituted because there is no
`
`“reasonable likelihood that the petitioner would prevail with respect to at least 1 of
`
`the claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`The ‘865 patent provides memory structures and means to promote more
`
`even wear of a non-volatile memory without requiring a significant use of
`
`computational resources. Apple’s challenges fail to disclose or suggest these
`
`claimed structures or means.
`
`In addition, the Petition should fail because it is in violation of the governing
`
`statute and the Board’s requirements, including those set forth in 35 U.S.C. §
`
`311(b), 37 C.F.R. §§ 42.6(a)(3), 42.22(a)(2), 42.104(b)(4), and 42.104(b)(5).
`
`In a proper petition: grounds of challenge should be clear and
`
`understandable; arguments must not be incorporated by reference from one
`
`document to another; a detailed explanation of the significance and relevance of
`
`the evidence, including any differences from the prior art, must be included; and a
`
`specific showing of where each element of the challenged claims is satisfied by the
`
`prior art must be made. But in this Petition, the materials attached to the Petition,
`
`including declaration and numerous exhibits mentioned nowhere in the Petition,
`
`
`
`1
`
`

`
`seek to vastly expand the scope and content of the Petition, instead of particularly
`
`stating the challenges and reasons therefore, as required by the Board’s rules.
`
`Moreover, Apple’s Challenges #6 and #7 are fundamentally flawed. As will
`
`be explained below, Challenge #6 does not analyze certain claims at all, and
`
`Challenge #7 applies fewer references when attacking dependent claims than
`
`Challenge #6 applied to the corresponding independent claims, without any
`
`justification. Further, a Petition must be based on patents or printed publications
`
`only. Apple fails to show that the non-patent materials relied upon in its Challenge
`
`#6 were printed publications, including when and how they were published.
`
`Moreover, Apple only provides a partial copy of one of the non-patent materials.
`
`For these reasons and more, the Petition fails to meet its burden in
`
`establishing a reasonable likelihood of success on any challenged claim. Since the
`
`Petition fails to show a “reasonable likelihood that the petitioner would prevail
`
`with respect to at least 1 of the claims,” and since Petitioner has failed to comply
`
`with the Board’s requirements in making the requisite showing, the Petition should
`
`be denied. 35 U.S.C. § 314(a).
`
`
`
`
`
`
`
`2
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`

`
`II. Background
`
`A. About U.S. Patent No. 6,831,865 (the “‘865 patent” or “Chang”)
`The ‘865 patent is entitled “MAINTAINING ERASE COUNTS IN NON-
`
`VOLATILE STORAGE SYSTEMS,” and it discloses techniques for efficient
`
`maintenance of erase counts, which are used to allow the wear associated with
`
`storage areas in a non-volatile storage system to be spread out across substantially
`
`all storage areas. ‘865 patent at 1:35-40. The ‘865 patent was filed as U.S. Patent
`
`Application No. 10/281,696 on October 28, 2002.
`
`The ‘865 patent explains that the repetitive programming of non-volatile
`
`memory systems, such as flash memory storage systems, causes the memory to
`
`wear out. ‘865 patent at 1:65-2:3. In particular, each block or physical location of
`
`the memory may only be erased a certain number of times before the block wears
`
`out, at least reducing the available size of the memory and potentially causing data
`
`loss or the inability to store data. ‘865 patent at 1:65-2:14. When some blocks are
`
`effectively worn out while other blocks are relatively unworn, the existence of the
`
`worn out blocks generally compromises the overall performance of the flash
`
`memory system unnecessarily. For example, a flash memory system may be
`
`deemed unusable when a critical number of worn out blocks are present in the
`
`flash memory system, even when many other cells in the flash memory system are
`
`relatively unworn. Id. at 2:31-38.
`
`
`
`3
`
`

`
`In order to increase the likelihood that blocks within a flash memory system
`
`are worn fairly evenly, the ’865 patent explains that “wear leveling” operations can
`
`be performed to, generally speaking, allow the physical locations or blocks which
`
`are associated with particular logical block addresses (LBAs) to be changed such
`
`that the same logical block addresses are not always associated with the same
`
`physical locations or blocks, making it less likely that a particular block may wear
`
`out well before other blocks wear out. ‘865 patent at 2:47-56.
`
`One conventional wear leveling process involves swapping physical
`
`locations to which two relatively large portions of host LBAs are mapped. That is,
`
`the LBAs associated with relatively large sections of storage cells are swapped.
`
`Swapping the data typically involves copying the data into another location and
`
`erasing the data from the first location. ‘865 patent at 2:57-3:6.
`
`The ‘865 patent is directed to efficiently and substantially transparently
`
`performing wear leveling within a flash memory storage system, seeking to
`
`promote more even wear without requiring a significant use of computational
`
`resources. ‘865 patent at 3:19-27.
`
`To more evenly use a memory, the ‘865 patent discloses keeping track of
`
`how many times each block in the memory has been erased, as for example
`
`through the utilization of an erase count. ‘865 patent at 5:44-49. At issue in this
`
`proceeding, the ‘865 patent provides memory structures, in the non-volatile
`
`
`
`4
`
`

`
`memory and in the system memory, to promote more even wear without requiring
`
`a significant use of computational resources. See, e.g., Fig. 5a at 480 and 454.
`
`Any suitable data structure in a system memory may be arranged to hold
`
`erase counts and an average erase count. ‘865 patent at 23:38-42. In one aspect of
`
`the ‘865 patent, blocks of the non-volatile memory containing user data are
`
`“categorized” into, e.g., three groups, in-use blocks, most-frequently erased blocks,
`
`and least frequently erased blocks. ‘865 patent at 5:52-6:5.
`
`When a block in use is erased, the block may be “added” to either a table of
`
`blocks which have relatively high erase counts or a table of blocks which have
`
`relatively low erase counts, as appropriate, based on an erase count stored with the
`
`block. Likewise, blocks may be “moved” from either the table of blocks which
`
`have relatively high erase counts or the table of blocks which have relatively low
`
`erase counts into the block mapping table, i.e., a set of tables of blocks which are
`
`in use, to substantially replace any block which has been reassigned from the block
`
`mapping table. ‘865 patent at 5:52-65.
`
`Categorizing blocks into tables enables blocks with a low erase count and
`
`blocks with a high erase count to be readily identified and, hence, allows for wear
`
`leveling without needing a significant amount of computational resources. ‘865
`
`patent at 5:66-6:5.
`
`
`
`5
`
`

`
`In an embodiment of the ‘865 patent, the non-volatile memory can allocate
`
`an erase count block. ‘865 patent at 6:10-19. Such a block may be arranged to
`
`provide a table that contains the erase counts of substantially all blocks which may
`
`be used to store data within the flash memory. The use of a table separate from the
`
`user data allows for effective maintenance of erase counts. For example, when a
`
`block containing user data is erased, the erase count of the block is typically erased
`
`at the same time. By storing the erase counts of substantially all blocks which have
`
`an associated erase count in the table of the erase count block, the erase count of an
`
`erased block may be readily obtained, e.g., by reading the erase count from the
`
`erase count block.
`
`A table in the non-volatile memory of an embodiment of the ‘865 patent can
`
`contain a variety of information. It can store an indication of a number of times
`
`blocks of the non-volatile memory have been erased and whether a block is
`
`unusable. ‘865 patent at 19:29-39. It can also include a header arranged to contain
`
`information relating to the blocks in the non-volatile memory, such as an average
`
`erase count indicating an average number of times each block in the plurality of
`
`blocks has been erased. Id. at 19:2-6; 20:15-18.
`
`Such a table allows the lifetime of a particular physical block, even an
`
`erased physical block, to be efficiently determined. ‘865 patent at 3:45-49.
`
`Specifically, by storing the erase counts of substantially all physical blocks which
`
`
`
`6
`
`

`
`have an associated erase count, or an indicator which identifies how many times a
`
`particular block has been erased, in an erase count block, the erase count of
`
`substantially any block may be determined by reading the appropriate erase count
`
`entry from the erase count block. As such, the number of erase cycles already
`
`undergone by a given block may be readily ascertained. Indications of whether
`
`particular blocks are unusable, e.g., have factory defects or growing defects, may
`
`also be stored in the erase count block to enable it to be readily determined whether
`
`particular blocks are usable. Id. at 3:49-61.
`
`FIG. 8a of the ‘865 patent provides a diagrammatic representation of an
`
`embodiment of an erase count block, i.e., a table of an embodiment of the ‘865
`
`patent. Erase count block 800 may include, e.g.,
`
`approximately three bytes for each block in the
`
`non-volatile memory. ‘865 patent at 18:44-45.
`
`Pages 810 in the erase count block contain erase
`
`count entries (a first page 810a may be arranged
`
`to contain erase count entries for blocks ‘0’
`
`through ‘169’ while second page 810b may be
`
`arranged to contain erase count entries for
`
`blocks ‘170’ through ‘339’). ‘865 patent at 18:53-65. When a particular block is
`
`unusable and may not be written to or read from, e.g., due to a manufacturing or
`
`
`
`7
`
`

`
`factory defect, that block will generally not have an erase count. In lieu of holding
`
`an erase count, entries for unusable blocks may hold indicators or markings which
`
`are arranged to identify blocks as being unusable. Id. at 19:29-39.
`
`Erase count block 800, in addition to including pages 810, also includes a
`
`header 820 that generally relates to the blocks within a non-volatile memory
`
`system, such as information relating to the number of hidden blocks, the number of
`
`reserved blocks, a total number of blocks, a total number of useable (in-use or
`
`available) and unusable blocks, and an average erase count. ‘865 patent at 19:2-6;
`
`20:2-17.
`
`The information in the table of the erase count block can be used in creation
`
`of associated tables in system memory. As depicted in Fig. 5a, system memory 454
`
`can hold a block mapping table
`
`462, a least frequently erased
`
`block
`
`table 466, and a most
`
`frequently erased block table 470.
`
`‘865 patent at 14:27-40. An
`
`average erase count 474, which is
`
`arranged to hold the average erase
`
`count of blocks within
`
`flash
`
`memory 460, is created when an
`
`
`
`8
`
`

`
`overall flash memory system is formatted. ‘865 patent at 14:40-43. In one
`
`embodiment, an erase count block 480 is arranged to contain the erase counts of
`
`substantially all blocks 465 within flash memory 460. ‘865 patent at 14:43-45.
`
`The tables in the system memory can be formed in response to an
`
`initialization request. As shown in Fig. 3, at step 320, a block mapping table is
`
`allocated in the system memory. The block mapping table may be arranged to
`
`provide a mapping between a logical
`
`block address (LBA) and a physical block
`
`address (PBA). Additionally, a most
`
`frequently erased block table and a least
`
`frequently erased block table are also
`
`allocated in step 320. ‘865 patent at 11:18-
`
`24. The most frequently erased block table
`
`holds information relating to erased blocks
`
`which have been erased most frequently.
`
`That is, a most frequently erased block is
`
`arranged to hold information, e.g., erase
`
`counts
`
`and mapping
`
`information,
`
`pertaining
`
`to erased blocks with
`
`the
`
`highest erase counts
`
`in
`
`the system.
`
`
`
`9
`
`

`
`Similarly, a least frequently erased block table holds information pertaining to
`
`erased blocks with the lowest erase counts. ‘865 patent at 11:25-34.
`
`After tables are allocated in step 320, erased blocks are identified in step
`
`324. ‘865 patent at 11:52-53. Then, in step 328, ‘N’ erased blocks may be assigned
`
`to the most frequently erased blocks and essentially be assigned to the most
`
`frequently erased table. Id. at 11:53-65. Once the most frequently erased block
`
`table is effectively populated, ‘M’ erased blocks may be identified and effectively
`
`be assigned to the least frequently erased block table in step 332. Id. at 11:66-12:9.
`
`
`
`The ‘865 Claims
`
`B.
`Petitioner challenges the validity of claims 1-5, 8, 18, and 24-29. Of these
`
`challenged claims, claims 1, 18, and 25 are independent. The independent claims
`
`are presented below:
`
`1. A data structure, the data structure being arranged in a non-volatile
`memory associated with a non-volatile memory system, the non-volatile
`memory system including a non-volatile memory which includes a plurality
`of blocks, the data structure comprising:
`a first indicator, the first indicator being arranged to provide an
`indication of a number of times a first block of the plurality of blocks has
`been erased; and
`a header, the header being arranged to contain information relating to
`the plurality of blocks.
`
`
`
`
`10
`
`

`
`18. A non-volatile memory system comprising:
`a non-volatile memory, the non-volatile memory including a plurality
`of blocks;
`a system memory; and
`means for indicating in the system memory a number of times each
`usable block included in the plurality of blocks has been erased.
`
`25. A data structure, the data structure being arranged in a physical
`block of non-volatile memory associated with a non-volatile memory
`system, the non-volatile memory system including a non-volatile memory
`which includes a plurality of blocks, the data structure comprising:
`a first plurality of indicators, the first plurality of indicators being
`arranged to provide indications of numbers of times blocks included in the
`plurality of blocks have been erased; and
`a plurality of pages, the pages of the plurality of pages being
`substantially divided into groups of bytes arranged to contain the first
`plurality of indicators, wherein a first page of the plurality of pages includes
`a first group of the groups of bytes that is arranged to contain a first indicator
`of the first plurality of indicators which is associated with a first block of the
`plurality of blocks.
`
`
`
`
`11
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`

`
`Petitioner’s Grounds of Challenge
`
`C.
`Petitioner’s purported grounds of rejection are as follows:
`
`Ground Basis
`
`Reference(s)
`
`1
`
`Anticipation under § 102
`
`U.S. Patent No. 5,485,595 (“Assar”)
`
`of claims 1-3, 5, 18, and
`
`25-27
`
`
`
`2
`
`Obviousness under § 103
`
`Assar in view of “the knowledge of a
`
`of claims 8, 24, and 29
`
`POSITA”
`
`
`
`3
`
`4
`
`5
`
`
`
`Obviousness under § 103
`
`Assar in view of U.S. Patent No. 5,838,614
`
`of claims 4-5 and 28
`
`(“Estakhri”)
`
`Anticipation under § 102
`
`U.S. Patent No. 6,427,186 (“Lin”)
`
`of claim 18
`
`Obviousness under § 103
`
`Lin in view of “the knowledge of a POSITA”
`
`of claim 24
`
`12
`
`

`
`6
`
`Obviousness under § 103
`
`U.S. Patent No. 6,381,176 (“Kim”) in view
`
`of claims 1-3, 8, 18, 24-
`
`of “the Linux Publication” and “the
`
`27, and 29
`
`knowledge of POSITA”
`
`7
`
`Obviousness under § 103
`
`Kim in view of Lin
`
`of claims 4, 5, 24 and 28
`
`
`
`Throughout this Preliminary Response, for ease of understanding, Longitude
`
`will refer to these references primarily by the names indicated above, rather than
`
`by exhibit number. These references are described below at Section III, in
`
`conjunction with the arguments presented in this Preliminary Response.1
`
`Apple’s Petition should be rejected because it is rife with impermissible
`
`incorporation by reference. For example, Apple often cites to the Baker declaration
`
`(Ex. 1003) in lieu of providing a fulsome exposition of Apple’s challenge in the
`
`Petition. For example, Apple’s analysis of the Assar reference relative to claim
`
`element 1(b) in its Petition could be contained on a single page (Pet. at 21-22); yet,
`
`
`1 Longitude reserves all right to present further argument and evidence related to
`
`these references and the content of the Petition and supporting Exhibits if Inter
`
`Partes Review is instituted, consistent with the Board’s Rules and practice. No
`
`waiver is intended by any argument withheld at this stage of the proceeding.
`
`
`
`13
`
`

`
`the Baker Declaration discusses this same element across three pages of reduced-
`
`font, single-spaced text. Ex. 1003 at 81-83.
`
`Moreover, Apple ostensibly relies on three primary references and three
`
`secondary references in seven challenges, yet its petition includes 40 exhibits.
`
`Many of these exhibits relate to Apple’s Challenge #6, where, in the place of
`
`consideration of a prior art printed publication, Apple relies on a technical
`
`declarant’s analysis of snippets of source code.
`
`In short, it is unclear how this large number of exhibits is being used in the
`
`Petition, and whether, for example, Apple intends to include these materials in its
`
`vague references to the knowledge of a POSITA. As such, Apple’s challenges are
`
`unclear.
`
`Further, throughout the Petition, Apple seeks to incorporate by reference a
`
`declaration of its technical declarant that is over four-times the size of an allowable
`
`petition. The declaration itself, in large part, is a mere paraphrase of the content of
`
`the Petition. For example, the Petition’s discussion of the Linux challenge can be
`
`found in a repackaged, and only slightly reworded, form in the declaration, as
`
`shown in the table below:
`
`Petition
`
`Declaration
`
`“The Linux publication was authored by
`
`“The Linux publication was authored by
`
`Dr. David Hinds, packaged into a
`
`Dr. David Hinds, packaged into a single
`
`
`
`14
`
`

`
`single .tar file (“pcmcia-cs-3.1.21.tar”)
`
`.tar file (“pcmcia-cs-3.1.21.tar”) and
`
`and published online and made available
`
`made available to the public in its
`
`to the public on October 3, 2000. Ex.
`
`entirety on October 3, 2000. Ex. 1025 at
`
`1025 at ¶10. Therefore, the Linux
`
`¶ 10. For the purpose of this inter partes
`
`Publication qualifies as prior art to
`
`review, I understand that only selected
`
`the ’865 patent under at least pre-AIA
`
`excerpts from the .tar container file have
`
`35 U.S.C. §§ 102 (a) and (b). For the
`
`been submitted as separate Exhibits,
`
`purpose of this inter partes review,
`
`although a true and correct copy of the
`
`Petitioner has submitted only selected
`
`full .tar file can still be accessed
`
`excerpts from the .tar container file as
`
`publicly at the following URL:
`
`separate Exhibits (Ex. 1026-1036),
`
`http://sourceforge.net/projects/pcmcia-
`
`although a true and correct copy of the
`
`cs/files/pcmcia-cs/3.1.21/. Ex. 1025 at ¶
`
`full .tar file can still be accessed
`
`10. It is my understanding that the
`
`publicly at the following URL:
`
`Linux Publication qualifies as prior art
`
`http://sourceforge.net/projects/pcmcia-
`
`to the ’729 patent under at least pre-AIA
`
`cs/files/pcmciacs/3.1.21/. Ex. 1025 at
`
`35 U.S.C. §§ 102 (a) and (b).” (Ex. 1003
`
`¶10. However, Petitioner submits that
`
`at ¶ 131.)
`
`collectively, Exhibits 1026-1036
`
`constitute excerpts from a single piece
`
`of prior art publication..” (Pet. at 44.)
`
`
`
`15
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`

`
`“Dr. Hinds began working on earlier
`
`“It is my understanding that Dr. Hinds
`
`versions of this publication in as early as
`
`began working on this publication in
`
`1995. His goal was, in part, to enable
`
`1995. I understand that his goal was, in
`
`products that comply with the
`
`part, to create card services driver
`
`“PCMCIA Standard” to work with
`
`software for the Linux operating system
`
`computers that run the Linux
`
`to enable products based on the
`
`operating system. See Ex. 1025 at ¶ 4.”
`
`PCMCIA standard. See Ex. 1025 at ¶ 4.
`
`(Pet. at 44-45.)
`
`My understanding is that the Linux
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`Publication, therefore, is compliant with
`
`the PC Card Standard. See Ex. 1025 at
`
`¶¶ 4-13; see also Ex. 1029 at 3.” (Ex.
`
`1003 at ¶ 135.)
`
`
`
`Moreover, the declaration includes nearly 150 pages of single-spaced, reduced font
`
`claim charts (see Ex. 1003, Tables 1-5, pages 74-118, 125-135, 148-195, 203-245),
`
`which the Petition repeatedly attempts to incorporate by reference without proper
`
`discussion of those tables. See, e.g., Pet. at 22 (citing to “Table 1”). This strategy
`
`represents an impermissible extension of the Petition’s page limit and this material
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`should be given little to no weight for the purposes of this proceeding.
`
`
`
`16
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`

`
`III. Argument
`
`The institution of an inter partes review requires a petitioner to establish that
`
`there is a “reasonable likelihood that the petitioner would prevail with respect to at
`
`least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a). None of
`
`Petitioner’s challenges meet the required threshold, and the Board should deny the
`
`Petition and decline to institute the inter partes review.
`
`As a preliminary matter, the procedural defects in the Petition render it
`
`impossible to determine the precise Grounds Petitioner seeks to raise, including the
`
`content of those challenges. Indeed, for Apple’s sixth and seventh challenges,
`
`Apple has not established that the applied references are prior art printed
`
`publications under 35 U.S.C. § 311(b), has not applied an analysis to each
`
`challenged claims, and has failed to apply its combinations of references in a
`
`logical manner. Thus, as will be explained in more detail below, the Petition
`
`should be denied solely on procedural grounds.
`
`Substantively, Apple has failed to show the claimed data structures and
`
`means are present in the prior art.
`
`
`
`
`
`17
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`

`
`A. The Petition Fails to Comply with the Board’s Rules for
`Particularity
`
`Apple’s Petition has several significant procedural defects, not the least of
`
`which is obfuscation as to the actual challenges being presented to the Board for
`
`consideration. As explained in an earlier case involving a petition by Apple, in
`
`Apple Inc. v. ContentGuard Holdings, LLC, Case No. IPR2015-00446, Decision,
`
`slip op. at 12-17 (PTAB July 10, 2015) (decision denying institution of inter partes
`
`review) (Paper 11),
`
`[A] petition for inter partes review must “identif[y], in
`writing and with particularity, each claim challenged, the
`grounds on which the challenge to each claim is based,
`and the evidence that supports the grounds for the
`challenge to each claim.” 35 U.S.C. § 312(a)(3).
`According to 37 C.F.R. § 42.104(b)(4), a petition for
`inter partes review “must identify . . . [h]ow the
`construed claim is unpatentable under the statutory
`grounds” on which the petitioner challenges the claims,
`and “must specify where each element of the claim is
`found in the prior art patents or printed publications
`relied upon.” Rule 42.104(b)(5) requires a petition to
`“identify[] specific portions of the evidence that support
`the challenge.” Similarly, 37 C.F.R. § 42.22(a)(2) states
`that each petition must include “[a] full statement of the
`reasons for the relief requested, including a detailed
`explanation of the significance of the evidence including
`material facts, and the governing law, rules, and
`precedent.” The Office Patent Trial Practice Guide
`suggests that parties requesting inter partes review should
`“avoid submitting a repository of all the information that
`a judge could possibly consider, and instead focus on
`concise, well-organized, easy-to-follow arguments
`supported by readily identifiable evidence of record.” 77
`Fed. Reg. 48,756, 48,763 (Aug. 14, 2012).
`
`
`
`18
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`

`
`
`
`As was the case with Apple’s petition in ContentGuard, Apple’s Petition
`
`here “contains vague, nested string citations to broad swaths of the references, the
`
`[technical] Declaration, and internal cross-references to whole sections of the
`
`Petition.” ContentGuard, slip op. at 13.
`
`Apple’s attempt to rely on a declaration that vastly expands the page-limit
`
`for the Petition should be rejected, as a review of the declaration reveals it is
`
`merely a large-format petition, replete with impermissible argument lacking
`
`evidentiary foundation, rather than an attempt to explain the references relied upon
`
`in Apple’s challenges. Accordingly, not only should Apple’s declaration be given
`
`little weight, Apple’s Petition should be denied for failing to comply with the
`
`Board’s page limits. See ContentGuard, slip op. at 15-16 (noting that use of a
`
`massive Declaration violates the Board’s Rules for “impermissible incorporation
`
`by reference” and circumvention of page limits) (citing Cisco Sys., Inc. v. C-Cation
`
`Techs., LLC, Case No. IPR2014-00454, slip op. at 7–10 (PTAB Aug. 29, 2014)
`
`(decision denying institution of inter partes review) (Paper 12) (informative) and
`
`37 C.F.R. §§ 42.24(a)(1)(i), 42.6(a)(3)). Under 37 C.F.R. § 42.22(a)(2), the petition
`
`itself must include “[a] full statement of the reasons for the relief requested,
`
`including a detailed explanation of the significance of the evidence including
`
`material facts, and the governing law, rules, and precedent.”
`
`
`
`19
`
`

`
`Finally, the Petition’s citation of numerous references not relied upon in the
`
`Challenges render the Challenges unclear and improper. See ContentGuard, slip
`
`op. at 16-17.
`
`Moreover, with regard to Challenge #6 and #7, Apple’s positions are unclear
`
`and not based on prior art printed publications, as will be explained in more detail
`
`below in the section addressing those challenges.
`
`Accordingly, the Board may and should deny the Petition solely on
`
`procedural grounds.
`
`The Proposed Grounds of Rejection Fail
`
`B.
`However, the procedural defects do not define the universe of the Petition’s
`
`shortcomings. The Petition should also be denied because no Ground of challenge
`
`is likely to succeed.
`
`Claim Construction
`
`1.
`Since the ‘865 patent is not expired, Longitude understands that the Board
`
`will interpret claims using the broadest reasonable interpretation as understood by
`
`one of ordinary skill in the art and consistent with the disclosure. See Office Patent
`
`Trial Practice Guide, 77 Fed. Reg. 48756, 48766 (Aug. 14, 2012); 37 C.F.R. §
`
`42.100(b). Under the broadest reasonable construction standard, claim terms are
`
`given their ordinary and customary meaning, as would be understood by one of
`
`ordinary skill in the art at the time of the invention. In re Translogic Tech., Inc.,
`
`
`
`20
`
`

`
`504 F.3d 1249, 1257 (Fed. Cir. 2007). Longitude submits that no construction is
`
`necessary regarding the ter