UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_______________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_______________
`
`
`
`
`
`APPLE INC.
`Petitioner
`
`v.
`
`LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.
`Patent Owner
`
`_______________
`
`Case IPR2015-01934
`Patent 8,316,177
`
`_______________
`
`
`
`PATENT OWNER LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L.
`AND EXCLUSIVE LICENSEE LONGITUDE LICENSING LTD.’S
`PRELIMINARY RESPONSE
` 
`
` 
`
`

`
`Introduction .......................................................................................................... 1 
`I. 
`II.  Background ....................................................................................................... 2 
`A.  About U.S. Patent No. 8,316,177 (the “‘177 patent”) .................................. 2 
`B. 
`Petitioner’s Grounds of Challenge ................................................................ 7 
`III.  Claim Construction ........................................................................................... 9 
`A. 
`Petitioner’s Proposed Construction Is Unnecessary ..................................... 9 
`IV.  The Petitioner Does Not Demonstrate That It Is More Likely Than Not to
`Prevail On Any Challenged Claim on the ‘177 Patent ............................................ 10 
`A. 
`Petitioner Fails to Demonstrate That Niijima Anticipates Claims 1-4, 6 and
`8 (Ground 1) .......................................................................................................... 10 
`  Petitioner Improperly Conflates Multiple Embodiments in Niijima .......... 11 1.
`
`
`  The Petitioner Fails To Demonstrate That Niijima Discloses “each page is 2.
`programmable in a preset order at a specified offset position,” As Recited In
`Independent Claim 1 .......................................................................................... 15 
`  The Petitioner Fails To Demonstrate That Niijima Discloses “programming 3.
`
`the…updated user data…in at least a second one of the blocks without
`necessarily in the same offset positions as in the at least a first one of the
`blocks,” As Recited In Independent Claim 1 .................................................... 16 
`  The Petitioner Fails To Demonstrate That Niijima Discloses “reading at 4.
`
`least the one or more pages of updated data from the at least the second one of
`the blocks…and reading pages of original user data that have not been
`updated…,” As Recited In Independent Claim 1 .............................................. 19 
`  The Petitioner Fails To Demonstrate That Niijima Discloses That “the 5.
`
`memory controller is further characterized by controlling operation of the
`memory system to assemble the read pages of updated data and read pages of
`original data not updated…,” As Recited In Claim 2 ........................................ 22 
`  The Petitioner Fails To Demonstrate That Niijima Discloses That “the 6.
`
`memory controller is further characterized by causing the one or more logical
`addresses…to also be programmed into those of the second one or more
`pages…along with the pages of updated data…,” As Recited In Claim 3 ........ 24 
`
`ii
` 
`
`

`
`  The Petitioner Fails To Demonstrate That Niijima Discloses That “the 7.
`
`memory controller is further characterized by causing the one or more logical
`addresses…to also be programmed into those of the first plurality of
`pages…along with the pages of original user data…,” As Recited In Claim 4 26 
`B. 
`The Petitioner Fails To Demonstrate That Niijima and the Admitted Prior
`Art or Cappelletti Render Obvious Claims 1-4, 6, and 8 (Ground 2) .................. 26 
`  The Petitioner Fails to Set Forth A Proper Obviousness Analysis ............. 27 1.
`
`
`  The Admitted Prior Art is Not Properly Combinable With Niijima to Teach 2.
`Claim 2 ............................................................................................................... 31 
`C. 
`The Petitioner Fails To Demonstrate That Niijima and the Admitted Prior
`Art or Miyauchi Render Obvious Claim 5 (Ground 3) ........................................ 32 
`D.  The Petitioner Fails To Demonstrate That Niijima and the Admitted Prior
`Art or Cappelletti Render Obvious Claim 7 (Ground 4) ...................................... 35 
`E.  Ground 5 ...................................................................................................... 37 
`F. 
`Reservation of Argument Regarding Other Deficiencies ........................... 37 
`V.  Conclusion ...................................................................................................... 38 
`
`
`
`iii
` 
`
`

`
`Cases 
`
`Table of Authorities
`
`Continental Can Co. v. Monsanto Co., 948 F.2d 1264 (Fed. Cir. 1991) ................ 21
`Corning Incorporated v. DSM IP Assets B.V., IPR 2013-00048, paper 94 (PTAB
`5/9/2014) ............................................................................................................... 22
`Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966) ............................. 27
`In re Oelrich, 666 F.2d 578 (CCPA 1981) .............................................................. 20
`In re Rijckaert, 9 F.3d 1531 (Fed. Cir. 1993) .......................................................... 20
`In re Translogic Tech., Inc., 504 F.3d 1249 (Fed. Cir. 2007) ................................... 9
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007) ................................................ 27
`Liberty Mutual v. Progressive Casualty, CBM2012-00003, paper 8 (PTAB
`10/25/2012) ........................................................................................................... 15
`MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362 (Fed. Cir. 1999) ............. 20
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359 (Fed. Cir. 2008) .............. 11, 12
`Nvidia Corp. v. Samsung Electronics Co., Ltd., IPR2015-01318, paper 8 (PTAB
`12/7/2015) ...................................................................................................... 11, 12
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48756 (Aug. 14, 2012) .......... 9, 22
`OSRAM Sylvania, Inc. v. Am. Induction Techs., Inc., 701 F.3d 698 (Fed. Cir. 2012)
` ............................................................................................................................... 27
`SanDisk Corp. v. Kingston Tech. Co., 2011 U.S. Dist. LEXIS 27696 (W.D. Wis.
`Mar. 15, 2011) ....................................................................................................... 14
`Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628 (Fed. Cir. 1987) .... 10
`Statutes 
`
`35 U.S.C. § 102 ................................................................................................... 8, 10
`35 U.S.C. § 103(a) ..................................................................................................... 8
`35 U.S.C. § 314(a) ........................................................................................ 1, 10, 38
`Other Authorities 
`
`M.P.E.P. § 2112 (IV) ............................................................................................... 20
`M.P.E.P. § 2131 ....................................................................................................... 10
`Rules 
`
`37 C.F.R. § 42.22(a)(2) .............................................................................................. 2
`
`iv
` 
`
`

`
`37 C.F.R. § 42.65(a) ............................................................................................ 1, 21
`37 C.F.R. § 42.65(a) .......................................................................................... .. 1, 21
`37 C.F.R. § 42.100(b) ................................................................................................ 9
`37 C.F.R. §42.100(b) .............................................................................................. ..9
`37 C.F.R. § 42.104(b)(4) ............................................................................................ 2
`37 C.F.R. § 42.104(b)(4) .......................................................................................... ..2
`37 C.F.R. § 42.104(b)(5) ............................................................................................ 2
`37 C.F.R. § 42.104(b)(5) .......................................................................................... ..2
`Fed. R. Evid. 705 ..................................................................................................... 22
`
`Fed. R. Evid. 705 ................................................................................................... ..22
`
`
`
`
`
`v
` 
`
`

`
`LIST OF PATENT OWNER’S EXHIBITS
`
`
`
`Description
`
`Claim Construction Opinion and Order, SanDisk Corp. v.
`Kingston Tech. Co., 2011 U.S. Dist. LEXIS 27696 (W.D. Wis.
`Mar. 15, 2011)
`
`
`
`
`Exhibit
`
`2001
`
`
`
`vi
` 
`
`

`
`I.
`
`Introduction
`
`The Petition for inter partes review of U.S. Patent No. 8,316,177 (“the ’177
`
`patent”) should be denied and no trial instituted because there is no “reasonable
`
`likelihood that the petitioner would prevail with respect to at least one of the
`
`claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`The Petition presents grounds for challenge against claims 1-9 of the ‘177
`
`patent based on anticipation and/or obviousness. But many of these grounds
`
`improperly rely on the doctrine of inherency without factual support for
`
`Petitioner’s allegations. Additionally, the Petitioner’s obviousness-based
`
`challenges not only fail to reach every feature of the challenged claims, they also
`
`lack sufficient rationale for why a person of ordinary skill in the art would have
`
`modified the prior art to disclose or suggest the challenged claims. And Petitioner’s
`
`expert testimony often fails to “disclose the underlying facts or data” on which it is
`
`based, in violation of 37 C.F.R. § 42.65(a), and instead simply repeats unsupported
`
`attorney argument and conclusions presented by Petitioner. Moreover, Petitioner
`
`habitually and improperly points to separate embodiments in a single reference,
`
`neither of which discloses all claim elements as arranged in the claim, to support
`
`allegations of anticipation. Petitioner similarly conflates different embodiments in
`
`the same reference to support obviousness allegations. But those allegations are
`
`void of support or evidence for combining the separate embodiments. As such,
`
` 
`
`1
`
`

`
`Petitioner does not meet its burden in establishing a reasonable likelihood of
`
`success.
`
`Further, the Petition is in violation of the Board’s governing requirements,
`
`including those set forth in 37 C.F.R. §§ 42.22(a)(2), 42.104(b)(4), and
`
`42.104(b)(5). Under these requirements, the Petition must include a detailed
`
`explanation of the significance and relevance of the evidence; and the Petition
`
`must specify where each element of the challenged claims is found in the prior art.
`
`II. Background
`
`A. About U.S. Patent No. 8,316,177 (the “‘177 patent”)
`
`The ‘177 patent is entitled “PARTIAL BLOCK DATA PROGRAMMING
`
`AND READING OPERATIONS IN A NON-VOLATILE MEMORY,” and it
`
`discloses techniques for updating data in less than all of the pages of a non-volatile
`
`memory block by programming new data in unused pages of either the same or
`
`another block. Ex. 1001 at Abstract. The ‘177 patent was filed as U.S. Patent
`
`Application No. 13/168,756 on June 24, 2011 and was issued on November 20,
`
`2012. The ‘177 patent ultimately claims priority to and the benefit of U.S. Patent
`
`Application No. 09/766,436, filed on January 19, 2001, now U.S. Patent No.
`
`6,763,424.
`
`Flash memory devices comprise one or more arrays of transistor cells, each
`
`cell capable of non-volatile storage of one or more bits of data so that power is not
`
`2
` 
`
`

`
`required to retain the data programmed therein. Ex. 1001 at 1:34-37. Once a cell is
`
`programmed, it must be erased before it can be reprogrammed with new data. Id. at
`
`1:38-39. Typical flash memory arranges large groups of cells into erasable blocks,
`
`wherein a block contains the smallest number of cells that are erasable at one time.
`
`Id. at 1:41-45. Blocks are often partitioned into individually addressable pages that
`
`are the basic unit for programming user data. Id. at 1:55-60.
`
`Ideally, the data in all of the pages in a block are updated together by
`
`programming the updated data into the pages of an erased block. Ex. 1001 at 2:9-
`
`12. However, it is more typical that data in less than all of the pages in a block are
`
`updated while the data in the remaining pages of that block remain unchanged. Id.
`
`at 2:13-18. This typical update is sometimes referred to as a partial block update.
`
`Id. at 2:20-24.
`
`The ‘177 patent describes two prior art techniques for performing partial
`
`block updates. Ex. 1001 at 2:21-35. In the first prior art technique, data of the
`
`pages to be updated are written into a corresponding number of pages in an unused
`
`erased block. Id. at 2:20-24. The unchanged pages from the original block are then
`
`copied into pages of the new block (e.g., the previously unused erased block). Id.
`
`The original block may then be erased. Id. at 2:24-26. This first prior art technique
`
`has problems. Notably, copying unchanged pages from the original block to the
`
`3
` 
`
`

`
`new block greatly reduces the write performance and usable lifetime of the storage
`
`system. Id. at 6:6-11.
`
`In the second prior art technique described by the ‘177 patent, updated pages
`
`are also written to a new block, but the need to copy unchanged pages of the
`
`original block into the new block is eliminated. Ex. 1001 at 2:26-32. This need is
`
`eliminated through the use of flags associated with each page. Id. When updated
`
`data is written to a new block, the flags of pages in the original block which
`
`correspond to the updated data are updated to indicate that they now contain
`
`obsolete (invalid) data. Id. This second prior art technique suffers from limitations
`
`as well. To program obsolete flags in pages where the data has been superceded
`
`requires that a page support multiple programming cycles. Id. at 6:67-7:2. And in
`
`some cases, memory systems do not permit additional cycles. Id. at 7:10-13.
`
`Moreover, blocks in a system that uses obsolete flags must support the ability to
`
`program a page when other pages in the block with higher offsets or addresses
`
`have already been programmed. Id. at 7:5-7. However, a limitation of some flash
`
`memories prevents the usage of obsolete flags by specifying that the pages in a
`
`block can only be programmed in a physically sequential manner. Id. at 7:7-10.
`
`One additional problem with some systems that use obsolete flags is that
`
`allowing those flags to be written in pages whose data is being superceded can
`
`disturb data in other pages of the same block that remain current. Id. at 7:29-32.
`
`4
` 
`
`

`
`NAND type flash memory is particularly susceptible to such disturbs when being
`
`operated in a multi-state mode to store more than one bit of data in each cell. Id. at
`
`7:37-40.
`
`The ‘177 patent presents several solutions to the problems of the prior art. In
`
`these solutions, pages containing updated data are assigned the same logical
`
`address as the pages whose data has been superceded. Ex. 1001 at 7:61-64. Rather
`
`than using obsolete flags to tag the pages whose data has been superceded, the
`
`memory controller distinguishes the pages with updated data from those with
`
`superceded data by keeping track of the order in which the page having the same
`
`logical address were written. Id. at 7:64-8:6. The controller can do so, for example,
`
`using a counter or time stamp. Id. at 7:64-8:6, 8:41-62. Alternatively, when pages
`
`are written in order within blocks from the lowest to highest physical page address,
`
`the controller can identify the most recent copy of data by checking the physical
`
`addresses of the pages that contain the updated and superceded data. Id. at 7:64-
`
`8:6. In this case, the higher physical address contains the most recent copy of the
`
`data. Id.
`
`FIG. 8 of the ‘177 shows an exemplary implementation.
`
`5
` 
`
`

`
`
`
`In this example, new data 37 for each of pages 3-5 of block 35 is written into
`
`three pages (0-2) of a new block 39 that has been previously erased. Ex. 1001 at
`
`8:17-20, FIG. 8. Pages 3-5 from block 35 is thus now superceded by pages 0-2
`
`from new block 39. Pages 3-5 from block 35 also have the same logical address as
`
`pages 0-2 from new block 39. Id. at 8:20-23. In order for the memory controller to
`
`determine whether pages 3-5 from block 35 or pages 0-2 from new block 39
`
`contains the updated data, each page contains an overhead field 43 that provides an
`
`indication of its relative time of programming. Id. at 8:33-40. The memory
`
`6
` 
`
`

`
`controller can thus use the overhead field when called upon to read the data, and
`
`assemble data from the identified new pages in new block 39 along with original
`
`data that has not been updated from block 35. Id. at 8:63-9:3.
`
`The example of FIG. 8 also shows that the pages with the updated data are
`
`stored in the first three pages (0-2) of new block 39, rather than in the same pages
`
`(3-5) as in block 35. Id. at 9:4-7. In other words, the respective pages have
`
`different offset positions. This is made possible by keeping track of the individual
`
`logical page numbers. Id. at 9:7-10. Pages of updated data can also be written to
`
`erased pages of the same block as the page of data being superceded. Id. at 9:10-
`
`12.
`
`B.
`
`Petitioner’s Grounds of Challenge
`
`The Petitioner challenges the validity of claims 1-9 of the ‘177 patent.
`
`Notwithstanding the Petitioner’s insufficient allegations of inherency and
`
`unsupported combinations of references, the cited art fails to disclose many of the
`
`features recited in the claims. The asserted grounds identified in the Petition rely
`
`upon five prior art references, including so-called Admitted Prior Art identified in
`
`the ‘177 patent. The Petitioner also relies upon the Declaration of Dr. Vivek
`
`Subramanian (“Subramanian Decl.”) (Ex. 1007).
`
`The asserted grounds of rejection are as follows:
`
`
`
`7
` 
`
`

`
`Ground Basis
`
`Reference
`
`1
`
`2
`
`3
`
`4
`
`5
`
`
`
`Anticipation under 35
`U.S.C. § 102(b) of
`Claims 1-4, 6, and 8
`Obviousness under 35
`U.S.C. § 103(a) of
`Claims 1-4, 6, and 8
`Obviousness under 35
`U.S.C. § 103(a) of Claim
`5
`Obviousness under 35
`U.S.C. § 103(a) of Claim
`7
`Obviousness under 35
`U.S.C. § 103(a) of Claim
`9
`
`U.S. Patent No. 5,457,658 to Niijima (Ex.
`1003) (“Niijima”)
`
`Niijima + Admitted Prior Art + “Flash
`Memories”, edited by Cappelletti et al. (Ex.
`1004) (“Cappelletti”)
`Niijima + Admitted Prior Art + U.S. Patent
`No. 5,627,783 to Miyauchi (Ex. 1005)
`(“Miyauchi”)
`Niijima + Admitted Prior Art + Cappelletti
`
`Niijima + Admitted Prior Art + PC Card
`Standard, Volumes 1 and 3 (Ex. 1006) (“PC
`Card Standard”)
`
`Throughout this Preliminary Response, for ease of understanding, the Patent
`
`Owner will refer to these prior art references by the names indicated above.1 These
`
`prior art references are described below at Section IV, in conjunction with the
`
`arguments presented in this Preliminary Response.2
`
`                                                            
`1 Patent Owner notes that both Niijima and Miyauchi were considered by the U.S.
`
`Patent Office (“PTO”) during the prosecution of the ‘177 patent. The PTO was
`
`right to allow the ‘177 patent over these references.
`
`2
`
` Patent Owner reserves its right to present further argument and evidence related
`
`to these prior art references and the content of the Petition and supporting Exhibits
`
`8
` 
`
`

`
`III. Claim Construction
`
`The standard for construing claim terms in this proceeding is not in dispute.
`
`Since the ‘177 patent is not expired, the Board will interpret claims using the
`
`broadest reasonable interpretation as understood by one of ordinary skill in the art
`
`and consistent with the disclosure (“BRI”). See Office Patent Trial Practice Guide,
`
`77 Fed. Reg. 48756, 48766 (Aug. 14, 2012) (“Office Patent Trial Practice Guide”);
`
`37 C.F.R. § 42.100(b). Under the BRI analysis, claim terms are given their
`
`ordinary and customary meaning, as would be understood by one of ordinary skill
`
`in the art at the time of the invention. In re Translogic Tech., Inc., 504 F.3d 1249,
`
`1257 (Fed. Cir. 2007).
`
` 
`
`A.
`
`Petitioner’s Proposed Construction Is Unnecessary
`
`The Petitioner proposes that the term “memory controller” be construed as
`
`“a device that controls access to a memory device.” Petition at 11. In support of
`
`this construction, the Petitioner does not rely on anything found in the ‘177 patent
`
`itself. Id. Instead, the Petitioner relies on a dictionary definition without explaining
`
`why it is appropriate to do so or why that particular definition should be used. Id.
`
`The Patent Owner does not believe that it is necessary to needlessly construe
`                                                                                                                                                                                                
`later in this proceeding, consistent with the Board’s Rules and practice. No waiver
`
`is intended by any argument withheld by Patent Owner at this stage of the
`
`proceeding.
`
`9
` 
`
`

`
`“memory controller,” particularly if extrinsic evidence must be used to do so.3
`
`Rather, the Patent Owner believes that the term’s ordinary and customary meaning
`
`should be applied.
`
`IV. The Petitioner Does Not Demonstrate That It Is More Likely Than Not
`to Prevail On Any Challenged Claim on the ‘177 Patent
`
` 
`
`The institution of an inter partes review requires Petitioner to establish that
`
`there is a “reasonable likelihood that the petitioner would prevail with respect to at
`
`least one of the claims challenged in the petition.” 35 U.S.C. § 314(a). None of
`
`Petitioner’s challenges meet this threshold, and the Board should deny the Petition
`
`and deny institution of the inter partes review.
`
`A.
`
`Petitioner Fails to Demonstrate That Niijima Anticipates Claims
`1-4, 6 and 8 (Ground 1)
`
`A finding of invalidity under 35 U.S.C. § 102 requires a showing that a
`
` 
`
`single reference teaches every limitation of the claim. “A claim is anticipated only
`
`if each and every element as set forth in the claim is found, either expressly or
`
`inherently described, in a single prior art reference.” M.P.E.P. § 2131, quoting
`
`Verdegaal Bros. v. Union Oil Co. of California, 814 F.2d 628, 631 (Fed. Cir.
`
`1987). Furthermore, an anticipatory reference must not only “disclose all elements
`
`of the claim within the four corners of the document,” it must disclose those
`                                                            
`3 Moreover, the Petitioner’s proposed construction is circular and not particularly
`
`helpful.
`
`10
` 
`
`

`
`elements “arranged as in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d
`
`1359, 1369 (Fed. Cir. 2008). The Petitioner in this case fails to establish that any
`
`claim of the ‘177 patent is anticipated by Niijima because it fails to show that
`
`Niijima discloses all the limitations of any challenged claim.
`
`
`1.
`
`Petitioner Improperly Conflates Multiple Embodiments in
`Niijima
`
`In arguing that certain claims are anticipated by Niijima, the Petitioner
`
`repeatedly relies on two different embodiments to attempt to cobble together an
`
`argument that the reference discloses each of the claimed features. But that is
`
`improper. Where a prior art reference discloses two embodiments, neither of which
`
`discloses all elements of a claim as arranged in the claim, those embodiments
`
`cannot be combined for anticipation purposes. See Net MoneyIN, Inc. v. Verisign,
`
`Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008); Nvidia Corp. v. Samsung Electronics
`
`Co., Ltd., IPR2015-01318, paper 8 at 17 (PTAB 12/7/2015). In that situation, the
`
`challenger must also present obviousness evidence to support the combination of
`
`the embodiments. The Petitioner in this case fails to do so.
`
`For example, with respect to claim 1, in arguing that “Niijima describes a
`
`memory controller,” the Petitioner points to controller 30 in Fig. 4, which is part of
`
`the preferred embodiments of Niijima. Petition at 19. Yet, the Petitioner
`
`subsequently points to operations performed by the solid state file apparatus (SSF)
`
`11
` 
`
`

`
`of Niijima’s admitted prior art, which is a different system, as teaching portions of
`
`the operations claimed in the ‘177 patent. For example, the Petitioner relies on the
`
`embodiment depicted in Fig. 2, which is a prior art system that differs from the
`
`system shown in Figs. 3 and 4, as allegedly teaching at least part of the claimed
`
`operations (a) and (b). Petition at 19-21. Pointing to two separate embodiments, as
`
`the Petitioner does, in support of an anticipation challenge is fatal to the challenge.
`
`See Net MoneyIN, Inc. v. Verisign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008);
`
`Nvidia Corp. v. Samsung Electronics Co., Ltd., IPR2015-01318, paper 8 at 17.
`
`Hypothetically speaking, separate embodiments could be combined where
`
`sufficient evidence of obviousness supports the combination of the separate
`
`embodiments. But here, the Petitioner fails to present such evidence. Therefore,
`
`Petitioner’s challenge of claim 1 fails on its face. See id.
`
`The Petitioner makes similar mistakes in its anticipation challenges of
`
`claims 3, 4, and 6. For each of these additional claims, the Petitioner again relies
`
`on two separate embodiments in Niijima as allegedly teaching the claim
`
`limitations. Petition at 25-27. And the Petitioner again fails to present obviousness
`
`evidence to support the combination of the separate embodiments on which the
`
`Petitioner relies. Therefore, Petitioner’s challenge of claims 3, 4, and 6 must fail.
`
`See Net MoneyIN, Inc. v. Verisign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008);
`
`Nvidia Corp. v. Samsung Electronics Co., Ltd., IPR2015-01318, paper 8 at 17.
`
`12
` 
`
`

`
`The problems do not cease with claims 1, 3, 4, and 6. The Petitioner makes
`
`the same error in its challenge of claim 5, which is an obviousness challenge.
`
`Petition at 32-35. While the Petitioner does not rely on Niijima for anticipation of
`
`claim 5, the Petitioner does still blur separate and distinct embodiments of Niijima
`
`in its obviousness challenge. Specifically, the Petitioner indicates that Niijima
`
`“provides the example of a logical address of ‘(1,4,5),’ which means Head 1,
`
`Cylinder 4, Sector 5.” Id. at 32. This example comes from the prior art
`
`embodiment of Fig. 2 (reproduced below), not the preferred embodiment on which
`
`the Petitioner relies as allegedly teaching the claimed memory controller.
`
`Despite challenging claim 5 under obviousness, the Petitioner still fails to
`
`present obviousness evidence to support the combination of the separate
`
`embodiments in Niijima on which the Petitioner relies. Id. at 32-35.
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`Moreover, even if the Petitioner had provided such obviousness evidence,
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`the challenge would have continued to fall short. The first relied-upon embodiment
`
`in Niijima, focused on the prior art system depicted in Fig. 2, is directed to a
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`memory system that uses invalid flags to mark superceded data as obsolete. Ex.
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`1003 at 2:57-67. However, this type of system was expressly disclaimed in the
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`‘177 patent. Ex. 1001 at 7:14-18; Ex. 2001 at 39-40. 4
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`The second relied-upon embodiment in Niijima does not use invalid flags,
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`and in fact is designed so as to not have to use invalid flags. Exhibit 1003 at 7:60-
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`8:6. Combining the two embodiments of Niijima together (something that the
`
`Petitioner did not even suggest) would either result in a system where invalid flags
`
`are used by the system to determine which data is valid or a system that is
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`inoperable due to the disparate manners in which the two embodiments work. In
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`either case, the two relied-upon embodiments in Niijima are not properly
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`combinable.
`                                                            
`4 Ex. 2001 is a claim construction order and opinion from SanDisk Corp. v.
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`Kingston Tech. Co., 2011 U.S. Dist. LEXIS 27696, *48 (W.D. Wis. Mar. 15,
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`2011). In that case, the Court held that, in a patent that has the same specification
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`as the ‘177 patent (namely, U.S. Patent No. 7,657,702), the same text upon which
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`the Patent Owner relies in the present IPR establishes that the patentee intended to
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`disclaim the use of invalid data flags.
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`2.
`
`The Petitioner Fails To Demonstrate That Niijima Discloses
`“each page is programmable in a preset order at a specified
`offset position,” As Recited In Independent Claim 1
`
`Claim 1 recites that “each page is programmable in a preset order at a
`
`specified offset position.” The Petitioner fails to show that Niijima discloses this
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`feature. The Petitioner points to col. 7, lines 38-59 of Niijima as disclosing this
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`element. Petition at 17-18. After reviewing the cited portion of Niijima, the Patent
`
`Owner is unable to determine how the Petitioner believes it maps to the claimed
`
`“each page is programmable in a preset order at a specified offset position.” At
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`most, the cited portion of Niijima appears to disclose programming in a preset
`
`order (e.g., Niijima discloses writing in ascending or descending order of address),
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`but there is no clear teaching of “at a specified offset position.”
`
`The Petitioner’s analysis in this regard is so vague and ambiguous that it
`
`forces the Patent Owner to “conjure up arguments against its own patent.” Liberty
`
`Mutual v. Progressive Casualty, CBM2012-00003, paper 8 at 14-15 (PTAB
`
`10/25/2012). The Board has previously warned against this practice:
`
`We address only the basis, rationale, and reasoning put forth by the
`Petitioner and resolve all vagueness and ambiguity in Petitioner’s
`arguments against the Petitioner. … It would be unfair to expect the
`Patent Owner to conjure up arguments against its own patent, and just
`as inappropriate for the Board to take the side of the Petitioner to
`salvage an inadequately expressed ground…
`Id.
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`15
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`In view of this vagueness and the lack of express teaching of the claimed “at a
`
`specified offset position,” the Petitioner’s challenge of claim 1 should be denied.
`
`
`3.
`
`The Petitioner Fails To Demonstrate That Niijima
`Discloses “programming the…updated user data…in at
`least a second one of the blocks without necessarily in the
`same offset positions as in the at least a first one of the
`blocks,” As Recited In Independent Claim 1
`
`Claim 1 also recites that “programming the received one or more pages of
`
`updated user data into a second one or more pages of storage elements in the preset
`
`order in at least a second one of the blocks without necessarily in the same offset
`
`positions as in at least a first one of the blocks.” The Petitioner fails to show that
`
`Niijima discloses this feature.
`
`To allege a teaching of programming updated user data into “a second one or
`
`more pages…in at least a second one of the blocks,” the Petitioner argues that
`
`“when the SSF receives another command to write new data to the same logical
`
`address, the new data is programmed into a sector (i.e., at least one page) of said
`
`one or another of the plurality of blocks.” Petition at 20. The first problem with this
`
`argument is that, as explained in more detail in Section IV.A.1. above, it is an
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`example of the improper mixing of embodiments by the Petitioner. The operation
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`pointed to by the Petitioner in this instance is from Niijima’s prior art embodiment.
`
`Petition at 20; Ex. 1003 at 2:45-67. But the Petitioner relies on the preferred
`
`embodiments of Niijima to teach other aspects of the claim. Mixing and matching
`
`16
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`embodiments in this manner is improper when, as here, the Petitioner fails to
`
`present obviousness evidence to support the combination of the separate
`
`embodiments.
`
`Another problem with the Petitioner’s argument is that the Petitioner posits
`
`that Niijima teaches that new data is programmed into a section “of said one or
`
`another of the plurality of blocks.” Petition at 20. But claim 1 does not recite “said
`
`one or another of the plurality of blocks.” Rather, it indicates that updated user data
`
`is programmed into a second one or more pages of storage elements in the preset
`
`order “in at least a second one of the blocks.” This difference is significant,
`
`because it appears that the Petitioner may be interpreting that language as being
`
`met by a system that programs updated user data to the same block as the original
`
`user data.
`
`The Petitioner relies on Fig. 2 of Niijima and