UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`XILINX, INC.,
`Petitioner
`
`v.
`
`QUICKCOMPILE IP, LLC and
`PIXEL VELOCITY INCORPORATED,
`Patent Owner
`
`___________________
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 7,073,158
`
`
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`XILINX, INC.,
`Petitioner
`
`v.
`
`QUICKCOMPILE IP, LLC and
`PIXEL VELOCITY INCORPORATED,
`Patent Owner
`
`___________________
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 7,073,158
`
`
`
`Petition for Inter Partes Review of U.S. 7,073,158
`
`TABLE OF CONTENTS
`
`I. MANDATORY NOTICES.............................................................................. 1
`
`A. Real Party-in-Interest............................................................................. 1
`
`B. Related Matters...................................................................................... 1
`
`C.
`
`Patent Owner ......................................................................................... 1
`
`D. Lead and Back-up Counsel and Service Information.............................. 2
`
`II. CERTIFICATION OF GROUNDS FOR STANDING.................................... 3
`
`III. OVERVIEW OF THE ‘158 Patent .................................................................. 3
`
`A.
`
`B.
`
`Specification and Claims of the ‘158 Patent........................................... 3
`
`Prosecution History of the ‘158 Patent................................................... 6
`
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED ...................... 7
`
`A.
`
`B.
`
`Prior Art Printed Publications of the Present Petition............................. 7
`
`Statutory Grounds for Challenge............................................................ 9
`
`C. Requested Relief...................................................................................10
`
`V. CLAIM CONSTRUCTION.............................................................................10
`
`A.
`
`“analyzing” ...........................................................................................11
`
`VI. IDENTIFICATION OF GROUNDS FOR PETITION....................................12
`
`A. Ground I: Claims 1, 2, 4, 9, 16, and 18-20 are unpatentable under 35
`U.S.C. § 103(a) over Banerjee and Benkrid.............................................13
`
`B. Ground II: Claims 3, 5, 7, and 8 are unpatentable under 35 U.S.C. §
`103(a) over Banerjee, Benkrid, and Haldar .............................................35
`
`i
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`C. Ground III: Claim 6 is unpatentable under 35 U.S.C. § 103(a) over
`Banerjee, Benkrid, Haldar, and Hammes ................................................44
`
`D. Ground IV: Claims 10-13 and 17 are unpatentable under 35 U.S.C. §
`103(a) over Banerjee, Benkrid, and AAPA .............................................46
`
`E. Ground V: Claims 14 and 15 are unpatentable under 35 U.S.C. §
`103(a) over Banerjee, Benkrid, AAPA, and Grant...................................56
`
`VII.
`
`CONCLUSION.....................................................................................59
`
`ii
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`FEDERAL CASES
`
`TABLE OF AUTHORITIES
`
`Dystar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick,
`464 F.3d 1356, 1368, (Fed. Cir. 2006) ..................................................37, 57
`
`In re GPAC Inc.,
`57 F.3d 1573, 1579 (Fed. Cir. 1995) ...........................................................12
`
`In re Gurley,
`27 F.3d 551, 554 (Fed. Cir. 1994) ...............................................................35
`
`In re Paulsen,
`30 F.3d 1475, 1480 (Fed. Cir. 1994) ...........................................................12
`
`In re Preda,
`401 F.2d 825, 826 (CCPA 1968).................................................................13
`
`In re Rinehart,
`531 F.2d 1048, 1051 (CCPA 1976).......................................................12, 52
`
`In re Samour,
`571 F.2d 559, 562 (CCPA 1978).................................................................12
`
`In re Susi,
`440 F.2d 442 (CCPA 1971) ........................................................................35
`
`In re Translogic Tech., Inc.,
`504 F.3d 1249, 1257 (Fed. Cir. 2007) .............................................10, 11, 13
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398, 406 (2007)...................................12, 13, 24, 38, 46, 49, 51, 53
`
`iii
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`Medichem, S.A. v. Rolabo, S.L.,
`437 F.3d 1157, 1165 (Fed. Cir. 2006) .........................................................35
`
`Multiform Desiccants, Inc. v. Medzam, Ltd.,
`133 F.3d 1473, 1477 (Fed. Cir. 1998) .........................................................10
`
`Okajima v. Bourdeau,
`261 F.3d 1350, 1355 (Fed. Cir. 2001) .........................................................12
`
`REGULATORY CASES
`
`Samsung Elecs. Co., Ltd. v. Va. Innov. Scis., Inc.,
`IPR2013-00569, Paper 9 at *2, (Oct. 30, 2013) .............................................10
`
`iv
`
`
`
`Ex. 1001
`
`Ex. 1002
`Ex. 1003
`Ex. 1004
`Ex. 1005
`
`Ex. 1006
`
`Ex. 1007
`
`Ex. 1008
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
`Ex. 1013
`
`Petition for Inter Partes Review of U.S. 7,073,158
`
`PETITIONER’S EXHIBIT LIST
`OCTOBER 20, 2015
`
`U.S. Patent No. 7,073,158 (the “‘158 Patent”). The
`‘158 Patent also contains Applicants Admitted
`Prior Art (“AAPA”)
`U.S. Patent No. 7,587,699 (the “‘699 Patent”).
`‘158 Patent File History
`Declaration of Dr. Martin G. Walker.
`Banerjee et al., A MATLAB Compiler For
`Distributed, Heterogeneous, Reconfigurable
`Computing Systems (“Banerjee”)
`Benkrid et al., High Level Programming For
`FPGA Based Image And Video Processing Using
`Hardware Skeletons (“Benkrid)
`Haldar, et al., Scheduling Algorithms for
`Automated Synthesis of Pipelined Designs on
`FPGAs for Applications described in MATLAB,
`(“Haldar”)
`Hammes, et al., Cameron: High Level Language
`Compilation for Reconfigurable Systems
`(“Hammes”)
`Xilinx The Programmable Logic Data Book,
`(“Xilinx Data Book”)
`Lokanathan, et at., Performance Optimized Floor
`Planning by Graph Planarization, (“Lokanathan”)
`Lucent Technologies Field-Programmable Gate
`Arrays Data Book (“Lucent”)
`Li, et al., A Computational Algorithm for
`Minimizing Total Variation in Image Restoration
`(“Li”)
`Weste, et al., CMOS VLSI Design: A Circuits and
`Systems Perspective, Addison-Wesley (“Weste”)
`
`v
`
`
`
`Ex. 1014
`Ex. 1015
`Ex. 1016
`Ex. 1017
`Ex. 1018
`
`Ex. 1019
`Ex. 1020
`
`Ex. 1021
`Ex. 1022
`Ex. 1023
`Ex. 1024
`
`Petition for Inter Partes Review of U.S. 7,073,158
`
`USPTO Assignment Record
`QuickCompile Complaint
`U.S. Patent No. 5,971,595 (“Grant”).
`Webster’s II, New College Dictionary, 1999
`Reconfigurable Computing Seminar Carnegie
`Mellon University
`U.S. Patent No. 5,659,781 (“Larson”)
`MATLAB Programming Object-Oriented
`Programming Example
`MATLAB, Language Reference Manual
`U.S. Patent No. 7,000,213 (the “Banerjee Patent”)
`C Family of Languages
`Semeria, A Dissertation Submitted To The
`Department Of Electrical Engineering Of Stanford
`University In partial Fulfillment Of The
`Requirements For The Degree Of Doctor Of
`Philosophy (“Semeria”)
`
`vi
`
`
`
`Petition for Inter Partes Review of U.S. 7,073,158
`
`In accordance with 35 U.S.C. §311 and 37 C.F.R. §42.100, Xilinx, Inc.
`
`(“Petitioner”) respectfully submits that this petition demonstrates a reasonable
`
`likelihood that the Petitioner will prevail with respect to at least one of the
`
`challenged claims (i.e., claims 1-20) of U.S. patent 7,073,158 (the “‘158 Patent,”)
`
`(Ex. 1001) and requests inter partes review of these claims. 35 U.S.C. §314(a).
`
`I.
`
`MANDATORY NOTICES
`
`A.
`
`Real Party-in-Interest
`
`Xilinx, Inc. is the real party-in-interest.
`
`B. Related Matters
`
`As of the filing date of this petition and to the best knowledge of Petitioner,
`
`the ‘158 Patent is the subject of the following litigations:
`
` QuickCompile IP, LLC v. Xilinx, Inc., 2:15-cv-00820 (ED Texas)
`
` QuickCompile IP, LLC v. Altera Corp., 2-15-cv-00818 (ED Texas)
`
`The noted litigations relate to the ‘158 Patent and U.S. Patent No. 7,587,699
`
`(“the ‘699 Patent”) (Ex. 1002), which is a divisional of the ‘158 Patent.
`
`C.
`
`Patent Owner
`
`According to the USPTO on-line assignment database, the ‘158 Patent is
`
`owned by Pixel Velocity Incorporated. (Ex. 1014) USPTO Assignment Record.
`
`However, in the above-referenced litigation, QuickCompile IP, LLC asserts that it
`
`is the “assignee and owner of the right, title and interest in and to the ‘158 and ‘699
`
`1
`
`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`Patents, including the right to assert all causes of action arising under said patents
`
`and the right to any remedies for their infringement.” (Ex. 1015) QuickCompile
`
`Complaint at ¶16. For purposes of this proceeding, both parties will be served and
`
`identified as the Patent Owner until otherwise notified.
`
`D. Lead and Back-up Counsel and Service Information
`Lead Counsel
`Back-up Counsel
`David M. O’Dell
`David L. McCombs
`Phone: (972) 739-8635
`HAYNES AND BOONE, LLP
`david.odell.ipr@haynesboone.com
`Phone: (214) 651-5533
`USPTO Reg. No. 42,044
`david.mccombs.ipr@haynesboone.com
`USPTO Reg. No. 32,271
`
`of the law firm:
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, Texas 15819
`Fax: (214) 200-0853
`
`Henry L. Welch
`HAYNES AND BOONE, LLP
`Phone (650) 687-8883
`henry.welch.ipr@haynesboone.com
`USPTO Reg. No. 65,516
`
`Gregory P. Huh
`HAYNES AND BOONE, LLP
`Phone: (972) 739-6939
`gregory.huh.ipr@haynesboone.com
`USPTO Reg. No. 70,480
`
`Jeffrey E. Danley
`SIMPSON THACHER & BARTLETT LLP
`2475 Hanover Street
`Palo Alto, CA 94304
`Phone: (650) 251-5072
`Fax: (650) 251-5002
`jdanley@stblaw.com
`USPTO Reg. No. 57,228
`
`2
`
`
`
`Petition for Inter Partes Review of U.S. 7,073,158
`
`Please address all correspondence to lead and back-up counsel. Petitioner
`
`consents to electronic service by email.
`
`II.
`
`CERTIFICATION OF GROUNDS FOR STANDING
`
`Petitioner certifies pursuant to Rule 42.104(a) that the ‘158 Patent for which
`
`review is sought is eligible for inter partes review and that Petitioner is not barred
`
`or estopped from requesting inter partes review challenging the patent claims on
`
`grounds stated in the petition.
`
`III. OVERVIEW OF THE ‘158 Patent
`
`Specification and Claims of the ‘158 Patent
`A.
`An overview of the relevant technology is provided by Dr. Walker in his
`
`declaration. Declaration of Dr. Martin G. Walker (Ex. 1004, hereinafter “Walker
`
`Dec.”) at ¶¶ 24-37.
`
`The ‘158 Patent describes “an FPGA-based image processing platform
`
`architecture that is capable dramatically speeding up the development of user-defined
`
`algorithms, such as those found in image processing applications.” ‘158 Patent at
`
`2:59-62. Walker Dec. ¶ 38.
`
`According to the ‘158 Patent, an FPGA is a type of programmable integrated
`
`circuit device that includes a number of configurable logic blocks (CLBs) and further
`
`includes an input port through which a bit stream can be received for configuring the
`
`CLBs, thereby programming the device. Id. at 5:49-6:63. The ‘158 Patent further
`
`3
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`notes that FPGAs were well known in the prior art, as was programming the devices
`
`from a set of user-provided algorithms (also referred to as source code). Id. at 9:25-26,
`
`11:13-25; 17:20-45; Walker Dec. ¶ 39.
`
`With reference to Fig. 5, reproduced below, the ‘158 Patent describes
`
`“automatically converting [user-specified algorithms] from a source code 22 to a
`
`field programmable gate array 24.” Id. at 9:53-55; Walker Dec. ¶ 40.
`
`‘699 Patent FIG. 5
`
`From left to right, Fig. 5 starts with a user-defined algorithm specified in a
`
`source code 22. Id. at 11:16-17. The source code 22 is a high-level software
`
`program that “describes the intended operation of the eventual FPGA 24.” Id. at
`
`9:56-57. These intended operations are “selected by a user from referring to a suitable
`
`image class library of functions …The image class libraries implement standard
`
`functions, including Boolean functions and neighborhood morphological functions
`
`and various gray scale functions and binary functions.” Id. 11:18-23. Notably, and as
`
`recognized by the ‘158 Patent, it was well-known to specify user-defined algorithms
`
`4
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`in source code for programming FPGAs, including the use of vectors. Id. at 3:8-14,
`
`9:25-27, and 11:13-15; Walker Dec. ¶¶ 41-43.
`
`With continued reference to Fig. 5, the source code 22 is provided to analyzer
`
`26. The analyzer 26 uses “standard compiler technology to parse the language of the
`
`source code 22.” ‘158 Patent at 9:62-64. The ‘158 Patent further explains:
`
`The analyzer module 26 processes the source code to identify vector
`elements within the source code and to provide a dataflow graph that
`indicates the overall processing vector processing flow and operation
`sequence within the source code 22. The dataflow graph is a specific
`implementation of the user-specified functions listed in the syntax tree
`associated with the high-level language in which the user writes his or
`her algorithms. In one example,
`the analyzer module identifies all
`operators and vector operands within the source code 22. Id. at 10:2-
`10:14; see also id. at 11:33-36. Walker Dec. ¶¶ 44-45.
`
`The output of the analyzer 26 is then provided to the mapper 28. See Fig. 5,
`
`above. “[T]he mapper program [then] takes the image processing operations specified
`
`in the user program and maps them into suitable hardware structures which can be
`
`used by the target FPGA and its bit stream software to generate the programmed
`
`FPGA.” ‘158 Patent at 11:40-44. “[T]he mapper elaborates the abstract flow graph
`
`operations into the physical operator blocks.” Id. at 15:4-6; Walker Dec. ¶¶ 46-47.
`
`The mapper 28 then provides its output as a low-level file to program the
`
`FPGA. ‘158 Patent at 11:50-55. Programming the FPGA is a process that uses
`
`5
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
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`“conventional” and “well-known” programming software and/or hardware tools for
`
`first generating a bit stream that contains the user-defined algorithm and second
`
`writing the bit stream to the FPGA. Id. at 6:64-7:7, 11:50-67, 17:33-36; Walker Dec.
`
`¶¶ 48-49.
`
`Of challenged claims 1-20, claim 1 is the only independent claim, and is
`
`provided below. Claim 1 is a method claim that includes four different claim
`
`elements, the first two being directed to functions of the analyzer 26, and the latter
`
`two being directed to functions of the mapper 28 and a programming tool.
`
`B.
`
`Prosecution History of the ‘158 Patent
`
`The application of the ‘158 Patent was filed on May 19, 2003, and claims
`
`priority to a provisional application filed on May 17, 2002.
`
`The prosecution history is brief. In a first Office Action, the claims were
`
`rejected under §102 as anticipated by the prior art, and various dependent claims were
`
`6
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`rejected under §103 as obvious. (Ex. 1003) ‘158 Patent File History at 87-89. In a
`
`Response dated December 20, 2005, the Applicant provided a declaration of the sole
`
`named inventor swearing behind the prior art, and canceled pending claims and added
`
`a new set of 20 claims. Id. at 103-126. The Examiner then issued a Notice of
`
`Allowance on March 20, 2006. Id. at 137. The ‘158 Patent subsequently issued on
`
`July 4, 2006.
`
`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner requests that
`
`the Patent Trial and Appeal Board (“the Board”) review the accompanying prior
`
`art and analysis, institute a trial for inter partes review of claims 1-20 (all claims)
`
`of the ‘158 Patent, and cancel those claims as unpatentable under 35 U.S.C. § 103.
`
`A.
`
`Prior Art Printed Publications of the Present Petition
`
`The prior art of record shows that the above-described image processing
`
`system and method of the ‘158 Patent, which converts a user-defined algorithm
`
`specified in source code for programming an FPGA, was well known prior to the
`
`patent. Specifically, a group at Northwestern University, including Dr. Banerjee
`
`and Dr. Haldar (two of the authors of the prior art listed below), had developed a
`
`system called the “MATCH Compiler”, which takes an image processing user-
`
`defined algorithm, written in MATLAB source code, and converts the source code
`
`for programming an FPGA in the same way as claimed. The primary reference
`
`7
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`listed below as “Banerjee” teaches or suggests all of the elements of the
`
`independent claim, along with a majority of the dependent clams. The remaining
`
`references are used to provide additional implementation details applicable to the
`
`system described in Banerjee. The references presented in this petition were not
`
`cited during prosecution. Walker Dec. ¶¶ 50-65.
`
`Ex. 1005 (“Banerjee”): Banerjee, et al., A MATLAB Compiler For
`
`Distributed, Heterogeneous, Reconfigurable Computing Systems, 2000 IEEE
`
`Symposium on Field-Programmable Custom Computing Machines, 39-48, 2000,
`
`which is prior art under 102(b).
`
`Ex. 1006 (“Benkrid”): Benkrid, et al., High Level Programming for FPGA
`
`Based Image and Video Processing Using Hardware Skeletons, The 9th Annual
`
`IEEE Symposium on Field-Programmable Custom Computing Machines, 219-226,
`
`March 2001, which is prior art under 102(b).
`
`Ex. 1007 (“Haldar”): Haldar, et al., Scheduling Algorithms for Automated
`
`Synthesis of Pipelined Designs on FPGAs for Applications described in
`
`MATLAB, Proceedings of the 2000 International Conference on Compilers,
`
`Architecture, and Synthesis for Embedded Systems, 85-93, 2000, which is prior art
`
`under 102(b).
`
`Ex. 1008 (“Hammes”): Hammes, et al., Cameron: High Level Language
`
`Compilation for Reconfigurable Systems, 1999 International Conference on
`
`8
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
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`Parallel Architectures and Compilation Techniques, 236-244, 1999, which is prior
`
`art under 102(b).
`
`Ex. 1016 (“Grant”): U.S. Patent No. 5,971,595 (“Grant”), was filed on
`
`April 28, 1997, and issued on October 26, 1999, which is prior art under 102(b).
`
`Ex. 1001 (“AAPA”): Applicants Admitted Prior Art (“AAPA), the ‘158
`
`Patent.
`
`B.
`
`Statutory Grounds for Challenge
`
`As explained below in the present petition, and also discussed in detail in the
`
`accompanying Declaration of Dr. Martin G. Walker (Ex. 1004) filed herewith, each
`
`element in challenged claims 1-20 (all claims) of the ‘158 Patent is described in the
`
`prior art, and the combinations would have been obvious to the person of ordinary
`
`skill. Thus, combinations of the references presented in the below grounds
`
`demonstrate that the challenged claims of the ‘158 Patent are unpatentable under 35
`
`U.S.C. § 103(a).
`
`Ground I: Claims 1, 2, 4, 9, 16, and 18-20 are unpatentable under 35 U.S.C. §
`
`103(a) over Banerjee and Benkrid;
`
`Ground II: Claims 3, 5, 7, and 8 are unpatentable under 35 U.S.C. § 103(a)
`
`over Banerjee, Benkrid, and Haldar;
`
`Ground III: Claim 6 is unpatentable under 35 U.S.C. § 103(a) over Banerjee,
`
`Benkrid, Haldar, and Hammes;
`
`9
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`Ground IV: Claims 10-13 and 17 are unpatentable under 35 U.S.C. § 103(a)
`
`over Banerjee, Benkrid, and AAPA; and
`
`Ground V: Claims 14 and 15 are unpatentable under 35 U.S.C. § 103(a) over
`
`Banerjee, Benkrid, AAPA, and Grant.
`
`C.
`
`Requested Relief
`
`Petitioner asks that the Board review the accompanying prior art and analysis,
`
`institute a trial for inter partes review of claims 1-20 (all claims) of the ‘158 Patent,
`
`and cancel those claims as invalid.
`
`V.
`
`CLAIM CONSTRUCTION
`
`Petitioner presents this claim analysis in a manner that is consistent with the
`
`broadest reasonable construction in light of the specification. See 37 C.F.R.
`
`§ 42.100(b). 1 Under the broadest reasonable construction standard, claim terms are
`
`given their ordinary and accustomed meaning as would be understood by one of
`
`ordinary skill in the art in the context of the disclosure, unless the inventor, as a
`
`lexicographer, has set forth a special meaning for a term. In re Translogic Tech.,
`
`Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007); Multiform Desiccants, Inc. v. Medzam,
`
`1 Petitioner reserves the right to pursue different constructions in a district court,
`
`where a different standard is applicable. See Samsung Elecs. Co., Ltd. v. Va. Innov.
`
`Scis., Inc., IPR2013-00569, Paper 9 at *2, Oct. 30, 2013.
`
`10
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`
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998).
`
`All claim terms not discussed below are to be given their broadest reasonable
`
`interpretation, as understood by one of ordinary skill in the art consistent with the
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`
`“analyzing”
`A.
`Claim 1 recites “analyzing” the user-defined algorithm. This term should be
`
`construed to mean “compiling and parsing.” Walker Dec. ¶ 67.
`
`The proposed construction is consistent with the ‘158 Patent, which describes
`
`analyzing the user-defined algorithm using “standard compiler technology to parse the
`
`language of the source code.” ‘158 Patent at 9:62-64. Further, the proposed
`
`construction is consistent with how a skilled artisan would have generally understood
`
`this term. See e.g., (Ex. 1017) Webster’s II, New College Dictionary, 1999 at 40
`
`(“Analyze – to separate into elemental parts or basic principles so as to determine the
`
`nature of the whole.”) Walker Dec. ¶ 68.
`
`Therefore, under the broadest reasonable construction, the term “analyzing”
`
`should be construed to mean “compiling and parsing.” Walker Dec. ¶ 69. To the
`
`extent the Board adopts a different construction, Petitioner submits that “compiling
`
`and parsing” is an example of “analyzing.”
`
`11
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`Petition for Inter Partes Review of U.S. 7,073,158
`
`VI.
`
`IDENTIFICATION OF GROUNDS FOR PETITION
`
`Pursuant to Rule 42.104(b)(4)-(5), the below sections, and as confirmed in
`
`the Declaration of Dr. Martin G. Walker, demonstrate in detail how the prior art in
`
`the present petition renders obvious each and every limitation of claims 1-20 of the
`
`‘158 Patent under 35 U.S.C. § 103(a). The present petition provides five grounds
`
`(Ground I-V) for finding claims 1-20 (all claims) of the ‘158 Patent unpatentable.
`
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`
`between the claimed subject matter and the prior art are such that the subject
`
`matter, as a whole, would have been obvious at the time the invention was made to
`
`a person having ordinary skill in the art to which said subject matter pertains. KSR
`
`Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007).
`
`The level of ordinary skill in the art may be reflected by the prior art of
`
`record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re
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`GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); see also Walker Dec. ¶ 22.
`
`A prima facie case of obviousness is established when the prior art itself
`
`would appear to have suggested the claimed subject matter to a person of ordinary
`
`skill in the art. In re Rinehart, 531 F.2d 1048, 1051 (CCPA 1976). Notably, prior
`
`art references must be “considered together with the knowledge of one of ordinary
`
`skill in the pertinent art.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994)
`
`(quoting In re Samour, 571 F.2d 559, 562 (CCPA 1978)). Moreover, “it is proper
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`Petition for Inter Partes Review of U.S. 7,073,158
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`to take into account not only specific teachings of the reference but also the
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`inferences which one skilled in the art would reasonably be expected to draw
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`therefrom.” In re Preda, 401 F.2d 825, 826 (CCPA 1968). That is because an
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`obviousness analysis “need not seek out precise teachings directed to the specific
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`subject matter of the challenged claim, for a court can take account of the
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`inferences and creative steps that a person of ordinary skill in the art would
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`employ.” KSR, 550 U.S. at 418; see also In re Translogic Tech., Inc., 504 F.3d at
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`1259.
`
`Ground I: Claims 1, 2, 4, 9, 16, and 18-20 are unpatentable under 35
`A.
`U.S.C. § 103(a) over Banerjee and Benkrid
`Independent Claim 12
`
`1.
`
`1.0 “A method for programming a field programmable gate array
`(FPGA) comprising”
`Banerjee teaches a method for programming a FPGA, as recited in the
`
`preamble. In more detail, Banerjee teaches utilizing a program called the MATCH
`
`Compiler for automatically compiling and parsing MATLAB source code to
`
`generate binary configurations for FPGAs.
`
`2 The elements of claim 1 will be annotated with the numbers “1.0” – “1.4” for
`
`the sake of later cross-reference.
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`Petition for Inter Partes Review of U.S. 7,073,158
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`the MATCH (MATlab Compiler
`for
`of
`objective
`The
`compiler
`at
`computing
`systems)
`project
`Heterogeneous
`Northwestern University is to make it easier for the users to
`develop
`efficient
`code
`for
`distributed,
`heterogeneous,
`reconfigurable computing systems. Towards this end we are
`implementing and evaluating an experimental prototype of a
`software system that will take MATLAB descriptions of various
`applications, and automatically map them on to… field-
`programmable gate arrays built from commercial off-the-shelf
`components. Banerjee at 1; see also, Walker Dec. ¶ 71.
`
`As will be described in detail below with regard to the corresponding claim
`
`elements, MATLAB is a high-level language that supports vectors and vector
`
`processing operations. Id. at Abstract. The MATCH compiler automatically
`
`partitions and maps a user defined algorithm in MATLAB to hardware components
`
`and produces a bit stream to program an FPGA (such as a Xilinx 4010 FPGA).
`
`Banerjee at 6 (“Finally, these generated programs are compiled using the
`
`respective target compilers to generate the executable/configuration bit
`
`streams.”); Walker Dec. ¶ 72.
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`Petition for Inter Partes Review of U.S. 7,073,158
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`Banerjee, FIG. 3 (annotated)
`It is noted that Benkrid also teaches a system for programming a FPGA.
`
`Benkrid describes using “Hardware Skeletons” for programming an FPGA based
`
`on “efficient FPGA based Image Processing algorithms.” Benkrid at 1, Abstract.
`
`FIG. 3 of Benkrid, reproduced below, shows how a user-defined algorithm with
`
`one or more skeletons can be used to program an FPGA, for example, a Xilinx
`
`XC4000 FPGA. Benkrid at 3; Walker Dec. ¶ 73.
`
`Benkrid, FIG. 3 (annotated)
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`Petition for Inter Partes Review of U.S. 7,073,158
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`A person of ordinary skill in the art would have understood that the bit
`
`streams of both Banerjee and Benkrid program the FPGA. (Ex. 1009) Xilinx Data
`
`Book at 54 (“An existing XC4000 bitstream can be used to program an XC4000E
`
`device.”); Walker Dec. ¶ 74 . Reasons to combine Banerjee and Benkrid are
`
`provided below at element 1.3.
`
`Therefore, Banerjee teaches or suggests the preamble of claim 1. Walker
`
`Dec. ¶ 75.
`
`1.1 “accepting a user-defined algorithm specified in a source code
`of a high level language and designed to process data vectors with
`one, two, or more dimensions;”
`
`Banerjee teaches accepting the MATLAB source code. Banerjee at 1
`
`(“Compilation Overview, The first step in producing parallel code from a
`
`MATLAB program involves parsing the input MATLAB program based on a
`
`formal grammar and building an abstract syntax tree.”); id. at Abstract; id. at 1;
`
`Walker Dec. ¶ 76.
`
`Further, Banerjee teaches that a user-defined algorithm is specified in the
`
`MATLAB source code (a high-level language) which is designed to process data
`
`vectors with at least one dimension. Banerjee at 1 (“MATLAB provides a very
`
`high level language abstraction to express computations in a functional style.”);
`
`id. at 3 (“MATLAB also supports language constructs using…vector notation
`
`and the like.”); id. (“For example, when the compiler sees a MATLAB statement a
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`Petition for Inter Partes Review of U.S. 7,073,158
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`= b * c, it might mean one of several things: a, b, c are scalar variables (either
`
`integer, or short, or float, or double-precision); or a can be a one-dimensional
`
`vector, b can be a two-dimensional matrix, and c can be a one-dimensional
`
`vector.”). A person of ordinary skill in the art would have understood that a two-
`
`dimensional matrix, as disclosed by Banerjee, is a two-dimensional vector. Walker
`
`Dec. ¶¶ 76-81.
`
`Thus, Banerjee’s disclosure of the MATCH Compiler receiving as input a
`
`user defined algorithm specified in MATLAB source code designed to process a
`
`data vector with at least one dimension teaches or suggests this limitation of claim 1.
`
`Walker Dec. ¶ 82.
`
`1.2 “analyzing the user-defined algorithm, including identifying
`the vector processing operations of the source code;”
`
`Banerjee teaches compiling and parsing the MATLAB source code to
`
`identify vector processing operations of the MATLAB source code. Banerjee at 3
`
`(“Compilation Overview, The first step …involves parsing the input MATLAB
`
`program based on a formal grammar and building an abstract syntax tree.”); id. at
`
`2 (“MATLAB is basically a function oriented language and most of the MATLAB
`
`programs can be written using pre-defined functions. These functions can be
`
`primitive functions or application specific.”); id. at 3 (“Some of the functions…
`
`include matrix addition, matrix multiplication, one dimensional FFT and
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`FIR/IIR filters.”); id. (“For example, when the compiler sees a MATLAB
`
`statement a = b * c… a can be a one-dimensional vector, b can be a two-
`
`dimensional matrix, and c can be a one-dimensional vector…Clearly, when a
`
`compiler has to generate the code, the correct type needs to be declared or
`
`inferred by the compiler. Our compiler provides mechanisms to automatically
`
`perform such inferencing”) A person of ordinary skill in the art would have
`
`understood that the vector processing operations of the source code described
`
`above are identified (seen/inferred) by the MATCH compiler during parsing.
`
`Walker Dec. ¶¶ 83-88.
`
`To the extent that Patent Owner argues that the identified “vector processing
`
`operations” are loop statements, Banerjee teaches this also. See Banerjee at 5 and
`
`Fig. 4 (“Control statements such as IF-THEN-ELSE constructs in MATLAB are
`
`converted into corresponding IF-THEN-ELSE constructs in VHDL. Assignment
`
`statements in MATLAB are converted into variable assignment statements in
`
`VHDL. Loop control statements are converted into a finite state machine as shown
`
`in Figure 4.”); Walker Dec. ¶¶ 89-91.
`
`To the extent that Patent Owner argues that the analyzer algorithm may include
`
`analysis of “the runtime behavior of the user’s program,” my review of the ‘158
`
`Patent indicates that any such analysis of the runtime behavior is directed to
`
`determining the sequencing and timing among the vector processing operations in the
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`Petition for Inter Partes Review of U.S. 7,073,158
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`source code, the analysis of claims 5, 6, and 8 teach such analysis. Walker Dec. ¶¶ 92-
`
`93.
`
`Thus, Banerjee’s teaching of compiling and parsing the MATLAB source
`
`code identify (see/infer) vector processing operations of the MATLAB source
`
`code, teaches or suggests this limitation of claim 1. Walker Dec. ¶ 94.
`
`1.3 “mapping the vector processing operations onto logic
`components of an FPGA;”
`
`Banerjee teaches developing pre-designed physical operator blocks (in RTL
`
`VHDL) that are made up of logic components. Banerjee at 3 (“We describe our
`
`effort in the development of various MATLAB libraries…These functions are
`
`developed in Register Transfer Level (RTL) VHDL, using Synplify logic
`
`synthesis tools…Some of the functions we have developed on the FPGA board
`
`include matrix addition, matrix multiplication, one dimensional FFT and
`
`FIR/IIR filters.”) A person of ordinary skill in the art would have understood that the
`
`pre-designed operator blocks (functions) are at the physical level and include logic
`
`components since they are developed in RTL VHDL using logic tools and perform
`
`matrix addition, multiplication, FFT, and FIR/IIR filtering functions. See ‘158 Patent
`
`at 3:15-17; Walker Dec. ¶¶ 95-98.
`
`Banerjee further teaches mapping vector processing operations onto the pre-
`
`designed functions of the FPGA. Banerjee at 6 (“When possible, the MATCH
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`Petition for Inter Partes Review of U.S. 7,073,158
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`Compiler tries to automatically map the user program on to the target
`
`machine…We have developed an automatic mapping tool called SYMPHANY [5]
`
`which takes as input (a) control and data flow graph of a MATLAB program which
`
`represents various MATLAB functions as nodes (b) Characterizations of the
`
`MATLAB functions on various resources such as single or multiple FPGAs.”)
`
`Walker Dec. ¶¶ 99-100.
`
`Moreover, in a similar field of endeavor, Benkrid supplements the teaching
`
`of Banerjee and provides specific examples of pre-designing physical operator
`
`blocks within a hardware skeleton library for commonly used image processing
`
`operations specified in a high level language optimized for logic components of
`
`FPGAs. Benkrid at 7 (“In this paper, we have presented a framework for FPGA
`
`based Im
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