(19) Japan Patent Office
`(JP)
`
`(12) Japanese Unexamined Patent
`Application Publication (A)
`
`
`
`(11) Japanese Unexamined Patent
`Application Publication Number
`H06-52696
`(43) Publication date February 25, 1994
`Theme codes (reference)
`
`(51) Int. Cl.5
`Identification codes JPO Internal No.
`
`G11C 29/00 301 B
`6741-5L
`
`11/401
`
`371 D
`G11C 11/34
`6741-5L
`Request for examination Not Requested Number of claims 6 (Total of 10 pages)
`
` FI
`
`
`
`Identification no. 000003078
`Toshiba Corp.
`72 Horikawacho, Saiwai-Ku, Kawasaki
`City, Kanagawa Prefecture, Japan
`MINAMI Naoaki,
`c/o Toshiba Corp., Semiconductor Systems
`Technology Center, 580-1 Horikawacho,
`Saiwai-Ku, Kawasaki City, Kanagawa
`Prefecture, Japan
`
`WATANABE Shigeyoshi c/o, Toshiba
`Corp., Central Research Institute, 1
`Komukaitoshibacho, Saiwai-Ku, Kawasaki
`City, Kanagawa Prefecture, Japan
`SUZUE Takehiko
`
`(71)
`Applicant
`
`(72)
`Inventor
`
`
`
`(72)
`Inventor
`
`(21) Application
`number
`(22) Date of application
`
`
`Japanese Patent Application
`H04-204765
`July 31, 1992
`
`
`
`
`
`
`(74) Agent
`
`
`
`
`
`reading/writing is executed on the defective regular
`memory cell connected to the regular bit lines BLj
`including a defective memory cell, the spare bit line
`SBL is driven instead of the BLj.
`
`
`
`54 TITLE OF THE INVENTION
`SEMICONDUCTOR MEMORY DEVICE
`
`ABSTRACT
`57
`PURPOSE: A contrivance at reducing the chip area
`and improving the yield by raising rescue efficiency
`and the success rate of rescue of defective memory
`cells.
`CONSTITUTION: This semiconductor memory device
`is provided with plural regular memory cells arranged
`in a matrix, plural regular word lines WLi connected to
`regular memory cells, plural regular bit lines BLj
`connected
`to regular memory cells, plural spare
`memory cells connected to regular word lines WLi, and
`a spare bit line SBL connected to the spare memory
`cells, characterized by when reading/ writing
`is
`executed on the normal regular memory cell connected
`to the regular bit lines BLj including a defective
`is driven, and when
`the BLj
`memory cell,
`
`
`
`
`
`MICRON-1006.001
`
`

`
`Scope of the Patent Claims
`Claim 1
`A semiconductor memory device equipped with plural
`regular memory cells arrayed in a matrix, and plural regular
`word lines connected to these regular memory cells, and
`plural regular bit lines connected to said regular memory
`cells, and plural spare memory cells connected to said regular
`word lines, and spare bit lines connected to these spare
`memory cells, characterized by the regular bit line being
`driven when there is the performance of write-in or read-out
`to/from a normal regular memory cell connected to a regular
`bit line including a defective memory cell, and a spare bit line
`being driven to replace the regular bit line when there is the
`performance of write-in or read-out to/from a defective
`regular memory cell connected to a regular bit line including
`a defective memory cell.
`Claim 2
`The semiconductor memory device claimed in claim 1
`characterized by when there are plural defective memory
`cells, and no two of these are on the same regular word line,
`then normally the same spare bit line is driven instead of the
`regular bit line connected to the defective memory cell.
`Claim 3
`A semiconductor memory device equipped with plural
`regular memory cells arrayed in a matrix, and plural regular
`word lines connected to these regular memory cells, and
`plural regular bit lines connected to said regular memory
`cells, and plural spare memory cells connected to said regular
`word lines, and spare word lines connected to these spare
`memory cells, characterized by the regular word line being
`driven when there is the performance of write-in or read-out
`to/from normal regular memory cells connected to a regular
`word line including a defective memory cell, and a spare
`word line being driven to replace the regular word line when
`there is the performance of write-in or read-out to/from a
`defective regular memory cell connected to a regular word
`line including a defective memory cell.
`Claim 4
`The semiconductor memory device claimed in claim 3
`characterized by when there are plural defective memory
`cells, and no two of these are on the same regular bit line,
`then normally the same spare word line is driven instead of
`the regular word line connected to the defective memory cell.
`Claim 5
`A semiconductor memory device equipped with plural
`regular memory cells arrayed in a matrix, and plural regular
`word lines connected to these regular memory cells, and
`plural regular bit lines connected to said regular memory
`cells, and a first spare memory cell connected to said regular
`word line, and a spare bit line connected to the first spare
`memory cell, and a second spare memory cell connected to
`said regular bit line, and a spare word line connected to the
`second spare memory cell, characterized by driving the
`regular bit line and the regular word line connected to a
`normal regular memory cell when there is the performance of
`write-in or read-out to/from said normal regular memory cell,
`and driving a regular word line and a spare bit line connected
`to a defective memory cell when performing write-in/read-
`out to/from said defective memory cell.
`Claim 6
`A semiconductor memory device providing peripheral
`circuits comprising an m unit configuration of unit circuits
`
`Japanese Unexamined Patent Application Publication H06-52696
`(2)
`
`connected to one each of k types of circuits, characterized by
`said peripheral circuits being comprised of a matrix disposing
`m + n units of the same type of circuit in the line direction,
`and disposing different k types of circuits in the row direction,
`and switching circuits which switch over the row direction
`disposed before/after each circuit, and connecting k types of
`circuits in the row direction detouring past the defective
`circuit by means of said switching circuit.
`
`Detailed Description Of The Invention
`[0001]
`Technical Field Of The Invention
`The present invention relates to semiconductor memory
`devices such as dynamic RAM (DRAM), in particular to
`semiconductor memory devices providing defect rescue
`functions of memory cells and peripheral circuits.
`[0002]
`Prior Art
`Plural memory cells are arrayed in a matrix in DRAM
`memory cells, and the selection of memory cells is performed
`by means of the selection of the line (word line) and row (bit
`line). Defective cells generated in memory cell arrays are
`rescued by means of replacement by spare cells prepared in
`advance. Conventionally, as
`this
`rescue method,
`the
`replacement was performed for row or line units and
`replacement was not performed at the cell unit level. In other
`words, columns or lines which included even one defective
`cell were treated as an entirely defective row or line
`(hereafter, this kind of row and line are called defective rows
`and defective lines), and a method was used where they were
`changed out for spare rows (reserve columns) or spare line
`(reserve lines).
`[0003]
`Hereafter, the conventional method of performing the rescue
`of defects at the row unit level is explained. Now, the rescue
`of defects at the line level was performed in the same manner.
`In Fig. 12, the redundancy circuit means in order to perform
`relief of defects at the row unit level in DRAM is represented.
`Memory cell arrays have four regular bit lines BL0, BL1,
`BL2, BL3, and a spare bit line SBL, in addition to comprising
`four regular word lines WL0, WL1, WL2, WL3. The regular
`memory cell selected by means of the word line WLi and the
`regular bit line BLj, and the spare memory cell selected by
`the spare bit line SBL comprise the SCi. The row address is
`input from the address lines A0,/A0, A1,/A1 (/A is an
`inverted output), and one of the regular bit lines is selected by
`means of the column decoders CD0, CD1, CD2 and CD3 in
`correspondence with the input address. When there is a defect
`in a regular bit line, that address is recorded in the spare
`decoder SD.
`[0004]
`Because the spare decoder SD is comprised of a MOS
`transistor and a fuse and the like, the recording of the address
`of the defective bit line is performed by severing the fuse in
`correspondence with the address. Then, when the input
`address correspondence to the defective line address, a
`current or voltage VCC is output in respect of the inverter I0,
`and when there is no correspondence, then 0V is output.
`When VCC is input, the inverter I0, outputs 0V to each
`column decoder to inactivate the regular bit lines, as well as
`to activate the spare bit line SBL via the inverter I1, and
`
`
`
`MICRON-1006.002
`
`

`
`when 0V is input, the spare bit lines are inactivated, and the
`regular bit lines selected by the column decoder are activated.
`[0005]
`The conventional defect relief methods as explained above
`have the following problems. Firstly, because containing
`even one defective cell is treated as an entirely defective row,
`unnecessary relief is performed in respect of normal cells in
`the defective row. For example, as illustrated in Fig. 13 (a),
`when the cell C11 is defective, the bit line BL1 is treated as
`defective in its entirety, and is changed out for the spare bit
`line SBL. For that reason, the C01, C21 and C31 cannot be
`used, even if they are normal.
`[0006]
`Moreover, because the spare row is employed for the relief of
`specific defective cells, depending on the distribution of the
`defects, as illustrated in Fig. 13 (b), there is a requirement for
`the same number of spare bits lines as the number of
`defective cells. In addition, as illustrated in Fig. 13 (c), when
`there are defective cells even in the spare columns, the rescue
`of the defects of regular cells is not enabled.
`[0007]
`On the other hand, in tandem with the densification of the
`DRAM and the miniaturization of elements, the fluctuation of
`the threshold of the transistors as a result of the short channel
`effect or the fluctuation in the distribution of impurities
`becomes great, and because there is an additional increase in
`the number of circuits and the number of elements, defects
`can be expected to be generated not only the memory cells,
`but also in the peripheral circuits. The peripheral circuits are
`comprised of sense amp drivers, DQ buffers, sense amp
`equalizers, column decoders, and spare decoders, and in
`particular the sense amp drivers, DQ buffers, sense amp
`equalizers are mutually connected and perform operations in
`series. Therefore, the defect relief of these circuits is not
`merely the changing out of the defective circuits for spare
`circuits, the connections between the circuits must be
`maintained. For example, in the event that there is a change
`out of a DQ buffer, the spare DQ buffer employed as the
`replacement must be connected to the sense amp driver and
`the sense amp equalizer which was connected to the defective
`DQ buffer.
`[0008]
`Fig. 14 represents an embodiment of the redundancy format
`of the peripheral circuits by means of the conventional
`methods. One each of a sense amp driver, a DQ buffer and a
`sense amp equalizer are connected in one circuit unit for use,
`and Fig. 14 (a) represents the situation where one spare unit
`is provided. Because the defects of a memory cell are rescued
`by the rescue of a bit line or a word line unit, and not by cell
`units in this embodiment, rescue is not performed for sense
`amp driver units, DQ buffer units or sense amp equalizer
`units.
`[0009]
`In this type of conventional redundancy format, as illustrated
`in Fig. 14 (b), when there is distribution of defects, three
`units of the circuits connecting one each of the sense amp
`driver, the DQ buffer and a sense amp equalizer are necessary,
`increasing the chip area by a large margin.
`[0010]
`Problems To Be Solved By The Invention
`In this manner, in the rescue methods of conventional
`memory cells, because there is change out with spare cells for
`the unnecessary relief of normal cells, and a large volume of
`spare cells are required in respect of all of the defective cells
`
`Japanese Unexamined Patent Application Publication H06-52696
`(3)
`
`which should be rescued, the rescue efficiency is very poor.
`Furthermore, because not even one defective cell can be
`permitted in the spare column, the success rate of relief is
`also poor. Moreover, even in the relief method of the
`peripheral circuits, there is change out using spare circuits in
`respect of peripheral circuits which do not need to be relieved,
`resulting in poor rescue efficiency.
`[0011]
`in
`invention was conceived of
`the present
`Because
`consideration of these facts, the object of the invention is the
`provision of a semiconductor memory device enabling high
`rescue efficiency and rescue success rates of defective
`memory cells and periphery circuits, enabling miniaturization
`of the surface area of chips and improved yields.
`[0012]
`Means for Solving the Problem
`The core of the present invention is the replacement of
`defective memory cells or peripheral circuits with spare cells
`or spare circuits, and not the replacement of normal memory
`cells or peripheral circuits which do not need to be relieved.
`[0013]
`In other words, the present invention (Claim 1) is a
`semiconductor memory device equipped with plural regular
`memory cells arrayed in a matrix, and plural regular word
`lines connected to these regular memory cells, and plural
`regular bit lines connected to said regular memory cells, and
`plural spare memory cells connected to said regular word
`lines, and spare bit lines connected to these spare memory
`cells, characterized by the regular bit line being driven when
`there is the performance of write-in or read-out to/from a
`normal regular memory cell connected to a regular bit line
`including a defective memory cell, and a spare bit line being
`driven to replace the regular bit line when there is the
`performance of write-in or read-out to/from a defective
`regular memory cell connected to a regular bit line including
`a defective memory cell.
`[0014]
`Moreover, the present invention (Claim 3) is a semiconductor
`memory device equipped with plural regular memory cells
`arrayed in a matrix, and plural regular word lines connected
`to these regular memory cells, and plural regular bit lines
`connected to said regular memory cells, and plural spare
`memory cells connected to said regular word lines, and spare
`word
`lines connected
`to
`these spare memory cells,
`characterized by the regular word line being driven when
`there is the performance of write-in or read-out to/from
`normal regular memory cells connected to a regular word line
`including a defective memory cell, and a spare word line
`being driven to replace the regular word line when there is
`the performance of write-in or read-out to/from a defective
`regular memory cell connected to a regular word line
`including a defective memory cell.
`[0015]
`is a
`(Claim 5)
`invention
`the present
`Furthermore,
`semiconductor memory device equipped with plural regular
`memory cells arrayed in a matrix, and plural regular word
`lines connected to these regular memory cells, and plural
`regular bit lines connected to said regular memory cells, and
`a first spare memory cell connected to said regular word line,
`and a spare bit line connected to the first spare memory cell,
`and a second spare memory cell connected to said regular bit
`line, and a spare word line connected to the second spare
`memory cell, characterized by driving the regular bit line and
`the regular word line connected to a normal regular memory
`
`
`
`MICRON-1006.003
`
`

`
`cell when there is the performance of write-in or read-out
`to/from said normal regular memory cell, and driving a
`regular word line and a spare bit line connected to a defective
`memory cell when performing write-in/read-out to/from said
`defective memory cell.
`[0016]
`is a
`(Claim 6)
`invention
`the present
`In addition,
`semiconductor memory device providing peripheral circuits
`comprising an m unit configuration of unit circuits connected
`to one each of k types of circuits, characterized by said
`peripheral circuits being comprised of a matrix disposing m +
`n units of the same type of circuit in the line direction, and
`disposing different k types of circuits in the row direction,
`and switching circuits which switch over the row direction
`disposed bore/after each circuit, and connecting k types of
`circuits in the row direction detouring past the defective
`circuit by means of said switching circuit.
`[0017]
`Effects
`By means of the present inventions (Claims 1, 3 and 5), on
`the occasion of reading-out and writing-in to a normal cell on
`a regular row (line) including a defective cell, that regular
`row (line) is activated, and there is no replacement with a
`spare row (line). Moreover, even if there are defective cells in
`multiple regular rows (lines), when no two of those defective
`cells are in the same line (row), one spare row (line) is
`sufficient for the rescue of the defects of multiple regular
`rows, by means of replacing with a regular row (line) using a
`spare row (line) in correspondence with the selected line
`(row) is enabled.
`[0018]
`In this manner, because there is no unnecessary replacement
`by spare cells with respect to normal cells on the defective
`row (line), the normal cells can be used efficiently. In
`addition, because the rescue of the defects of multiple regular
`rows (lines) is enabled with one spare row (line), good
`efficient rescue using very few spare rows (lines) is enabled.
`Furthermore, even if there are defective cells in the spare
`rows (lines) the performance of the rescue of the defects of
`regular cells is enabled.
`[0019]
`Moreover, by means of the present invention (Claim 6), when
`there are k types of circuits A, B, … K, and when there are m
`+ n units each including n units of spares of the same kind of
`circuit for each, an m unit configured circuit connecting one
`each of k types of circuits while avoiding n units of defects in
`each line is enabled.
`[0020]
`Embodiments
`Hereafter the present invention is explained based on the
`attached figures.
`[0021]
`Fig. 1 is a circuit configuration diagram representing the
`redundancy circuit means of DRAM related to the first
`embodiment of the present invention. In this embodiment, a
`regular memory cell array comprised of four lines by four
`rows and one spare row and the circuit for the control thereof
`are represented.
`[0022]
`The memory cell array is comprised of memory cells arrayed
`in a matrix, four regular bit lines BLJ (BL0, BL1, BL2, BL3)
`and a spare bit line SBL, in addition to comprising four
`regular word lines (WL0, WL1, WL2, WL3). The regular
`memory cells Cij selected by means of the word line WLi and
`
`Japanese Unexamined Patent Application Publication H06-52696
`(4)
`
`the regular bit line BLj, and the spare memory cell SCi
`selected by the word line WLi and the spare bit line SBL. The
`row address is input from the address lines A0,/A0, A1,/A1
`and one of the regular bit lines is selected by means of the
`in
`column decoders CD0, CD1, CD2
`and CD3
`correspondence with the input address. When there is a defect
`in a regular bit line, that address is recorded in the spare
`decoder SD.
`[0023]
`The spare decoder SD, unlike the conventional device
`represented in Fig. 12, is set for each word line WLi. The
`output of the spare decoders SDi (SD1, SD2, SD3 and SD4)
`is supplied to the inverter I0 via the NMOS transistors Ti (T0,
`T1, T2, T3) input by the word line WLi to the gate. Moreover,
`the input terminal of the inverter I0 is precharged with the
`power source voltage VCC by means of the PMOS transistor
`P. For that reason, when the input address corresponds to a
`defective line address, and when the word line of the
`defective cell is selected, the power source voltage VCC is
`output respect to the inverter I0, and when there is no
`correspondence then 0V is output. In other words, each spare
`decoder SDi records the address of defective regular cells on
`WLi.
`[0024]
`The inverter I0 not only inactivates the regular bit lines by
`outputting 0V to each column decoder when VCC is input, but
`also activates the spare bit line SBL via the inverter I1.
`Moreover, when 0V is input, the spare bit line is deactivated,
`and the regular bit line selected by the column decoder is
`activated.
`[0025]
`The specific configuration of the spare decoders is as
`illustrated in Fig. 2. Each of the NMOS transistors Ti0,/Ti0,
`Ti1,/Ti1 are connected by gates to the address lines A0,/A0,
`A1,/A1, and the drain of each transistor and the output node
`of SD are connected by the fuses Fi0,/Fi0, Fi1,/Fi1. The output
`node is connected to the input of the invertor I0, and
`precharged with the VCC by means of the PMOS transistor
`Pi. The recording of the address of the defective bit line is
`performed by means of the severance of the fuse connecting
`the transistor to the address line whose potential becomes
`VCC when that bit line is selected.
`[0026]
`For example, if the C11 connected to the bit line BL1 is
`defective, because the BL1 selection to input VCC to the
`address line A0 and /A1, the fuses F10 and /F11 are switched
`over. When the input address corresponds to the address of a
`defective bit line, in addition to when the word line WL1 of a
`defective cell is selected, because the output node is not
`grounded, the inverter I0 outputs VCC, and because the output
`node is grounded when the input address does not correspond,
`the Inverter I0 outputs 0V.
`[0027]
`Next, an explanation is provided of the operations of this
`embodiment. When the word line WLi is selected, the
`transistor Ti becomes conductive and there is connection of
`the output of the spare decoder SDi and the input of the
`inverter I0. When there is a defective cell CIJ on the word
`line WLi, and the spare decoder SDi records the address of
`the bit line BLj. When the bit line BLj is selected, there is no
`grounding of the input of the inverter I0 and the output of the
`spare decoder SDi, and the potential thereof is maintained at
`VCC. Therefore in this situation, instead of the regular bit line
`BLj, the spare bit line SBL is activated, and read-out and
`
`
`
`MICRON-1006.004
`
`

`
`writing-in is performed to the spare cell SCi. When the other
`bit line BLj’ (j ≠ j’) is selected, the output of SDi and the
`input of I0 are grounded, and the potential thereof becomes
`0V. Therefore in that situation, the regular bit line BLj is
`selected and read out on writing in to Cij is performed.
`[0028]
`A specific embodiment of the rescue of a defect by means of
`the method described above is represented in Fig. 3. In this
`embodiment, there are three defective cells C01, C10 and C22
`in the regular cell array comprised of four lines and four rows.
`In the conventional method, there was a requirement for three
`spare bits lines as illustrated in Fig. 13 (b), but if this
`embodiment is employed, one spare bit line is sufficient. In
`other words, as illustrated in Fig. 3 (a), when WL0 and BL1
`are selected, because C01 is defective, SBL is activated in
`place of BL1, and read-out and write-in is performed in
`respect of SC0. Here, the replacement of BL1 by SBL is not
`something which normally occurs, as illustrated in Fig. 3 (b),
`when WL3 and BL1 are selected, BL1 is activated and read-
`out and write-in is performed to the normal cell C31.
`[0029]
`Moreover, SBL can also rescue defects on bit lines other than
`BL1. As illustrated in Fig. 3 (c), when WL2 and BL2 are
`selected, SBL is activated instead of BL2, and read out and
`write-in is performed to SC2. In other words, each of the
`spare cells SCi of the spare bit line can rescue any of the
`defective cells of the word line WLi. Moreover, because
`there are no defective regular cells on WL3, even if the spare
`cell SC3 is defective, there is no failure of the rescue.
`[0030]
`By means of this type of embodiment, when reading out or
`writing in to a normal cell on the regular bit line BLj
`including a defective cell, that regular bit line BLj is
`activated, and there is no replacement by the spare bit line
`SBL. Moreover, even if there are defective cells in multiple
`regular bit lines BLj, when no two of those defective cells are
`on the same regular bit line BLj, one spare bit line SBL
`enables the rescue of defects on multiple regular bit lines BLj
`by means of changing out the regular bit line BLj by means
`of the spare bit line SBL in correspondence with the selected
`word line WLi. As a result of this, because there is no
`wasteful change out of spare cells in respect of normal cells
`on defective bit two lines, the efficient use of normal cells is
`enabled. Moreover, because the rescue of defects of multiple
`regular bit lines using only one spare bit line, efficient and
`good rescue is enabled with very few spare bits lines.
`Furthermore, even if there are defective cells in the spare bit
`lines, the performance of the rescue of defects of regular cells
`is enabled.
`[0031]
`Fig. 4 is a circuit configuration diagram representing the
`second embodiment. This embodiment combines multiple
`word lines in one block (BWL0, ~, BWLm), and provides one
`spare decoder (SD0, ~, SDm) to each of the blocks. When the
`probability of the occurrence of defects in memory cells is
`low, and when defective memory cells are not generated one
`to each word line, this method reduces the area of the spare
`decoder, and a more efficient and good rescue of defects is
`enabled.
`[0032]
`Fig. 5 is a circuit diagram representing the third embodiment
`of the present invention. This embodiment does not provide
`spare memory cells in the spare bit line, but provides spare
`memory cells in the spare word line.
`
`Japanese Unexamined Patent Application Publication H06-52696
`(5)
`
`[0033]
`The switching circuits SWj (SW0, SW1, SW2, SW3) are
`connected to the column decoder CDj, and every SWj is
`controlled by a spare line decoder SRDj (SRD0, SRD1, SRD3,
`SRD3). Each spare line decoder SRDj records the line
`address of the defective regular cells replaced by spare cells
`on the spare word line SWL found on the bit line BLj. Each
`regular bit line is divided in two, and one half is connected to
`a regular memory cell, and the other half is connected to a
`spare memory cell on the spare word line SWL. Then, SWj
`can more easily selectively activate either.
`[0034]
`If the configuration is as described above, when each spare
`input
`line address which
`line decoder SRDj has an
`corresponds to its own recorded address, the SWj operates,
`and the column decoder CDj is connected to the spare cell
`side of the bit line BLj. When another address is input, the
`CDj is connected to the regular cell side of the BLj.
`[0035]
`In other words, when there is read-out/write-in to normal cell
`on a regular word line WLj including a defective cell, that
`is selected, and
`there
`is no
`line WLj
`regular word
`replacement by the spare word line SWL, and only when
`there is read-out/write-in to/from the defective cell on the
`regular word line WLj including a defective cell is there
`replacement performed by the spare word line SWL. By this
`means, the rescue of the defects of plural regular word lines
`WLj with only one spare word line SWL is enabled, such
`that the same good efficiency as in embodiment 1 is enabled.
`[0036]
`the fourth
`is a circuit diagram representing
`Fig. 6
`embodiment of the present invention. The configuration of
`the memory cell array, column decoder, inverter and the
`address line are the same as that represented in the
`embodiment of Fig. 1. Spare column decoders SCDj (SCD0,
`SCD1, SCD2, SCD3) are connected with respect of the
`regular word line WLj in the same manner as in embodiment
`1, and the output thereof is connected to the inverter I0 via
`the NMOS transistor Ti. Each spare column decoder SCDi
`records the row address of defective regular cells replaced
`with spare cells on the spare bit line SBL which is on the
`regular word line WLi. The input of the inverter I0 is
`precharged to the power source voltage VCC by means of a
`PMOS transistor.
`[0037]
`A switching circuit SWj is connected to each column decoder,
`and each SWj is controlled by means of a spare line decoder
`SRDj, Each spare line decoder SRDj records the defective
`regular cell line address replaced by a spare cell on the spare
`word line SWL which is on the bit line BLj. Each regular bit
`line BLj is divided into two, and one side is connected to a
`regular memory cell, and the other is connected to a spare
`memory cell on a spare word line SWL. Then, the selection
`of the regular memory cell or the spare memory cell is
`performed by the SWj.
`[0038]
`In this embodiment, two types of rescue are possible by
`means of the spare bit line and the spare word line, but firstly
`the rescue of defects by means of the spare bit line SBL is
`explained. When a regular word line WLi is selected, the
`transistor Ti conducts and there is the connection of the
`output of the spare decoder SDi and the input of the inverter
`I0. When there is a defective cell Cij on the regular word line
`WLi, the spare column decoder SDi records the address of
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`MICRON-1006.005
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`the regular bit line BLj. When the regular bit line BLj is
`selected, the output of the spare column decoder SDi and the
`input of the inverter I0 are not grounded, and the potential
`thereof is maintained at VCC. Therefore, in this situation, the
`spare bit line SBL is activated instead of the regular bit line
`BLj, and there is the performance of read-out/write-in to the
`spare cell SCi. When other regular bit lines BLj’ (j ≠ j’) are
`selected, the output of the spare column decoder SDi and the
`input of the inverter I0 are grounded, such that the potential
`thereof becomes 0V. Therefore, in this situation, the regular
`bit line BLj is selected and read-out/write-in is performed to
`the regular cell Cij.
`[0039]
`Next, defect rescue by means of the spare word line SWL is
`explained. When the input line address corresponds to its
`own recorded address, each spare column decoder SRDj
`operates the switching circuit SWj and the column decoder
`CDj connects to the spare cell side of the regular bit line BLj.
`When another address is input, the column decoder CDj
`connects to the regular cell side of the regular bit line BLj.
`[0040]
`A specific embodiment of defect rescue by means of this
`method is represented in Fig. 7. There are three [sic]
`defective cells C00, C01, C12 and C21 in the regular cell array
`comprised of four lines and four rows. In the conventional
`method, three spare bit lines or three spare word lines would
`be required, but if this embodiment is implemented, only one
`spare bit line and one spare word line are needed. The
`defective cells C00, C01, are replaced by the spare cells on the
`spare word line SWL, the defective cells C12 and C21 are
`replaced by the spare cells on the spare bit line SBL. In this
`manner, even when there are multiple defective cells on the
`same word line or the same bit line, rescue by one spare word
`line SWL and one spare bit line SBL is enabled.
`[0041]
`Now, in the switchover method between the column decoder
`and the bit line, the following two methods are conceivable.
`In Fig. 8 (a) the sense amps 21 and 22 are provided on both
`of the divided regular cell side and the spare cell side, and the
`switching circuit 10 is provided between these and the
`input/output line. In that situation, because the sense amp is
`operated on
`the row address
`input side, high speed
`performance characteristics are not enabled. In Fig. 8 (b), the
`input/output line and the sense amp 20 are in series, and the
`switching circuit 10 is provided between the sense amp 20
`and the bit line. In that situation, because the sense amp is
`shared between the regular cell side and the spare cell side,
`increases in the area of the chip are suppressed.
`[0042]
`Fig. 9 is a circuit diagram representing the fifth embodiment
`of the present invention. There are five each of the sense amp
`drivers A (A1 ~ A5), the DQ buffers (B1 ~ B5) and the sense
`amp equalizers C (C1 ~ C5), and there are the switching
`circuits SW (SW11, SW11’,~ SW14, SW14’, ~, SW31, SW31’,~
`SW34, SW34’) straddling each line and switching between the
`sense amp drive A and the DQ buffer B, and between the DQ
`buffer B and the sense amp equalizer C is thereby enabled.
`Moreover, the fuses F (F11 ~ F15, ~, F31 ~ F35) are provided
`between a pair of SW in order to record the location of the