throbber
Trials@uspto.gov
`571-272-7822
`
`
`
`
`Paper 15
`Date Entered: May 4, 2016
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`AMERICAN MEGATRENDS, INC.,
`MICRO-STAR INTERNATIONAL CO., LTD,
`MSI COMPUTER CORP.,
`GIGA-BYTE TECHNOLOGY CO., LTD., AND
`G.B.T., INC.,
`Petitioner,
`
`v.
`
`KINGLITE HOLDINGS INC.,
`Patent Owner.
`____________
`
`Case IPR2016-00114
`Patent 5,937,200
`____________
`
`
`
`Before GLENN J. PERRY, TREVOR M. JEFFERSON, and
`BRIAN J. McNAMARA, Administrative Patent Judges.
`
`PERRY, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
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`I. INTRODUCTION
`American Megatrends, Inc., Micro-Star International Co., Ltd., MSI
`Computer Corp., Giga-Byte Technology Co., Ltd., and G.B.T., Inc.,
`(collectively, “Petitioner”) filed a Petition, Paper 6 (“Pet.”), to institute an
`inter partes review of claims 9 and 19–23 (“the challenged claims”) of U.S.
`Patent No. 5,937,200 (“the ’200 patent”). 35 U.S.C. § 311. Kinglite
`Holdings, Inc. (“Patent Owner”) timely filed a Preliminary Response, Paper
`13 (“Prelim. Resp.”), contending that the Petition should be denied as to all
`challenged claims.
`We have jurisdiction under 35 U.S.C. § 314(a), which provides that an
`inter partes review may not be instituted unless the information presented in
`the Petition shows “there is a reasonable likelihood that the petitioner would
`prevail with respect to at least 1 of the claims challenged in the petition.”
`Upon consideration of the Petition, Patent Owner’s Preliminary
`Response, and the evidence of record, we conclude Petitioner has
`established a reasonable likelihood it would prevail with respect to at least
`one of the challenged claims and therefore institute an inter partes review.
`This is not a final judgment on the merits.
`A. Real Parties in Interest
`Petitioner identifies as real parties in interest:
`American Megatrends, Inc. (an American corporation, principal place
`of business in 5555 Oakbrook Parkway, Norcross, Georgia 30093).
`Micro-star International Co., Ltd (a Taiwanese corporation with its
`principal place of business at No. 69, Lide Street, Zhonghe District, New
`Taipei City 235, Taiwan).
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`MSI Computer Corp (an American corporation with its principal place
`of business at 901 Canada Court, City of Industry, California 91748).
`GIGA-BYTE Technology Co., Ltd. (a Taiwanese corporation,
`principal place of business at No.6, Bao Chiang Road, Hsin-Tien Dist., New
`Taipei City 231, Taiwan).
`G.B.T, Inc. (an American corporation, principal place of business in
`17358 Railroad St, City Of Industry, CA 91748). Pet. 3.
`B. Related Matters
`Petitioner and Patent Owner identify the following related District
`Court litigation.
`Kinglite Holdings Inc. v. Giga-Byte Tech. Co. Ltd., et al., CV 14-
`04989 JVS (PJWx) (C.D. Ca); and
`Kinglite Holdings Inc. v. Micro-Star Int’l Co. Ltd., et al., CV 14-
`03009 JVS (PJWx) (C.D. Ca).
`Papers 8 and 11.
`Petitioners and Patent Owner also identify the following related
`PTAB matters: IPR2015-001079; IPR2015-01081; IPR2015-01094;
`IPR2015-01132; IPR2015-01133; IPR2015-01140; IPR2015-01141;
`IPR2015-01188; IPR2015-01189; IPR2015-01191; IPR2015-01197;
`IPR2015-01487; IPR2015-01488; IPR2015-01515; and IPR2016-00122. Id.
`
`C. The ’200 Patent (Ex. 1001)
`1. Described Invention
`A single controller handles keyboard functions and advanced
`configuration power interface (“ACPI”) configuration and power
`management functions, in a manner that provides priority to keyboard
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`functions so to avoid end user-perceptible compromise of keyboard
`functionality. When the controller receives an interrupt, it determines
`whether that interrupt is an embedded controller interrupt or a keyboard
`interrupt. If it is a keyboard interrupt, the keyboard function is handled in a
`standard fashion. However, if it is an embedded controller interrupt for an
`ACPI configuration or power management function, a burst timer is started
`and the command is handled by a command dispatcher. If the embedded
`controller is in burst mode, multiple commands may be received during a
`burst period. Execution of commands not completed before expiration of
`the burst timer is stopped, only to be resumed upon reception of the next
`embedded controller interrupt. Ex. 1001, Abstract.
`Figure 2 of the ’200 patent is reproduced below.
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`Figure 2 shows a schematic diagram of a standard keyboard controller (e.g.,
`Intel 8042 keyboard) with two identical host interfaces 70 and 72. Bus 210
`communicates with mouse 13, bus 215 communicates with keyboard 14.
`Interface 70 (keyboard function interface) has data port 60 and command
`port 64 accessed by system I/O bus 71. Second interface 72 has data port 62
`and command port 66 accessed by system 1/O bus 73, which may be the
`same bus as system I/O bus 71. The keyboard controller includes internal
`burst period timer 250, data return vector register 255, and control method
`register 260. Id. at 4:17–44.
`
`2. Illustrative Claim
`
`Claim 9 of the ’200 patent is illustrative of the claims at issue:
`9. A method for use of a controller for handling a first set
`of high-priority tasks and a second set of lower-priority
`tasks, comprising the steps of:
`(a) receiving a task interrupt;
`(b) determining whether the task interrupt is for the first
`set of high-priority tasks or the second set of lower-
`priority tasks;
`(c) executing a current function associated with the task
`interrupt if the task interrupt is for one of the first set of
`high-priority tasks;
`(d) starting a burst period timer if the task interrupt is for
`one of the second set of lower-priority tasks;
`(e) executing the current function associated with the task
`interrupt if the task interrupt is for the one of the
`second set of lower-priority tasks; and
`(f) returning to step (e) if an additional communication for
`execution of an additional function is received prior to
`expiration of the burst period timer and if the controller
`is in burst mode, where the current function is defined
`as the additional function.
`
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`D. Petitioner’s Challenges
`Petitioner asserts the following grounds of unpatentability (Pet.
`12−14) and relies upon declaration testimony (Ex. 1015) of Mr. Sankar
`Mandal :
`
`Reference(s)
`ST20 RTOS1 and Intel
`8051 Controller2
`ST20 RTOS and Intel
`8051 Controller and IBM
`PS/23
`
`Basis
`35 U.S.C. § 103
`
`Claims challenged
`19 and 21–23
`
`35 U.S.C. § 103
`
`9 and 20
`
`Kuki4
`
`19 and 21
`
`35 U.S.C. §§
`102(a) and
`102(b)
`Our factual findings and conclusions at this stage of the proceeding
`are based on the evidentiary record developed thus far (prior to Patent
`Owner’s Response). This is not a final decision as to the patentability of any
`of the claims for which inter partes review is instituted. Our final decision
`will be based on the record as fully developed during trial.
`
`II. ANALYSIS
`We turn now to Petitioner’s asserted grounds of unpatentability and
`Patent Owner’s arguments in its Preliminary Response to determine whether
`
`
`1 SGS-Thomson Microelectronics Application Note, “Real-Time Kernels on
`the ST20” by Julian Wilson, copyright 1996 (Ex. 1003, “ST20”).
`2 Intel “8XC51SL/LOW VOLTAGE 8XC51SL KEYBOARD
`CONTROLLER” copyright Intel Corporation 1995 (Ex. 1011, “Intel 8051”).
`3 IBM Personal System/2 Hardware Interface Technical Reference (Ex.
`1010. “PS/2”).
`4 US Patent 5,168,566 – Kuki (Ex. 1004, “Kuki”).
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`Petitioner has met the threshold standard.
`A. Claim Construction
`Claim constructions presented in this Decision are preliminary. They
`are based on the record developed thus far, prior to Patent Owner’s formal
`response and evidence submissions. Constructions may change as the record
`more fully develops.
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. 37 C.F.R. § 42.100(b); see also In re Cuozzo
`Speed Techs., LLC, 793 F.3d 1268, 1278–79 (Fed. Cir. 2015) (stating that
`“Congress implicitly approved the broadest reasonable interpretation
`standard in enacting the AIA,” and “the standard was properly adopted by
`PTO regulation”), cert. granted sub nom. Cuozzo Speed Techs. LLC v. Lee,
`136 S. Ct. 890 (mem.) (2016). Under the broadest reasonable construction
`standard, claim terms are given their ordinary and customary meaning, as
`would be understood by one of ordinary skill in the art in the context of the
`entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed.
`Cir. 2007). Any special definition for a claim term must be set forth with
`reasonable clarity, deliberateness, and precision. In re Paulsen, 30 F.3d
`1475, 1480 (Fed. Cir. 1994).
`1. Summary of Claim Construction Positions
`The following table summarizes the party’s proposed claim
`constructions:
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`Term
`
`“a device”
`
`“receive a notification
`of a function”
`
`“start a timer[,] . . .
`begin execution of the
`function . . . after
`starting the timer[, and]
`abort the function if not
`completed before
`expiration of the timer”
`
`“store an address of a
`point of abortion of the
`function”
`
`“data return vector”
`
`“the first set of lower-
`priority functions”
`
`
`
`Petitioner’s Proposed
`Construction
`
`“a hardware
`component.” Pet. 9–10.
`
`“obtain information
`about a task or
`operation.” Pet. 10
`
`“a sequence of
`operations that should
`be construed to mean
`‘time-sharing.’” Pet.
`10–11.
`
`“save address
`information of the
`suspended task or
`operation so that it
`can later be resumed.”
`Pet. 11
`“area of memory that
`stores, at least, an
`address of a point of
`abortion.” Pet. 11
`“the second set of
`lower-priority
`functions.” Pet. 11–12
`
`Patent Owner’s
`Proposed Construction
`Patent Owner agrees
`with Petitioner’s
`proposed construction.
`Prelim. Resp. 7.
`Patent Owner agrees
`with Petitioner’s
`proposed construction.
`Prelim. Resp. 7.
`
`Construction should not
`include a reference to
`time-sharing. Prelim.
`Resp. 10.
`
`“save address
`information of the
`aborted task or
`operation so that it
`can later be resumed.”
`Prelim. Resp. 11.
`Patent Owner agrees
`with Petitioner’s
`proposed construction.
`Prelim. Resp. 11.
`Patent Owner agrees
`with Petitioner’s
`proposed construction.
`Prelim. Resp. 12.
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`2. “start a timer[,] . . . begin execution of the function . . . after
`starting the timer[, and] abort the function if not completed before
`expiration of the timer”:
`
`Petitioner proposes to construe “start a timer[,] . . . begin execution of
`the function . . . after starting the timer[, and] abort the function if not
`completed before expiration of the timer” as comprising “a sequence of
`operations” that requires “time-sharing.” Petitioner submits the testimony of
`Mr. Mandal, who explains that a particular function being allowed to
`execute between the start and expiration of a timer “is the same as time-
`sharing.” Pet. 10–11 (citing Ex. 1015 ¶¶ 42 and 46).
`Patent Owner argues (Prelim. Resp. 7–10) that our construction of this
`claim term should reflect its plain and ordinary meaning without reference to
`“time-sharing.” It notes that the ’200 patent does not mention “time-
`sharing.” We have reviewed the text of the ’200 patent Specification and
`agree with Patent Owner. There is no mention of “time-sharing.”
`We decline to adopt Petitioner’s proposed construction that
`incorporates the word “time-sharing.” We are not persuaded by the record,
`thus far developed, that “time-sharing” is the same as what is set forth in the
`claim limitation. For purposes of this decision, we preliminarily construe
`“start a timer[,] . . . begin execution of the function . . . after starting the
`timer[, and] abort the function if not completed before expiration of the
`timer” to mean: start a timer, begin execution of a function after the time has
`been started, and stop executing the function if it has not been completed
`prior to expiration of the timer.
`This claim term, without more, says nothing about whether a function
`that has been stopped from executing is to be resumed and under what
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`circumstances it is to be resumed. Our construction does not require
`utilizing a separate or specialized timer distinct from typical timing and
`synchronization utilized in digital computing.
`3. “store an address of a point of abortion of the function”
`We construe “store an address of a point of abortion of the function”
`to mean that there is stored an address at which a function being executed
`ceases to be executed. This claim term, without more, says nothing about
`how and under what circumstances the stored address is used.
`4. Agreed Upon Constructions
`For purposes of this decision, we adopt the agreed upon constructions
`set forth in the table above.
`
`B. Challenges Relying on ST20 (Ex. 1003)
`and Intel 8051 (Ex. 1011)
`Petitioner contends that claims 19 and 21–23 are obvious under
`35 U.S.C. § 103(a) based on ST20 (Ex. 1003) and Intel 8051 (Ex. 1011),
`relying on the supporting testimony of Sankar Mandal. Petitioner provides a
`detailed analysis of these claims and the prior art references. (Pet. 15–28)
`1. ST20 (Ex. 1003)
`ST20 is an application note from SGS-Thomson Microelectronics,
`titled “Real-Time Kernels on the ST20,” that discusses facilities provided by
`the ST20 architecture for implementing a real-time kernel. Ex. 1003, 1.
`ST20 states that “[a] real-time kernel is a mechanism for controlling the
`execution of the tasks existing in a system.” Id. It explains that a real-time
`system has timing constraints governing its behavior in that some actions
`must be carried out by particular deadlines, e.g., controlling a fuel valve to a
`motor must be carried out in real time, but updating of a database record is
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`not urgent and can be scheduled to occur later. ST20 describes a
`“deterministic system” as one in which the time taken from the occurrence
`of an event and the software associated with that event running on the
`processor has a known maximum duration. Id. The application note
`describes requirements for implementing a multi-priority preemptive
`scheduler on the ST20. Id.
`2. Intel 8051 (Ex. 1011)
`Intel 8051 provides “advance information” on the “8XC51SL/Low
`Voltage 8XC51SL Keyboard Controller.” Ex. 1011, 1 (emphasis omitted).
`3. Claims 19 and 21–23
`Petitioner argues that it would have been obvious to one of ordinary
`skill to combine the teachings of the ST20 real time OS kernel with those of
`the Intel 8051 keyboard controller to meet the limitations of claims 19 and
`21–23. Pet. 17. Petitioner argues that the implementation of a real-time
`operating system (RTOS) was within the knowledge of a person of ordinary
`skill(Id. at 15) and that Intel 8051 was designed to be adapted through its
`expanded memory (Id. at 18).
`Petitioner points to Keil Software’s (Ex. 1012) RTOS as an example
`demonstrating including a RTOS into an Intel 8051 microcontroller. Id. at
`18–19 (citing Ex. 1015 ¶ 76. Thus, those of ordinary skill knew to use a
`RTOS in a keyboard controller. Petitioner points to AMI Megakey (Ex.
`1006) as suggesting a need to handle keyboard functions and other controller
`functions within a single device. Id. at 18–19.
`Patent Owner argues that Mr. Mandal does not explain why one of
`ordinary skill would have added a complex OS to Intel 8051 to handle
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`prioritization. Prelim. Resp. 14–15 (citing Ex. 1015 ¶ 76). We are not
`persuaded by Patent Owner’s argument because Petitioner has provided an
`example of a RTOS incorporated into an Intel 8051.
`Patent Owner argues that ST20 describes proprietary software was
`developed particularly for IBM and Sun System hardware, and that neither
`the Petitioners nor Mr. Mandel explain how such software would be
`imported into Intel hardware, let alone why one would do so. Id. at 15
`(citing Ex. 1015 ¶ 76 and Ex. 1009, 5). Although Petitioner does not
`provide a detailed explanation of the combination, Petitioner has provided an
`exemplary incorporation of an RTOS into and Intel 8051. We are not
`persuaded by the present record that adaptations, if any, required to
`incorporate ST20 into an Intel device (as opposed to an IBM device) are
`beyond the reach of one of ordinary skill. We encourage further
`development of the record on this issue.
`Further, Patent Owner argues, Petitioner has neither persuasively
`established that Keil was known to those ordinarily skill, nor how it would
`have suggested to those of ordinary skill to combine a RTOS with an Intel
`8051. According to Patent Owner, Petitioner has not established that AMI
`(Ex. 1006) was known to those of ordinary skill as of the critical date of the
`’200 patent, given that AMI is marked “proprietary information.” Prelim.
`Resp. 16 (citing Ex. 1006, 2). However, Petitioner does not base its
`challenge on AMI. Pet. 6, ftnt. 1. Instead, Petitioner cites AMI only as
`evidence that for many years before the filing of the application for the ’200
`patent the industry recognized the need to handle keyboard functions and
`other controller functions within a single device. Id. at 18.
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`Patent Owner further argues that ST20 and Intel 8051 together do not
`teach “start a timer . . . .” This argument depends upon our construing this
`claim term as suggested by Patent Owner. Based on our construction of this
`claim limitation, we are not persuaded by Patent Owner’s argument.
`For purposes of institution, Petitioner has established a reasonable
`likelihood of prevailing on the asserted ground. We encourage the parties to
`develop further the record regarding the motivation to combine the
`references and how ST20 teaches/does not teach the recited limitations of
`the challenged claims.
`
`C. Challenges Relying on ST20 (Ex. 1003) and Intel
`8051 (Ex. 1011) and PS/2 (Ex. 1010)
`
`Petitioner challenges claims 9 and 20 based on ST20 (Ex. 1003), Intel
`8051 (Exhibit 1011) and PS/2 (Ex. 1010) and provides a detailed analysis of
`claims 9 and 20 and these references at Petition pages 29–34.
`1. PS/2 (Ex. 1010)
`PS/2 is a technical reference describing the IBM Personal System/2
`hardware interface. Ex. 1010, p. 1. It focuses on the “micro channel
`architecture” of the PS/2 system. Id. at 8. PS/2 provides a detailed
`description of the types of commands used in a typical keyboard controller.
`Ex. 1010, pp.340–343; Ex. 1015 ¶ 110. At pages 30–31, the Petition focuses
`on the “A5” command:
`Load Password: This command initiates the
`Password Load procedure. Following this
`command the controller takes input from the data
`port until a null (0) is detected. The null terminates
`password entry.
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`Ex. 1010, p. 341.
`
`2. Claims 9 and 20
`Petitioner argues that the PS/2 “A5” command is used when the host
`intends to write data to the controller as a series of write functions. Pet. 30
`(citing Ex. 1015 ¶ 111). According to Petitioner, this is how the ’200 patent
`envisioned a command implemented in “burst mode.” Id. (citing Ex. 1001,
`5:23–28). The ’200 patent explains:
`In burst mode, the embedded controller 200
`discontinues normal processing and waits for a
`series of commands to be sent from the host 20.
`This allows the host 20 to quickly read or write
`several bytes of data at a time without the
`overhead of SCI’s between the commands.
`
`Id. (emphasis omitted).
`Petitioner’s Declarant, Mr. Mandal, opines that this embodiment of
`the ’200 patent generally describes the A5 command. Ex. 1015 ¶ 112.
`Petitioner argues that the A5 command is equivalent to “burst mode” and
`“burst enable function.” Pet. 29–31, 34.
`According to Petitioner, one of ordinary skill would be motivated to
`use the A5 command with a system that combines ST20 and the Intel 8051
`controller because the A5 command was “widely adopted.” Pet. 31.
`Patent Owner argues that claims 9 and 20 require that burst mode be
`in effect before the timer is expired. Prelim. Resp. 19. Patent Owner notes
`that the PS/2 A5 command initiates Password Load procedure. Then, the
`controller takes input from data port until a null (0) is detected, which null
`terminates password entry. Prelim. Resp. 20 (citing Ex. 1010 at 341).
`Patent Owner explains that:
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`This reference does not disclose that the A5 command is to be
`terminated according to a timer. For instance, assuming the A5
`command is associated with the claimed timer, the A5
`command is not terminated until a null (0) is detected from the
`data port, even if the timer has expired. Therefore, the PS/2
`reference fails to disclose the A5 command of the PS/2 is
`executed “in burst mode,” or is a “burst enabled function” of
`claims 9 and 20 of the ’200 patent respectively.”
`Prelim. Resp. 20. However, Petitioner states that “Mr. Mandal considers
`this embodiment of the ’200 Patent generally describes the A5 command”
`and that “Mr. Mandal explains that the A5 command is necessarily executed
`in the burst mode.” Pet. 30 (citing Ex. 1015 ¶¶ 111, 112). Based on Mr.
`Mandal’s testimony (subject to cross-examination during trial and the
`possible introduction of testimony to the contrary) we accept for purposes of
`this decision that PS/2 discloses a burst timer sufficient to meet the
`limitations of claims 9 and 20.
`D. Challenges Relying on Kuki (Ex. 1004)
`Petitioner challenges claims 19 and 21 as anticipated by Kuki (Ex.
`1004). Pet. 34–41. Claim 19 reads:
`19. In a computer system with an operating system and
`firmware, the computer system comprising a device for
`handling a first set of higher-priority functions and a
`second set of lower-priority functions using the
`firmware, the device configured to:
`receive a notification of a function to be performed;
`determine whether the function to be performed is one of
`the first set of higher-priority functions or one of the
`second set of lower-priority functions;
`execute the function associated with the notification if the
`notification is for one of the first set of higher-priority
`functions;
`start a timer if the notification is for one of the first set of
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`lower-priority functions and the timer has not already
`been started;
`begin execution of the function associated with the
`notification after starting the timer if the notification is
`for one of the first set of lower-priority functions;
`abort the function if not completed before expiration of the
`timer, and store an address of a point of abortion of the
`function in a data return vector; and
`resume execution of the function if previously aborted due
`to the expiration of the timer upon reception of a
`subsequent notification, by continuation at the address
`stored by the data return vector.
`
`
`
`1. Kuki (Ex. 1004)
`Kuki describes a computer peripheral device incorporating a multi-
`task control device for a microcomputer system. It controls a plurality of
`tasks executed by the CPU comparing prior orders between a plurality of
`tasks, and generating interrupts for switching among tasks. Ex. 1004,
`Abstract. Petitioner describes Kuki as an example of “offloading the
`scheduling functionality of an operating system onto a peripheral device.”
`Pet. 34 (citing Ex. 1004, Abstract; Ex. 1015 ¶ 125. Petitioner relies, among
`other portions, on Kuki’s Figure 2, which is reproduced below.
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`Figure 2 shows a simplified block diagram of an embodiment of the
`internal configuration of a multi-task control element. Ex. 1004, 2:13–15.
`The control element has a number of registers that can be accessed from
`CPU 2 (shown in Figure 1). Command parameter register CP10 stores such
`parameters that are received from CPU 2 when executing the command or
`output after executing the command. The command status register CNST
`writes the command during write mode and stores the already executed
`command data during read mode. The new stack pointer register SPN
`outputs the stack pointer value of such a task to be executed so that this
`value can be made available for the task switching data. Ex. 1004, 3:8–20.
`Petitioner also relies on Kuki’s Figure 6, reproduced below.
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`Figure 6 is a flowchart describing the operation of the main routine executed
`by the multi-task control device. Ex. 1004, 2:23–25. Petitioner cites Figure
`6 as demonstrating that the loop back after step 92 establishes that an
`aborted task eventually resumes. Pet. 39 (citing Ex. 1015 ¶ 136).
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`2. Claim 19
`We have reviewed Petitioner’s analysis of claim 19 and Kuki at Pet.
`pages 35–40. Petitioner contends that Kuki discloses offloading the
`scheduling functionality of an operating system onto a peripheral device.
`Pet. 34 (citing Ex. 1004, p.1, Abstract; Ex. 1015 ¶ 125). Petitioner offers the
`declaration testimony of Mr. Mandal that an operating system traditionally
`handles tasks by applying prioritization and time-sharing. Id. at 35. This
`approach, according to Petitioner, is the same as that taken by the ’200
`patent. Id.
`Patent Owner argues that Kuki’s storing of priority levels does not
`equate to determining whether a function to be performed is of higher or
`lower priority. Patent Owner notes that the priority of a function can be
`changed at any time using a “TPRI” command. Prelim. Resp. 22.
`We are not persuaded by Patent Owner’s argument. Rather, for
`purposes of this decision, we accept the inference that storing priority levels
`(even though they can be changed) suggests that decisions are made based
`on a comparison of priority levels, some being higher than others.
`Patent Owner further argues that the timer limit as described by the
`’200 patent claims is to be set so any interruption of the mouse and keyboard
`functions are not noticeable. There is no mention in Kuki of lower priority
`tasks being performed between the start and the expiration of the timer, as
`required by claim 19. We are not persuaded by this argument because, as
`Petitioner explains, Kuki generates an interrupt signal for a time-sharing
`process. Pet. 38. This suggests timing the duration of execution of lower
`priority tasks.
`
`19
`
`
`
`

`
`IPR2016-00114
`Patent 5,937,200
`
`
`For reasons stated, Petitioner has demonstrated a reasonable
`likelihood of success in establishing that claim 19 is anticipated by Kuki.
`3. Claim 21
`Claim 21 depends from claim 19 and requires the device to interface
`with the BIOS firmware or with the operating system.
`Petitioner argues that Kuki discloses this element and that Kuki also
`explains using timer interrupts to implement time-sharing. Pet. 40 (citing
`Ex. 1004, Figure 24). Kuki explains that “interrupt signals are employed for
`the switching of those tasks executed by the CPU, thus the device
`incorporating these functions can be usefully applied to a wide variety of
`microcomputers.” (Id., p.16, 1:46–50). Mr. Mandal explains that the multi-
`task control element’s use of interrupts implies that it interfaces with BIOS
`firmware. (Ex. 1015, p.50, ¶ 141). According to Petitioner, one of ordinary
`skill would know that BIOS firmware is responsible for handling interrupts.
`(Pet. 40).
`Petitioner further argues that because Kuki’s multi-task control
`element is designed to be a peripheral. (Ex. 1004, p.17, 3:2–7). Kuki then
`explains that “when the power is supplied to the system, the multi-task
`control element 1 first enters the reset operation to initialize all the internal
`functional elements (step 1).” (Ex. 1004, p.17, 4:54–57). Mr. Mandal
`explains that initialization is performed by firmware such as BIOS. (Ex.
`1015, pp.50–51, ¶¶142–143). Pet. 40.
`Patent Owner argues that Kuki is silent with the respect to the
`disclosure of BIOS firmware, which is an element of claim 21. Prelim.
`Resp. 24 (citing Ex. 1001 at 13:2).
`
`20
`
`
`
`

`
`IPR2016-00114
`Patent 5,937,200
`
`
`We agree with Patent Owner. For at least this reason, Petitioner has
`not demonstrated a reasonable likelihood that it would prevail in showing
`that claim 21 is anticipated by Kuki.
`
`III. CONCLUSIONS
`Having considered the arguments presented in the Petition and in
`Patent Owner’s Preliminary Response, along with all of the evidence relied
`upon by both parties, we conclude that the information presented in the
`Petition establishes a reasonable likelihood Petitioner will prevail in
`challenging claims 9 and 19–23 based on the following:
`1) claims 19 and 21–23 as obvious based on ST20 and Intel 8051;
`2) claims 9 and 20 as obvious based on ST20 and Intel 8051 and
`PS/2; and
`3) claim 19 as anticipated by Kuki;
`Petitioner has not established a reasonable likelihood of prevailing as
`to claim 21 anticipated by Kuki.
`
`IV. ORDER
`
`In consideration of the foregoing, it is hereby:
`ORDERED that the Petition is granted as to claims 9 and 19–23 of the
`’200 patent;
`FURTHER ORDERED that, pursuant to 35 U.S.C. § 314(d) and
`37 C.F.R. § 42.4, notice is hereby given of the institution of a trial, the trial
`commencing on the entry date of this decision; and
`FURTHER ORDERED that trial will be conducted only as to the
`following listed challenges and no other ground of unpatentability alleged in
`the Petition for any claim is authorized for this inter partes review:
`21
`
`
`
`

`
`IPR2016-00114
`Patent 5,937,200
`
`
`1) claims 19 and 21–23 as obvious based on ST20 and Intel 8051;
`2) claims 9 and 20 as obvious based on ST20 and Intel 8051 and
`PS/2; and
`3) claim 19 as anticipated by Kuki;
`FURTHER ORDERED that the trial will be conducted in accordance
`with the accompanying Scheduling Order. In the event that an initial
`conference call has been requested or scheduled, the parties are directed to
`the Office Trial Practice Guide, 77 Fed. Reg. 48756, 48765–66 (Aug. 14,
`2012) for guidance in preparing for the initial conference call, and should
`come prepared to discuss any proposed changes to the scheduling order
`entered herewith and any motions the parties anticipate filing during the
`trial.
`
`
`PETITIONER:
`
`Vivek Ganti
`Gregory Ourada
`HILL, KERTSCHER & WHARTON, LLP
`vg@hkw-law.com
`go@hkw-law.com
`
`PATENT OWNER
`
`Christopher Frerking
`chris@ntknet.com
`
`George C. Summerfield
`STADHEIM & GREAR, LTD
`summerfield@stadheimgrear.com
`
`22

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