The ATLANTA™Chipset:
`A Low-Cost Scalable VLSI Solution for High-
`Performance ATM Switching Systems
`
`Fabio M. Chiussi, Joseph G. Kneuer and Vijay P. Kumar
`
`High-Speed Networks Research Department
`Bell Laboratories, Lucent Technologies
`Holmdel, NJ 07733, USA
`
`Provides path for future growth in features
`
`Nonblocking
`Modularly scalable from 622 Mbps to 25 Mbps
`using commonly available implementation
`technology
`High buffer utilization while using distributed
`buffers
`
`The ATLANTA™Architecture
`
`Low complexity
`
`EMC Exhibit 1036
`EMCv.Intellectual Ventures
`
`IPR2016-01106
`
`
`A Low-Cost Scalable VLSI Solution for High-
`Performance ATM Switching Systems
`
`Fabio M. Chiussi, Joseph G. Kneuer and Vijay P. Kumar
`
`High-Speed Networks Research Department
`Bell Laboratories, Lucent Technologies
`Holmdel, NJ 07733, USA
`
`Provides path for future growth in features
`
`Nonblocking
`Modularly scalable from 622 Mbps to 25 Mbps
`using commonly available implementation
`technology
`High buffer utilization while using distributed
`buffers
`
`The ATLANTA™Architecture
`
`Low complexity
`
`EMC Exhibit 1036
`EMCv.Intellectual Ventures
`
`IPR2016-01106
`
`
`
`The ATLANTA Architecture: Basics
`Chiussi, Kneuer, Kumar
`
`Ingress and egress buffers
`n
`n Selective backpressure
`u No Head-of-Line (HOL)blocking
`u Sharing of distributed buffers
`Buffer utilization comparable with centralized shared-memory switch
`u Majority of buffers in ingress and egress port cards
`low-cost off-the-shelf RAM’s, regardless of switching capacity
`
`n Fabric
`
`Ltn rrewetions
`
`n Complete set of building blocks for implementing ATLANTA™
`switches from 622 Mbpsto 25 Gbps
`4 chips (2 for fabric, 2 for port cards)
`622-Mbpsinput/output port rates (plus local header overhead)
`Up to 64K cell buffers per port
`Up to 64K VC’s per port
`4 Quality-of-Service (QoS) service classes per port
`Optimal support of multicast traffic
`Physical interface supports UTOPIA II multiplexing standard.
`Maximum 30 subports per port
`Support of redundant fabric configurations
`Port devices: full-duplex ingress and egress functionality
`
`Lucent Technologieset
`
`u Up to 5 Gbps: standalone switching module
`u From 5 Gbps to 25 Gbps: Memory/Space/Memory
`Configuration
`
`LucentTechnologies O
`
`The ATLANTA™Chipset: Essential Features
`
`
`
`The ATLANTA™Chipset: Fabric Devices
`
`Chiussi, Kneuer, Kumar
`
`n ATM Switch Module (ASX)
`u 5 Gps switching module
`u Operates either as 8x8 standalone switch,oras first stage, or
`as third stage in MSM configuration
`Small integrated buffer (512 cells)
`
`n ATM Crossbar Element (ACE)
`u 8x8 bufferless crossbar for second stage in MSM
`configuration
`u Implements one, two, or four crossbars, depending on fabric
`size
`
`switching module
`
`n ATM BufferManager
`Managesingress and egress port buffers (up to 64K cells in shared buffer
`pool in external RAM)
`Multicasting to subports within a port
`Rate matching to subports
`rate matching to subports with variable rate (e.g., SAR’s) also supported
`Dual switch interfaces and monitoring logic for fault-tolerant redundant
`fabric configurations
`Complete set of hooks for Available Bit Rate (ABR) and Operation,
`Administration & Maintenance (OA&M)support via external engine.
`Can operate without the fabric as a low-cost 622-Mbps
`
`The ATLANTA™Chipset: Port Devices
`
`Chiussi, Kneuer, Kumar
`
`n ATM Layer Manager(ALM)
`u
`Input and output header processing, ATM-Forum-compliantpolicing,
`statistics collection, local header generation
`
`
`
`The ATLANTA™Chipset: Pictures
`
`Fabric Devices
`
`Ly
`
`il
`
`HiT
`
`The ATLANTA™Chipset: Pictures (cont.)
`
`Port Devices
`
`> VOLT TTT MEEVEE ET ETE TETEe
`; oa
`FE
`a
`
`POUAtedtiti
`
`
`
`ATLANTA™Architecture: Single-Stage Switch Fabric
`Chiussi, Kneuer, Kumar
`
`Egress Port Card 1
`
`8x8
`Standalone
`Single ASX Chip
`Switch Fabric
`
`Ingress Port Card 1
`Ingress
`
`Ingress
`Buffer
`
`Multiple
`Physical
`Subports
`
`Ingress Port Card 8
`Ingress
`Ingress
`ALM
`ABM
`
`i
`Subports
`
`Ingress
`Buffer
`
`(In reality, ingress and egress port devices are full duplex)
`
`Switch Fabric
`
`One queueing group per output
`port
`Each queueing group: 4 service
`priorities, separate FIFO’s for
`each priority
`u Round robin amonggroups
`u Weighted round robin (work-
`conserving) amongpriorities
`within group
`
`ATLANTA”Architecture: Cell Flows
`Chiussi, Kneuer, Kumar
`
`(4 Service Queues)
`Sapa tont
`loutput Port 2
`(4 Service Queues)
`
`fOutput Port §
`(4 Service Queues)
`
`‘Waighted
`—
`
`(4ServiceQueues)
`cuparront
`[Output Port 2
`(4ServiceQueues)
`
`(4ServiceQueues)
`Soper rony
`
`8x8
`Standalone
`Single ASX Chip
`
`ABM:exactreplica of
`queueing structure in ASX
`Selective backpressure
`between ASX and ABM
`
`
`
`ATLANTA”Architecture: Buffers
`
`Chiussi, Kneuer, Kumar
`
`ASX: Common 512-cell on-chip buffer pool
`ABMcell buffer (up to 64K cells) in external
`low-speed static RAM
`
`ATLANTA’ Stand-Alone Fabric: Performance
`
`Chiussi, Kneuer, Kumar
`
`Buffer management:
`u each queue controlled by dynamic thresholds
`T(t) = max(% G - QV), 0)
`u ABM: dynamicthreshold triggers discarding
`u ASX: dynamic threshold triggers selective backpressure
`ABMonegress: backpressureto the fabric
`(optional)
`
`Las rreweters
`
`L100
`8x8
`Load 90%
`Dynamic Thresholds
`
`\.
`
`XS,
`
`—— Ingress Alpha 2
`ar--
`Ingress Alpha 8
`—
`Ingress Alpha 16
`Ingress Alpha 32
`=
`Ingress Alpha 64
`
`-
`
`0
`
`4000
`3000
`2000
`1000
`Buffer Size per Ingress Port Card
`
`5000
`
`CellLossRate
`
`E-04
`
`1E-05
`1E-06
`
`1E-07
`
`Example: bursty traffic, geometrically distributed bursts, average burst length
`L=100cell, 90% load, single service class
`Selective backpressure
`u Backpressure appliedselectively onlyto the traffic flows destined to congested port(s)
`u No HOLblocking
`u Buffers in ingress cards act as an extension of output buffers in the fabric
`u Buffer requirements less than a factor of two larger than centralized shared-memory switch
`vucenttet
`Buffer requirements depend on a
`
`
`
`ATLANTA™Architecture: Multi-Stage Switch Fabric
`Chiussi, Kneuer, Kumar
`
`Memory/Space/
`Memory
`Configuration
`Nonblocking multi-
`stage routing network
`Expansion; multiple
`paths from each input
`to each output module
`All interconnection
`
`lines between stages
`have samerate as
`
`input and output ports
`
`LucentTechnologies O
`
`cell sequence
`
`n Achieves non-blocking behavior with low complexity
`u Buffers in the input and output stages
`u Bufferless second stage
`u Simple, efficient, fully distributed self-routing algorithm
`Concurrent Dispatching Algorithm
`independently run by each input module in the fabric
`Very simple to implement.
`
`Memory/Space/Memory Configuration
`
`Chiussi, Kneuer, Kumar
`
`n Small buffers in the fabric
`
`u Selective backpressure from the output to the input buffers in the fabric
`
`n Cell sequenceis preserved
`u Bufferless center stage, cells can be routed individually without affecting
`
`
`
`ATLANTA™Multi-Stage Fabric: Performance
`
`Chiussi, Kneuer, Kumar
`
`Buffer requirements decrease as
`
`increases
`
`CellLossRate
`
`CellLossRate
`
`3000
`2500
`2000
`1500
`Buffer Size per Ingress Port Card
`
`3500
`
`1000
`
`3000
`2500
`2000
`1500
`Buffer Size per Ingress Port Card
`
`
`
`Lucent Technologiestet Las rreweters
`
`Expansionfactor as small as 6:8 sufficient to achieve nonblocking behavior
`ASX device supports 4:8, 5:8, and 6:8 expansion factors
`u_
`buffer requirements in the ingress depend on expansionfactor.
`Example: bursty traffic, geometrically distributed bursts, average burst length
`L=100cell, 90% load, single service class, dynamic thresholding parameter
`a=2
`
`and selective backpressure scheme
`
`= Ingress Alpha 2
`---H--
`Ingress Alpha 8
`= -8=
`Ingress Alphalé
`== Ingress Alpha 32
`— Ingress Alpha 64
`— 8 — Ingress Alpha 256
`
`+3500
`
`4000
`
`
`
`ATLANTA™Architecture: Multicasting
`
`Chiussi, Kneuer, Kumar
`
`n Minimum multicast tree
`
`u Cells alwaysreplicated as far downstream as possible in the switch
`Noreplication in ingress ABM
`In first stage of multi-stage fabric only one replication to each desired output module
`
`u Minimizes expansionin traffic volumeinternally to the switch due to
`multicasting
`u Excellent performance
`
`Replication does not require external control
`u
`embeddedin self-routing structure
`
`Single copy of a multicast cell locally stored in each buffer
`u_
`replicated (if necessary) only whenthecell is sent to following stage in the switch
`
`Efficient and robust interaction between multicasting scheme
`
`
`
`ATLANTA™Multicasting: Example
`
`Connection V
`
`Chiussi, Kneuer, Kumar
`
`
`
`
`
`
`
`
`(e.g., Per-VC queueing)
`
`Four chips, complete VLSI solution for implementing ATLANTA" switches
`ranging in capacity from 622 Mbpsto 25 Gbps
`Innovative architecture
`Nonblocking
`Scalable, modular
`Highly-distributed
`Low complexity
`Excellent multicasting
`Extensive set of features and hooks
`
`ATLANTA™Chipset: Conclusions
`
`Chiussi, Kneuer, Kumar
`
`»
`
`Majority of buffers in low-cost off-the-shelf RAM’s
`Dueto its distributed nature, the ATLANTA™architecture is a very desirable
`platform for future growth.
`u
`Evenlarger switching and buffering capacities
`u Higher link rates
`u More sophisticated buffer managementfor better provisioning of QoS guarantees
`
`
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