JEDEC Standard No. 21–C
`Page 4.6.1–1
`
`4.6.1 – 278 PIN BUFFERED SDRAM DIMM FAMILY
`CAPACITY––up to the addressing capacity of 16 bits, address multiplexed with words of 16 bytes (144 bits).
`DATA CONFIGURATIONS––Only one DATA Word configurations is defined in the initial release:
`––144 BIT SDRAM with the location of CHECKBITS undefined
`CONFIGURATION––2 Different Configurations are defined using X16 SDRAM memories with 1 and 2 banks
`LOGIC FEATURES––The modules contain the Serial Presence Detect (SPD) feature that conist of a built
`in serial access EEPROM that stores information on mutiple parameters and attributes of the module
`such as technology, storage capacity, configuration, data word configuration, refresh mode, and
`speed of the module.
`PACKAGE––278 PIN JEDEC DIMM MEMORY MODULE
`PIN ASSIGNMENTS ––Figs. 4.6.1–A, 4.6.1–B, & 4.6.1–C
`DRAM SPD INFORMATOION –– Fig. 4.6.1–D
`MODULE KEYING DEFINITION –– Fig. 4.6.1–E
`MODULE PIN DEFINITIONS –– Fig. 4.6.1–F
`X144 SDRAM CONFIGURATION BLOCK DIAGRAMS ––Figs. 4.6.1–G and 4.6.1–H
`
`Release 7
`
`Page 1 of 8
`
`INTELLECTUAL VENTURES EX. 2004
`EMC v. Intellectual Ventures
`IPR2016-01106
`
`
`Page 4.6.1–1
`
`4.6.1 – 278 PIN BUFFERED SDRAM DIMM FAMILY
`CAPACITY––up to the addressing capacity of 16 bits, address multiplexed with words of 16 bytes (144 bits).
`DATA CONFIGURATIONS––Only one DATA Word configurations is defined in the initial release:
`––144 BIT SDRAM with the location of CHECKBITS undefined
`CONFIGURATION––2 Different Configurations are defined using X16 SDRAM memories with 1 and 2 banks
`LOGIC FEATURES––The modules contain the Serial Presence Detect (SPD) feature that conist of a built
`in serial access EEPROM that stores information on mutiple parameters and attributes of the module
`such as technology, storage capacity, configuration, data word configuration, refresh mode, and
`speed of the module.
`PACKAGE––278 PIN JEDEC DIMM MEMORY MODULE
`PIN ASSIGNMENTS ––Figs. 4.6.1–A, 4.6.1–B, & 4.6.1–C
`DRAM SPD INFORMATOION –– Fig. 4.6.1–D
`MODULE KEYING DEFINITION –– Fig. 4.6.1–E
`MODULE PIN DEFINITIONS –– Fig. 4.6.1–F
`X144 SDRAM CONFIGURATION BLOCK DIAGRAMS ––Figs. 4.6.1–G and 4.6.1–H
`
`Release 7
`
`Page 1 of 8
`
`INTELLECTUAL VENTURES EX. 2004
`EMC v. Intellectual Ventures
`IPR2016-01106
`
`
`
`JEDEC Standard No. 21–C
`Page 4.6.1–2
`
`X144 SDRAM DIMM
`
`VSSQ
`DQ1
`DQ2
`DQ4
`VDDQ
`DQ7
`
`1
`2
`3
`4
`5
`6
`
`REAR
`SIDE
`
`FRONT
`SIDE
`
`Interface Key
`
`140
`141
`142
`143
`144
`145
`
`DQ0
`VDDQ
`DQ3
`DQ5
`DQ6
`VSSQ
`
`146
`147
`148
`149
`150
`151
`152
`153
`154
`155
`156
`157
`158
`159
`160
`161
`162
`163
`164
`165
`166
`167
`168
`169
`170
`171
`172
`173
`174
`175
`176
`177
`178
`179
`180
`181
`182
`183
`184
`185
`186
`187
`188
`189
`190
`191
`192
`193
`194
`195
`196
`197
`198
`199
`
`VDD
`DQMB1
`DQ9
`DQ11
`VDDQ
`DQ13
`DQ15
`DQ17
`VSSQ
`DQ19
`DQ21
`DQ23
`VDD
`DQMB3
`VDDQ
`DQ25
`DQ27
`DQ29
`VSSQ
`DQ31
`DQ32
`DQ34
`VDDQ
`DQ36
`DQ38
`DQMB4
`VDD
`DQ40
`VSSQ
`DQ42
`DQ44
`DQ46
`VDDQ
`DQ48
`DQ50
`DQ52
`VSSQ
`DQ54
`VDD
`DQMB7
`DQ57
`DQ58
`VDDQ
`DQ60
`DQ62
`RFU
`VSSQ
`A3
`A4
`A1
`VDD
`A0
`A10
`A11
`SS
`
`Figure 4.6.1–A
`278 PIN X144 SDRAM DIMM PINOUT (TOP THIRD)
`Release 7
`
`DQMB0
`VSS
`DQ8
`DQ10
`DQ12
`VSSQ
`DQ14
`DQ16
`DQ18
`VDDQ
`DQ20
`DQ22
`DQMB2
`VSS
`DQ24
`VSSQ
`DQ26
`DQ28
`DQ30
`VDDQ
`VREF
`DQ33
`DQ35
`VSSQ
`DQ37
`DQ39
`DQMB5
`VSS
`DQ41
`VDDQ
`DQ43
`DQ45
`DQ47
`VSSQ
`DQ49
`DQ51
`DQ53
`VDDQ
`DQ55
`DQMB6
`DQ56
`VSS
`DQ59
`VSSQ
`DQ61
`DQ63
`RFU
`VDDQ
`A2
`A5
`A6
`VSS
`A7
`A8
`
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`48
`49
`50
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`
`Top Third
`
`Top View
`
`Page 2 of 8
`
`
`
`JEDEC Standard No. 21–C
`Page 4.6.1–3
`
`DQ55
`DQNB6
`DQ56
`VSS
`DQ59
`VSSQ
`DQ61
`DQ63
`RFU
`VDDQ
`A2
`A5
`A6
`VSS
`A7
`A8
`A9
`VDD
`A13
`A15
`CKE
`VSS
`NU
`
`45
`46
`47
`48
`49
`50
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`
`S0
`68
`69
`VDD
`RE
`70
`W
`71
`72
`RFU
`73
`VSS
`74
`RFU
`75
`VDDQ
`76
`DQ65
`77
`DQ67
`78
`DQ69
`79
`VSSQ
`80
`DQ71
`81
`VSS
`82
`DQ72
`83
`VDDQ
`84
`DQ74
`85
`DQ75
`86
`DQ77
`87
`VSSQ
`88
`DQ80
`89
`DQ81
`90
`DQ83
`91
`VDDQ
`92
`DQ86
`93
`DQ87
`DQMB11 94
`VDD
`95
`DQ89
`96
`VSSQ
`97
`DQ92
`98
`DQ93
`99
`VREF
`100
`VDDQ
`101
`DQ97
`102
`DQ98
`103
`
`184
`185
`186
`187
`188
`189
`190
`191
`192
`193
`194
`195
`196
`197
`198
`199
`200
`201
`202
`203
`204
`205
`206
`
`207
`208
`209
`210
`211
`212
`213
`214
`215
`216
`217
`218
`219
`220
`221
`222
`223
`224
`225
`226
`227
`228
`229
`230
`231
`232
`233
`234
`235
`236
`237
`238
`239
`240
`241
`242
`
`VDD
`DQMB7
`DQ57
`DQ58
`VDDQ
`DQ60
`DQ62
`RFU
`VSSQ
`A3
`A4
`A1
`VDD
`A0
`A10
`A11
`VSS
`A12
`A14
`RFU
`VDD
`CK
`CK
`
`VSS
`S1
`CE
`RFU
`VDD
`RFU
`VSSQ
`DQ64
`DQ66
`DQ68
`VDDQ
`DQ70
`DQMB8
`DQMB9
`VDD
`DQ73
`VSSQ
`DQ76
`DQ78
`DQ79
`VDDQ
`DQ82
`DQ84
`DQ85
`VSSQ
`DQMB10
`VSS
`DQ88
`DQ90
`DQ91
`VDDQ
`DQ94
`DQ95
`DQ96
`VSSQ
`DQ99
`
`X144 SDRAM DIMM
`
`REAR
`SIDE
`
`FRONT
`SIDE
`
`VOLTAGE KEY
`
`Middle Third
`
`POLARITY KEY
`
`Figure 4.6.1–B
`278 PIN X144 SDRAM DIMM PINOUT (MIDDLE THIRD)
`Release 7C8
`
`104
`VSSQ
`105
`DQ101
`106
`DQ102
`DQMB12 107
`VDD
`108
`
`243
`244
`245
`246
`247
`
`DQ100
`VDDQ
`DQ103
`VSS
`DQMB13
`
`Page 3 of 8
`
`
`
`JEDEC Standard No. 21–C
`Page 4.6.1–4
`
`VDD
`DQ89
`VSSQ
`DQ92
`DQ93
`
`VDDQ
`DQ97
`DQ98
`
`VSSQ
`DQ101
`DQ102
`DQMB12
`VDD
`DQ104
`VDDQ
`DQ107
`DQ108
`DQ110
`VSSQ
`DQ113
`DQ114
`DQ116
`VDDQ
`DQ119
`VDD
`DQMB15
`DQ120
`DQ122
`VSSQ
`DQ125
`DQ126
`DQ128
`VDDQ
`DQ131
`DQ132
`DQ134
`VDD
`DQMB17
`VSSQ
`DQ137
`DQ138
`DQ140
`VDDQ
`DQ143
`
`95
`96
`97
`98
`99
`
`101
`102
`103
`
`104
`105
`106
`107
`108
`109
`110
`111
`112
`113
`114
`115
`116
`117
`118
`119
`120
`121
`122
`123
`124
`125
`126
`127
`128
`129
`130
`131
`132
`133
`134
`135
`136
`137
`138
`139
`
`X144 SDRAM DIMM
`
`POLARITY KEY
`
`Bottom Third
`
`REAR
`SIDE
`
`FRONT
`SIDE
`
`234
`235
`236
`237
`238
`
`240
`241
`242
`
`243
`244
`245
`246
`247
`248
`249
`250
`251
`252
`253
`254
`255
`256
`257
`258
`259
`260
`261
`262
`263
`264
`265
`266
`267
`268
`269
`270
`271
`272
`273
`274
`275
`276
`277
`278
`
`DQ88
`DQ90
`DQ91
`VDDQ
`DQ94
`
`DQ96
`VSSQ
`DQ99
`
`DQ100
`VDDQ
`DQ103
`VSS
`DQMB13
`DQ105
`DQ106
`VSSQ
`DQ109
`DQ111
`DQ112
`VDDQ
`DQ115
`DQ117
`DQ118
`VSSQ
`DQMB14
`VSS
`DQ121
`DQ123
`DQ124
`VDDQ
`DQ127
`DQ129
`DQ130
`VSSQ
`DQ133
`DQ135
`DQMB16
`VSS
`DQ136
`VDDQ
`DQ139
`DQ141
`DQ142
`VSSQ
`
`Figure 4.6.1–C
`278 PIN X144 SDRAM DIMM PINOUT (BOTTOM THIRD)
`Release 7
`
`Page 4 of 8
`
`
`
`JEDEC Standard No. 21–C
`Page 4.6.1–5
`
`PD6 PD5
`195
`194
`
`SPEED (tCYC)
`15 ns
`12 ns
`10 ns
`8 ns
`0
`0
`PD SPEED TABLE
`
`1 0 1
`
`1 1 0
`
`INTERFACE
`
`PD7
`196
`
`UNBUFFERED
`BUFFERED
`MODULE INTERFACE
`
`0 1
`
`WRITE MODE
`
`PD8
`197
`
`PD BITS
`4 3 2 1
` 1 1 1 1 NO MODULE
`
`MODULE
`CONFIGURATION
`
`CE
`RE
`SDRAM
`ORGANIZATION ADDR. ADDR
`
` 1 0 0 0
` 0 0 0 0
`
`1M X 64/72/80
`2M X 64/72/80
`
` 1 0 0 1
` 0 0 0 1
`
`2M X 64/72/80
`4M X 64/72/80
`
`1M X 16
`1M X 16
`
`2M X 8
`2M X 8
`
` 1 0 1 0
` 0 0 1 0
`
`4M X 64/72/80
`8M X 64/72/80
`
`4M X 4/16
`4M X 4/16
`
` 1 0 1 1
` 0 0 1 1
`
`8M X 64/72/80
`16M X 64/72/80
`
` 1 1 0 0
` 0 1 0 0
`
`16M X 64/72/80
`32M X 64/72/80
`
` 1 1 0 1 RFU
` 0 1 0 1 RFU
`
`8M X 8
`8M X 8
`
`16M X 4
`16M X 4
`
`TBD
`TBD
`
`12
`12
`
`12
`12
`
`12
`12
`
`TBD
`TBD
`
`TBD
`TBD
`
`TBD
`TBD
`
`8
`8
`
`9
`9
`
`10
`10
`
`TBD
`TBD
`
`TBD
`TBD
`
`TBD
`TBD
`
`TBD
`TBD
`TBD
` 1 1 1 0 RFU
`BYTE
`TBD
`TBD
`TBD
` 0 1 1 0 RFU
`This page is reserved for the future addition of serial presence detect tables.
`WORD
` 0 1 1 1 Expansion
`.
`WRITE MODE DETECT
`
`0 1
`
`Note 1 Presence Detect pins PD1––PD8 are buffered and enabled by
`PDE. The ”1” outputs are NC and the ”0” outputs are driven low
`by on–module drivers when PDE is asserted active low.
`
`Note 2 Buffered DIMMs (PD7=1) with PD8=0 (Byte–Write) shall be capa-
`ble of both Word–Write and Byte–Write operations
`
`POWER
`
`ID3
`107
`
`RAS TIMING
`
`ID2
`7
`
`INTERVAL
`
`ID1
`6
`
`2 CLOCKS
`1 CLOCK
`COMMAND INTERVAL
`
`0 1
`
`NO EARLY RAS
`EARLY RAS
`READ PRECHARGE TIMING
`
`0 1
`
`NORMAL
`LOW–POWER
`POWER LEVEL DETECT
`
`0 1
`
`Figure 4.6.1–D
`278 PIN X144 SDRAM DIMM PD AND CONFIGURATION TABLES
`Release 7
`
`Page 5 of 8
`
`
`
`JEDEC Standard No. 21–C
`Page 4.6.1–6
`
`Interface
`Voltage
`
`RFU
`
`LVTTL
`
`RFU
`
`RFU
`
`3.3 V
`
`RFU
`
`Figure 4.6.1–E
`278 PIN 144 BIT SDRAM DIMM MECHANICAL KEY DEFINITION
`
`Pin Name
`A0....A15
`DQ0....DQ143
`CK, CK
`CKE
`S0, S1
`RE
`CE
`W
`DQM
`DQMB0....DQMB17
`VDD
`VDDQ
`VREF
`VSS
`VSSQ
`NU
`RFU
`Notes:
`1.
`NU pin is reserved for board test control of PLL, Make no connection at system level.
`2
`RFU pins are available for future standardization of serial Presence Detect and VTT.
`
`Function
`Address Input (multiplexed)
`Data Input/Output (common)
`Clock Input
`Clock Enable Input
`Chip Select Input
`Row Enable (RAS) Input
`Column Enable (CAS) Input
`Write Enable Input
`Data Mask
`Byte Data Mask input
`Primary Positive Power Supply
`Posivite Power for Input/Output
`Reference Power Supply
`Ground
`Ground for data Input/Output
`Reserved for board test of PLL
`Reserved for Future Use
`
`Number
`16
`144
`2
`1
`2
`1
`1
`1
`1
`18
`14
`27
`2
`14
`27
`1
`7
`
`Figure 4.6.1–F
`278 PIN 144 BIT SDRAM DIMM PIN DEFINITIONS
`Release 7
`
`Page 6 of 8
`
`
`
`JEDEC Standard No. 21–C
`Page 4.6.1–7
`
`DQ64
`
`DQ71
`DQMB8
`DQ72
`
`DQ79
`DQMB9
`
`DQ80
`
`DQ87
`DQMB10
`DQ88
`
`DQ95
`DQMB11
`
`DQ96
`
`DQ103
`DQMB12
`DQ104
`
`DQ111
`DQMB13
`
`DQ112
`
`DQ119
`DQMB14
`DQ120
`
`DQ127
`DQMB15
`
`DQ128
`
`DQ135
`DQMB16
`DQ136
`
`DQ143
`DQMB17
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`D4
`
`D5
`
`D6
`
`D7
`
`D8
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`D0
`
`D1
`
`D2
`
`D3
`
`REGISTER
`
`CKE
`S0
`S1
`W
`CE
`RE
`
`AO–An
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ16
`
`DQ23
`DQMB2
`DQ24
`
`DQ31
`DQMB3
`
`DQ32
`
`DQ39
`DQMB4
`DQ40
`
`DQ47
`DQMB5
`
`DQ48
`
`DQ55
`DQMB6
`DQ56
`
`DQ63
`DQMB7
`
`CK
`
`PLL
`CLOCK
`BUFFER
`
`FEEDBACK
`
`Notes:
`1, A 10 (cid:1) (cid:1) 20% resistor shall be wired in series with all
` DQn lines near the card edge conector.
`2. All clock lines from the PLL Clock Buffer shall be of
` equal length.
`
`Figure 4.6.1–G
`278 PIN X144 BUFFERED SDRAM DIMM 1 BANK with X16 SDRAM
`Release 7
`
`Page 7 of 8
`
`
`
`JEDEC Standard No. 21–C
`Page 4.6.1–8
`
`REGISTER
`
`CKE
`S0
`S1
`W
`CE
`RE
`
`AO–An
`
`DQ0
`
`DQ7
`DQMB0
`DQ8
`
`DQ15
`DQMB1
`
`DQ16
`
`DQ23
`DQMB2
`DQ24
`
`DQ31
`DQMB3
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D0
`
`D1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D9
`
`D10
`
`DQ64
`
`DQ71
`DQMB8
`DQ72
`
`DQ79
`DQMB9
`
`DQ80
`
`DQ87
`DQMB10
`DQ88
`
`DQ95
`DQMB11
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D4
`
`D5
`
`
`
`DQ0 DQ0
`
`
`DQ7DQ7
`
`DQMBODQMBO
`
`DQ8DQ8
`
`
`DQ15DQ15
`
`DQMB1DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D13
`
`D14
`
`DQ32
`
`DQ0
`
`DQ0
`
`DQ96
`
`DQ0
`
`DQ0
`
`DQ39
`DQMB4
`DQ40
`
`DQ47
`DQMB5
`
`DQ48
`
`DQ55
`DQMB6
`DQ56
`
`DQ63
`DQMB7
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D2
`
`D3
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D11
`
`D12
`
`CK0
`
`PLL
`CLOCK
`BUFFER
`
`FEEDBACK
`
`Notes:
`1, A 10 (cid:1) (cid:1) 20% resistor shall be wired in series with all
` DQn lines near the card edge conector.
`2. All clock lines from the PLL Clock Buffer shall be of
` equal length.
`
`DQ103
`DQMB12
`DQ104
`
`DQ111
`DQMB13
`
`DQ112
`
`DQ119
`DQMB14
`DQ120
`
`DQ127
`DQMB15
`
`DQ128
`
`DQ135
`DQMB16
`DQ136
`
`DQ143
`DQMB17
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D6
`
`D7
`
`D8
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`DQ0
`
`DQ7
`DQMBO
`DQ8
`
`DQ15
`DQMB1
`
`D15
`
`D16
`
`D17
`
`Figure 4.6.1–H
`278 PIN X144 BUFFERED SDRAM DIMM 2 BANKS with X16 SDRAM
`Release 7
`
`Page 8 of 8
`
`
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