U.S. Patent 6,516,442
`Petition for Inter Partes Review
`
`Docket No.: 0100157.00263US1
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`PATENT:
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`6,516,442
`
`INVENTORS: YUANLONG WANG, BRIAN BIARD, DANIEL FU, EARL
`COHEN, CARL AMDAHL
`
`FILED:
`
`ISSUED:
`
`TITLE:
`
`MARCH 30, 1999
`
`FEBRUARY 4, 2003
`
`CHANNEL INTERFACE AND PROTOCOLS FOR CACHE
`COHERENCY IN A SCALABLE SYMMETRIC
`MULTIPROCESSOR SYSTEM
`
`
`
`___________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`EMC Corporation
`Petitioner
`
`v.
`
`Intellectual Ventures II, LLC
`Patent Owner
`
`Case IPR2016-01106
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,516,442
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
`
`
`
`

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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`
`TABLE OF CONTENTS
`
`Introduction .......................................................................................................... 1 
`I. 
`II.  Mandatory Notices ............................................................................................... 2 
`A.  Real Party-in-Interest .................................................................................... 2 
`B.  Related Matters ............................................................................................. 2 
`C.  Counsel .......................................................................................................... 3 
`D.  Service Information ....................................................................................... 3 
`III. Certification of Grounds for Standing ................................................................. 3 
`IV. Overview of Challenge and Relief Requested ..................................................... 3 
`A.  Prior Art Patents and Printed Publications .................................................... 4 
`B.  Level of Ordinary Skill in the Art ................................................................. 4 
`C.  Relief Requested ........................................................................................... 5 
`V.  Overview of the ’442 Patent ................................................................................ 5 
`A.  Purported Invention of the ’442 Patent ......................................................... 5 
`B.  Summary of the Prosecution History ............................................................ 9 
`VI. Claim Construction ............................................................................................ 11 
`A.  “switch fabric” (claims 1, 24) ..................................................................... 11 
`B.  “packet” (claims 1-2, 24, and 25 ) .............................................................. 13 
`C.  “channel” (claims 1-2, 12, 24-25, 28, 34) ................................................... 14 
`D.  “interface” (claims 1-2, 5, , 12, 24, 34) ....................................................... 15 
`E. 
`“error correction” (claims 1 and 24) ........................................................... 19 
`F. 
`“error correction code” (claims 2 and 25) ................................................... 20 
`VII.  GROUNDS FOR CHALLENGE ............................................................... 21 
`A.  Overview of Prior Art ................................................................................. 23 
`B.  Ground 1: Claims 1, 2, 12, 24, 25, and 34 are anticipated by Reschke ...... 31 
`C.  Ground 2: Claims 1, 2, 12, 24, 25, and 34 are obvious over Reschke ........ 64 
`D.  Ground 3: Claims 5, 9, 10, 28, 32, and 33 would have been obvious over
`Reschke in view of Nishtala........................................................................ 65 
`E.  Ground 4: Claims 2 and 25 would have been obvious over Reschke in view
`of Müller ...................................................................................................... 75 
`
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`VIII.  Conclusion ................................................................................................... 79 
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`
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`ii
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
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`I.
`
`INTRODUCTION
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`U.S. Pat. No. 6,516,442 (“the ’442 patent,” Ex. 1001) concerns a shared-
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`memory multi-processor system in which processors and memory are
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`interconnected through the use of a switch fabric. The ‘442 applicants asserted that
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`their use of a switch fabric – providing “multiple concurrent buses” so that
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`multiple processors could concurrently access data stored in memory – was an
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`improvement over the prior art, which (the applicants believed) required processors
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`to compete for access to a shared system bus. (Ex. 1002, ¶24.)
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`During prosecution, it soon became clear that the applicants’ concept of
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`using a switch fabric was not new. To secure allowance, the applicants accordingly
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`changed course, and amended their claims to additionally require that the
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`interfaces to the switch, processors, and memory perform error correction.
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`But the concept of interfaces performing error correction – like the concept
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`of using a switch fabric – was old and had already been disclosed in multiple prior
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`art references. In fact, the precise configuration the applicants claimed as novel
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`was previously disclosed in U.S. Patent No. 5,490,250 to Reschke et al.
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`(“Reschke,” Ex. 1003), which was not before the Examiner during prosecution.
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`Among other prior art references, Reschke discloses a shared-memory
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`multiprocessor system that uses a switch fabric to provide multiple concurrent
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`buses between the various components of the system, including multiple
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`1
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`processors and shared memory, and that has interfaces that perform error
`
`correction. (Ex. 1002, ¶91.)
`
`In sum, all of the features of the ’442 claims were well known in the art
`
`years before the ’442 priority date. (Ex. 1002, ¶58.)
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`EMC Corporation (“EMC” or “Petitioner”) is the real party-in-interest.
`
`B. Related Matters
`The ’442 patent is assigned to Intellectual Ventures II LLC and has been
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`asserted four times: On July 8, 2015, Intellectual Ventures I LLC and Intellectual
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`Ventures II LLC. (collectively, “Intellectual Ventures” or “Patent Owner”) sued
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`HCC Insurance Holdings, Inc. and related entities in the Eastern District of Texas.
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`Intellectual Ventures I LLC. et al. v. HCC Insurance Holdings, Inc. et al. (6:15-cv-
`
`660). On Feb. 23, 2016, Intellectual Ventures II LLC sued Kemper Corporation
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`and related entities in the Eastern District of Texas. Intellectual Ventures II LLC v.
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`Kemper Corp. et al. (6:16-cv-081). On May 10, 2016, Intellectual Ventures sued
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`EMC Corp. (Petitioner), Lenovo Group Ltd., and related entities in the District of
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`Massachusetts. Intellectual Ventures I LLC. et al. v. Lenovo Group Ltd., et al.
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`(1:16-cv-10860). On May 11, 2016, Intellectual Ventures sued NetApp, Inc. in the
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`2
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`District of Massachusetts. Intellectual Ventures I LLC. et al. v. NetApp, Inc. (1:16-
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`cv-10868).
`
`C. Counsel
`Lead Counsel:
`Peter M. Dichiara (Registration No. 38,005)
`
`Backup Counsel: Brian M. Seeve (Registration No. 71,721)
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`Service Information
`
`D.
`E-mail: peter.dichiara@wilmerhale.com, brian.seeve@wilmerhale.com
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`Post and Hand Delivery: WilmerHale, 60 State St., Boston MA 02109
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`Telephone: 617-526-6000
`
`Petitioners consent to service by email.
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`III. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the ‘442 patent is
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`available for inter partes review and that Petitioner is not barred or estopped from
`
`requesting an inter partes review challenging the patent claims on the grounds
`
`identified in this Petition.
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`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
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`claims 1, 2, 5, 9, 10, 12, 24, 25, 28, and 32-34 of the ’442 Patent (the “challenged
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`claims”) and requests that each challenged claim be canceled.
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`Prior Art Patents and Printed Publications
`
`A.
`Petitioner relies upon the patents and printed publications listed in the Table
`
`of Exhibits, including:
`
`1. U.S. Patent No. 5,490,250 to Reschke et al., filed Dec. 31, 1991. (Ex. 1003).
`
`2. U.S. Patent No. 5,581,729 to Nishtala et al., Filed Mar. 31, 1995. (Ex. 1004).
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`3. Müller, William G., “Storage Controller Chip”, published in Spruth, W. The
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`Design of a Microprocessor. Stamped Dec. 14, 1989 by the Library of
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`Congress (“Müller,” Ex. 1005).
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`Level of Ordinary Skill in the Art
`
`B.
`The ’442 patent relates to the field of computing technology in general, and
`
`more specifically the field of computer systems architecture. At the time the ’442
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`patent was filed, a person of ordinary skill in this field would have had at least a
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`bachelor’s degree in computer science or electrical engineering and 3-5 years of
`
`professional experience in computer systems design, or a master’s or doctorate and
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`1-2 years of professional experience in computer systems design, or equivalent
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`academic experience. Such a person would have been familiar with computer
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`systems architecture and design, and would have been aware of design trends
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`relating to multiprocessing systems, switch fabrics, and shared-memory
`
`techniques. (Ex. 1002, ¶22.)
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
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`C. Relief Requested
`Petitioner requests that the Patent Trial and Appeal Board cancel the
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`challenged claims because they are unpatentable under 35 U.S.C. §§ 102 and 103
`
`as set forth in this Petition. This conclusion is supported by the declaration of Dr.
`
`Douglas Clark, Ph.D. (“Clark Declaration,” Ex. 1002), filed herewith.
`
`V. OVERVIEW OF THE ’442 PATENT
`A.
`Purported Invention of the ’442 Patent
`The ’442 patent describes systems and methods for transferring data among
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`the components of a shared-memory multiprocessor system, including multiple
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`processors, a switch fabric, and a shared memory.
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`The ’442 patent applicants contended that prior art multiprocessor systems
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`were limited because they required each of the processors in the system to access
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`memory using a shared system bus, causing problems for systems with large
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`numbers of processors . (Ex. 1001, 1:18-20, 1:36-40.) In particular, they claimed
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`that such an architecture “limits the scalability” of multiprocessor systems because
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`“[a]s more processors are added, eventually, system performance is limited by the
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`saturation of the shared system bus.” (Ex. 1001, 1:37-40.) Thus, according to the
`
`’442 patent, there was a need for a multiprocessor system architecture “that
`
`provides greater scalability by permitting concurrent use of multiple buses” and
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`that “further provides increased transaction throughputs.” (Ex. 1001, 1:41-46.) (Ex.
`
`1002, ¶24.)
`
`The ’442 patent purports to address this need with a “multiprocessor system
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`[that] includes a switched fabric (switch matrix) for data transfers that provides
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`multiple concurrent buses that enable greatly increased bandwidth between
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`processors and shared memory.” (Ex. 1001, 1:49-54.) (Ex. 1002, ¶25.)
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`Fig. 3, reproduced below (with color added), shows the basic components of
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`the system:
`
`
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`’442 Patent, Fig. 3
`(Ex. 1001, Fig. 3)
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`The system includes multiple microprocessors (CPUs 120, top), a shared
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`memory (SDRAM 1300-1303, right), and a Flow Control Unit (FCU 220, center.)
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`The FCU includes, among other things, a switch fabric (red) composed of multiple
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`vertical and horizontal buses 320 and 340 and node switches 380, and integrated
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`switch interfaces 3102 and 3108 (green). (Ex. 1001, 4:45-6, 4:59-61, 5:33-35.) (Ex.
`
`1002, ¶29.)
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`The microprocessors 120 communicate with microprocessor interfaces
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`(CCUs 210, purple), which, in turn, exchange data packets over a set of channels
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`112 (orange) with switch interfaces 3102 (green). (Ex. 1001, 2:51-3, 56-60 and 65-
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`7.) The memory 1300-4 communicates with memory interfaces (MCUs 230,
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`yellow), which exchange data packets over another set of channels 114 (orange)
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`with switch interfaces 3108 (green). (Ex. 1001, 2:51-3,56-60 and 3: 26-30.) (Ex.
`
`1002, ¶30.)
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`The microprocessor, memory, and switch interfaces each include a “channel
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`interface block” (CIB). (Ex. 1001, 5: 20-23.) As the ’442 patent explains, “the CIB
`
`presents a simple, logical interface to a Channel” (Ex. 1001, 6:49; see also 1:56-7),
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`and “forms a full-duplex, bidirectional interface between the core logic and the
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`Channel.” (Ex. 1001, 15:23-26.) (Ex. 1002, ¶32.)
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`The microprocessor, memory, and switch interfaces also perform error
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`correction. As the ’442 patent states, each packet exchanged over the channels
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`includes data as well as “ECC” bits. (Ex. 1001, 6:52-60.) These ECC (i.e., “error-
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`correction code”) bits provide information about the data in the packets so that
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`errors can be detected and corrective action can be taken. For example, in one
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`embodiment, the interfaces perform error correction using an ECC code. (Ex.
`
`1001, 16:50-55.) In other embodiments, the interfaces examine the ECC to
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`determine whether an error has occurred and, if so, request a retransmission of the
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`packet. (Ex. 1001, 15:8-18; see also id. at 16:50-56 (“the CIB logic … must
`
`generate ECC, detect errors, and invoke a retry procedure for error recovery”).)1
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`(Ex. 1002, ¶33.)
`
`The ’442 patent also discusses maintaining “cache coherency.” Typically, in
`
`multiprocessor systems with shared memory, each processor maintains a local
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`store (or “cache”) of data on which it has recently operated. It accordingly is
`
`necessary to maintain consistency between the caches of the various processors, so,
`
`for example, when one processor has altered the contents of the shared memory,
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`the changes can be “seen” by the other processors in the system, before they
`
`attempt to read the altered data. Maintaining the processor caches in a consistent
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`state is known in the art as “cache coherency.” (Ex. 1002, ¶35.)
`
`The ’442 patent maintains cache coherency by requiring all transactions
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`between the processors and shared memory to be “funneled” through a centralized
`
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` This retry procedure is described in more detail in “Channel Transport and Retry
`
` 1
`
`Procedure.” (Ex. 1001, 20:10 et seq..)
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`controller. Specifically, as the ’442 patent explains, the FCU includes “a single,
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`system-serialization point” – the Transaction Controller – which serves as “the
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`‘funnel’ through which all transactions must pass” so that “a precise order of
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`transactions can be defined.” (Ex. 1001, 3:55-63.) The Transaction Controller
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`maintains a set of “cache tags” that duplicate state information in the cache tags
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`maintained in each of the processors’ local caches, to keep track of the status of the
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`individual processor caches and to ensure that they remain consistent with each
`
`other. (Ex. 1001, 4:4.) The transaction controller supports the MOSEI and MESI
`
`cache state protocols, which were well known in the art by the priority date of the
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`’442 patent. (Ex. 1001, 3:22-3.) (Ex. 1002, ¶36.)
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`Summary of the Prosecution History
`
`B.
`The ’442 patent issued from U.S. Patent Appl. No. 09/281,749, filed on
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`March 30, 1999, and is a continuation-in-part of U.S. Patent Appl. No. 09/163,294
`
`(now U.S. Patent No. 6,292,705), which in turn is a continuation-in-part of U.S.
`
`Patent Appl. No. 08/986,430 (now U.S. Patent No. 6,065,077.)
`
`During prosecution, the Examiner rejected the original independent claims
`
`as anticipated by U.S. Patent No. 6,279,084 to VanDoren et al. (“VanDoren”),
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`which is directed to optimizing data flow in a switch-based, multi-processor
`
`system. (Ex. 1009, p. 2; Ex. 1008, Abstract.) The Examiner found that VanDoren
`
`teaches “the claimed shared memory multi processor system and method of
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`operation with a plurality of switch interfaces and processors with interconnects
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`(column 7 lines 1-13)” that are “configured to exchange packet data (column 8
`
`lines 1-3) between memory and processors (column 8 lines 19-42) using error
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`correction (column 6 lines 56-58, column 8 lines 1-4.)” (Ex. 1009, pp. 2-3.)
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`The applicants, in response, amended what became independent claim 1 and
`
`24 to further require “a plurality of channels configured to transfer the packets”
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`and to require a plurality of switch interfaces, a plurality of microprocessor
`
`interfaces, and a memory interface each configured to “exchange the packets over
`
`the channels, and perform error correction of the data in the packets exchanged
`
`over the channels.” (Ex. 1010, p. 11.)
`
`In the subsequent Notice of Allowability, the Examiner focused on these
`
`amendments: “the claimed invention recites limitations [] in which the error
`
`correction of the data in the packets transferred over the channels is performed in
`
`the interface [sic] including the switch interfaces. This error correction is
`
`performed on channels where the channel is between the processor and the switch
`
`and where another channel is between the switch and the memory.” (Ex. 1011, p.
`
`2.)
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
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`VI. CLAIM CONSTRUCTION
`In IPR proceedings, claims are currently given their “broadest reasonable
`
`construction in light of the specification.” 37 C.F.R. § 42.100(b.)2 This section
`
`provides proposed constructions under the currently applicable “broadest
`
`reasonable interpretation” (BRI) standard. The following sections will explain why
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`the claims are unpatentable under Petitioner’s proposed BRI constructions, as well
`
`as under any other reasonable construction. Terms not specifically discussed in this
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`section should have their ordinary and customary meaning in light of the
`
`specification, as commonly understood by those of ordinary skill in the art.
`
`“switch fabric” (claims 1, 24)
`
`A.
`The broadest reasonable construction of a “switch fabric,” in the context of
`
`the ’442 specification and claims, is “a communication subsystem that provides
`
`for parallel routing of packets between multiple sources and targets.” (Ex. 1002,
`
`¶43.)
`
`
`
` 2
`
` The Supreme Court is considering whether to change the claim construction
`
`standard for IPRs in Cuozzo Speed Technologies, LLC v. Lee. The outcome of that
`
`case will have no impact on this petition for IPR, because the challenged claims are
`
`unpatentable under any standard.
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`The ’442 specification describes the “switch fabric,” consistent with the
`
`ordinary meaning of the term, as a “Data Switch,” “Switched Matrix,” or
`
`“switched fabric data path” which “provides for parallel routing of transaction data
`
`between multiple initiators [or sources] and multiple targets [or destinations].” (Ex.
`
`1001, 4:30-34; see also 3:6-9 (“The FCU 210 provides a high-bandwidth and low-
`
`latency connection among these components via a Data Switch, also referred
`
`herein as a Simultaneous Switched Matrix (SSM), or switched fabric data path”)
`
`(emphasis added).) The Examiner similarly equated the “switch fabric” with a
`
`“switch” in his Reasons for Allowance, stating that “[t]his error correction is
`
`performed on channels where the channel is between the processor and the switch
`
`and where another channel is between the switch and the memory.” (Ex. 1011, p. 2
`
`(emphasis added).) (Ex. 1002, ¶51.)
`
`Thus, the Board should adopt Petitioner’s construction (above). But under
`
`any applicable claim construction standard, the term would encompass, at a
`
`minimum, a data switch, switch matrix, or switched fabric data path, providing for
`
`parallel routing of packets between multiple sources and targets. (Ex. 1001, 4:30-
`
`34, 3:6-9.) (Ex. 1002, ¶51.)
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
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`“packet” (claims 1-2, 24, and 25 )
`
`B.
`The broadest reasonable construction of a “packet,” in the context of the
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`’442 patent specification and claims, is “a basic unit of transport over a channel.”
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`(Ex. 1002, ¶43.)
`
`The ’442 specification describes a “packet,” consistent with the ordinary
`
`meaning of the term, as “the basic unit of transport over the Channel.” (Ex. 1001,
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`6:52-55 (emphasis added).) As independent claims 1 and 24 confirm, the “packets”
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`contain the “data” that is exchanged between the relevant components over the
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`channels. (Ex. 1001, 1:24.) In the preferred embodiments, the packets are
`
`transmitted in a specified format (i.e., a “frame”) and include data. (Ex. 1001, 6:52-
`
`60 (“In a preferred embodiment, conceptually a packet is a single 80-bit frame
`
`(information unit) exchanged between CIBs…”).) (Ex. 1002, ¶52.)
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`Patent Owner has argued in its ongoing litigation with HCC that “the term
`
`‘packet’ is readily understandable by those skilled in the pertinent art as a ‘unit of
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`transmitted data’.” (Ex. 1006, pp. 14-15 (emphasis added).) It has further stated
`
`that, “if the ‘442 Patent defines the term “packet” at all, it defines it . . . . [as] “a
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`basic unit of transport over the [c]hannel.” (Ex. 1006, p. 15.) Patent Owner should
`
`not be heard to argue for a narrower construction in this proceeding.
`
`Thus, the Board should adopt Petitioner’s construction (above). But under
`
`any applicable claim construction standard, the term would encompass, at a
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`minimum, a basic unit of transport over a channel that is arranged in a specified
`
`format (e.g., a frame). (Ex. 1001, 6:52-55; claims 1, 24.) (Ex. 1002, ¶52.)
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`“channel” (claims 1-2, 12, 24-25, 28, 34)
`
`C.
`The broadest reasonable construction of “channel,” in the context of the ’442
`
`specification and claims, is “a communication path.” (Ex. 1002, ¶43.)
`
`The ’442 specification describes a “channel,” consistent with the ordinary
`
`meaning of the term, as a “communication path.” (Ex. 1001, 6:50-52 (“[t]he CIB
`
`presents a simple, logical interface to a Channel, providing a communication path
`
`(a Channel) to and from a CIB in another IC”) (emphasis added), 7:39-42, 1:57,
`
`Abstract.) Such a communication path would include, for example, the point-to-
`
`point “interconnect bus” referenced in the ‘442 embodiments. (Ex. 1001, 6:40-43
`
`(explaining that “[t]he Channel of the present invention is a general-purpose, high-
`
`speed, point-to-point, full-duplex, bi-directional interconnect bus”) (emphasis
`
`added).) (Ex. 1002, ¶44-46.)
`
`As the Examiner stated in his Notice of Allowability, these point-to-point
`
`channels include a “channel … between the processor and the switch” and
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`“another channel … between the switch and the memory.” (Ex. 1011, p. 2
`
`(emphasis added).)
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`Consistent with Petitioner’s proposed construction, Patent Owner has stated
`
`in its ongoing litigation against HCC that “the ‘442 Patent explains that a ‘channel’
`
`is a communication path.” (Ex. 1006, pp. 15; Ex. 1006.) (Ex. 1002, ¶44-46.)3
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`Thus, the Board should adopt Petitioner’s construction (above). But under
`
`any applicable claim construction standard, the term would encompass, at a
`
`minimum, communication paths such as the point-to-point “interconnect buses” in
`
`the ’442 embodiments, including those between the processors and switch and
`
`those between the switch and memory. (Ex. 1001, 6:40; see also Ex. 1011, p. 2.)
`
`(Ex. 1002, ¶44-46.)
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`“interface” (claims 1-2, 5, , 12, 24, 34)
`
`D.
`The broadest reasonable construction of an “interface,” in the context of the
`
`’442 specification and claims, is “circuitry or logic at the boundaries between
`
`components, through which information is conveyed.” 4 This circuitry or logic
`
`
` 3
`
` In the HCC litigation, there is no dispute over the term “channel.” Patent Owner
`
`made this statement in connection with its arguments concerning the term
`
`“packets.”
`
`4 The claims recite additional functions that each interface must perform. For
`
`example, claim 1 states that the “microprocessor interfaces” exchange data with
`
`the microprocessors, exchange packets with the switch interfaces over the
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`could be a separate standalone component or it could be integrated into other
`
`components. The ’442 specification uses the term “interface,” consistent with the
`
`ordinary meaning of the term, to refer to circuitry or logic at the boundaries
`
`between components. For example, the “microprocessor interfaces” are located at
`
`the boundary between the microprocessor and a channel to the switch; the
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`“memory interface” is located at the boundary between the memory device and a
`
`channel to the switch; and the “switch interfaces” are at the boundary between the
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`switch fabric and a channel to either a microprocessor or memory. (See, e.g., IEEE
`
`Standard Dictionary of Electrical and Electronics Terms 4th Ed.; Ex. 1007 (defining
`
`“interface” (in the context of computer bus architecture) as “[a] shared boundary
`
`between two systems, or between parts of systems, through which information is
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`conveyed”.) The microprocessor, memory, and switch interfaces each include a
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`“channel interface block” (CIB). As the ’442 patent explains, “[t]he CIB forms a
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`
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`channels, and perform error correction of the data in the packets (the claim also
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`recites different functions that are performed by the claimed “switch interfaces”
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`and “memory interfaces”.) (Ex. 1001, claim 1.) By explicitly reciting functionality
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`for each interface, the claim language makes clear what specific functionality must
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`be performed by each, and thus other functions should not be imported into the
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`construction of “interface.”
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`full-duplex, bidirectional interface between the core logic and the Channel” (see
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`’442 patent at 15:23-26; Ex. 1001). The CIB also presents a logical interface to the
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`Channel. (Ex. ’442 patent at 6:49; see also 1:56-7; Ex. 1001.) (Ex. 1002, ¶¶43, 47-
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`50.)
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`The claimed “interfaces” may be separate from other system components, or
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`integrated into other physical components (as distinct parts of an integral whole).
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`For example, in the embodiments in Figure 3 and Figure 2 (below), the
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`microprocessor interfaces (DCIUs 210, purple) and memory interfaces (MCUs
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`230, yellow) are separate physical components:
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`’442 Patent, Fig. 2, showing separate interfaces
`(Ex. 1001, Fig. 2)
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`
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`In the embodiments of Figures 4 and 8, in comparison, these interfaces are
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`not separate but instead are integrated into other components. For example, Figure
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`17
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`U.S. Patent 6,516,442
`Petition for Inter Partes Review
`4 depicts the microprocessor interfaces (purple) integrated into the microprocessors
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`and switch interfaces (green) integrated into the FCU, and Figure 8 also shows a
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`microprocessor interface (purple) integrated into a microprocessor:
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`(Ex. 1001, Figs. 4 (left), 8 (right))
` (See also Ex. 1001, 2:26 (“Fig. 8 is a drawing of a CPU having an integral
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`
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`CCU”) (emphasis added).) Further, in every embodiment, the switch interfaces are
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`not integrated into the FCU. (Ex. 1002, ¶47-50.)
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`Patent Owner has acknowledged in its ongoing litigation with HCC that the
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`claimed “interfaces” may be “contained in the same physical structure” as other
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`components of the system. (Ex. 1006, p. 11-12 (emphasis added).) Patent Owner
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`should not be heard to argue for a narrower construction in this proceeding. Patent
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`Owner urged that “[n]othing in the claims nor the specification requires the
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`interfaces to be physically distinct. Indeed, the specification points the other way.”
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`(Ex. 1006, pp. 11; see also id. at 12 “there is nothing in the claims that require the
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`interfaces to be physically distinct structures.”) 5 (Ex. 1002, ¶47-50.)
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`Thus, the Board should adopt Petitioner’s construction (above). But under
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`any applicable claim construction standard, the term would encompass, at a
`
`minimum, circuitry or logic at the boundaries between components that transmit
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`and receive packets between the components. (See, e.g., Ex. 1001, 5:20-22.) (Ex.
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`1002, ¶47-50.)
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`“error correction” (claims 1 and 24)
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`E.
`The broadest reasonable construction of “error correction,” in the context of
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`the ’442 patent specification and claims, is “reconstruction of erroneous data.”
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`(Ex. 1002, ¶43.)
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`The ’442 patent describes multiple mechanisms for addressing errors in data
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`packets exchanged over channels. For example, the specification refers in several
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`places to “error correction.” (Ex. 1001, 15: 45, 16: 50-56, 26:34-38.) In each
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`instance, it uses the term, consistent with its ordinary and customary meaning, to
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`refer to reconstructing data that has been received with an error. In one
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`
` 5
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` Patent Owner made this statement in connection with a dispute over whether the
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`claimed interfaces must be “distinct” from each other. This dispute has no bearing
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`on the grounds presented in this IPR.
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`19
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`U.S. Patent 6,516,442
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`embodiment, the interface performs error correction using an ECC code. (Ex.
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`1001, 16:50-55.) In another embodiment, the interfaces detect errors and request a
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`retransmission of the packet. (Ex. 1001, 21:14-15 (describing “a mode where the
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`packet received in error is retried”); see also 19:3-5.) (Ex. 1002, ¶53.)
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`In its ongoing litigation with HCC, Patent Owner has taken the position that
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`the term “error correction” has the “broad ordinary meaning” of “reconstruction of
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`erroneous data” (Ex. 1006, p. 9.), and that “error correction” (without the further
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`recitation of the word “code”) does not require codes. (Ex. 1006, p. 10.) Patent
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`Owner should not be heard to argue for a narrower construction in this proceeding.
`
`(Ex. 1002, ¶53.)
`
` Thus, the Board should adopt Petitioner’s construction (above). But under
`
`any applicable claim construction standard, the term would encompass, at a
`
`minimum, reconstruction of erroneous data using an ECC code. (Ex. 1001, 16:50-
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`55.) (Ex. 1002, ¶53.)
`
` “error correction code” (claims 2 and 25)
`
`F.
`The broadest reasonable construction of “error correction code,” in the
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`context of the ’442 patent specification and claims, is “a code that can be used to
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`correct erroneous data.” (Ex. 1002, ¶43.)
`
`As explained above, in the ’442 embodiments, the “error correction code” is
`
`ECC bits. (Ex. 1001, 26:34-38.) ECC code was well known in the prior art as
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`containing information to detect and correct certain bit errors, e.g., single bit errors,
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`and to detect other bit errors, e.g., two bit errors. (See Ex. 1001, 16: 52-55.) (Ex.
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`1002, ¶54.)
`
`In its ongoing litigation with HCC, Patent Owner has taken the position that
`
`the term “error correction code” has a “broad ordinary meaning” of “a code that
`
`can be used to correct erroneous data.” (Ex. 1006, p. 8.) It has also stated that “the
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`’442 Patent discloses that the system can employ an error correction code to
`
`correct single-bit errors,” but the “claims are not limited to that embodiment.” (Id.)
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`Patent Owner should not be heard to argue for a narrower construction in this
`
`proceeding. (Ex. 1002, ¶54.)
`
`Thus, the Board should adopt Petitioner’s construction (above). But under
`
`any applicable claim construction standard, the term would encompass, at a
`
`minimum, error correction code (ECC) that can detect and correct single bit errors.
`
`(Ex. 1001, 16:50-54.) (Ex. 1002, ¶54.)
`
`VII. GROUNDS FOR CHALLENGE
`This Petition, supported by Declaration of Dr. Douglas Clark filed herewith,
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`demonstrates that there is a reasonable likelihood that Petitioner will prevail with
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`respect to at least one challenged claim and that each of the chall