`
`(12) United States Patent
`Hammond et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,219,774 B1
`Apr. 17, 2001
`
`USOO6219774B1
`
`OTHER PUBLICATIONS
`Shanley, Tom and Anderson, Don, ISA SystemArchitecmre,
`~
`~
`Chapters 5, 8, 10, 11, and 18, Published by Mindshare, Inc.
`Second Edition Oct 1993
`'
`'
`i486 [Microprocessor Programmer’s Reference Manual,
`Intel Corporation, 1990, pp. 1—1—1—9, 2—2—2—24,3—1—3—45,
`41411, 51525, 61625, 71715, 8188,
`9—1—9—26,
`19 1 19 6
`21 1 21 5,
`22 1 22 12,
`23—1—23—15, 24—1—24—8, 26—1—26—289.
`
`Kane, Gerry and Heinrich, Joe,]\/[IPS RISC Architecture, pp.
`1 1
`4 30, 6 1
`6 57, 9 1, 9 1
`9 12, Published by
`Prentiss—Hall, Inc. 1992.
`
`
`
`Wyant, Gregg and Hammerstrom, Tucker, How Micropro-
`cessors Work, Intel Corporation 1994, pp. 78—102, 199—185.
`
`Primary Examiner—Kenneth S. Kim
`(74) Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor &
`Zafman LLP
`57
`
`ABSTRACT
`
`)
`(
`A Method and Apparatus for Providing Memory Manage-
`ment and Event Handling Functionality in a Computer
`System. According to one embodiment of the invention, a
`processor comprises an instruction set unit, a segmentation
`unit, and a paging unit. The instruction set unit is to support
`a first and second instruction sets. The segmentation unit is
`coupled to the instruction set unit
`to translate Virtual
`addresses used by the first instruction set into translated
`addresses. The
`unit is coupled to the instruction set
`unit to translate both virtual addresses used by the second
`instruction set and the translated addresses into physical
`addresses. According to another embodiment of the
`invention, a computer system includes an instruction set unit
`and an event handling unit in a processor, as well as a first
`plurality of event handlers that includes a first event handler.
`The instruction set unit is to support a first and second
`instruction sets. Problems that arise during the processing of
`instructions from the first and second instruction sets respec-
`tively causes a first and second set of events. The event
`handling unit
`is to cause the processor to execute the
`appropriate one of the first plurality of eVent handlers. At
`least some of the first set of eVthS are mapped to differth
`ones of the first plurality of event handlers. All of the second
`set of events are mapped to the first event handler.
`
`(54) ADDRESS TRANSLATION WITH/BYPASSING
`INTERMEDIATE SEGMENTATION
`TRANSLATION TO ACCOMMODATE TWO
`
`DIFFERENT INSTRUCTION SET
`ARCHITECTURE
`
`(75)
`
`Inventors: Gary Hammond, Campbell, Donald
`Alpert, Santa Clara, both of CA (US);
`Kevin Kahn, Portland, OR (US);
`Harsh Sharangpani, Santa Clara, CA
`(US)
`
`(73) Assignee:
`
`Intel Corporation, Santa Clara, CA
`(Us)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/048,241
`.
`Flled3
`
`(22)
`
`Mar- 25’ 1998
`
`Rdated U-s- Application Data
`
`(63)
`
`continuation 0f application N0~ 08/482339.- filed 0“ Jun~ 7:
`1995’ now Pat‘ NO‘ 597749686
`
`Int. (11.7 .................................................... ..
`
`(52) U_s_ CL .......................... N 711/202; 711/206; 712/229
`
`_
`(58) Flew 0f searCh ~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~ 712/43> 208> 229;
`703/26; 711/202> 206
`
`(56)
`
`REfEI‘EHCES CitEd
`
`U‘S‘ PATENT DOCUMENTS
`1/1996 Blomgren et al.
`................. .. 712/225
`1/1996 Richter, el al.
`.................... .. 712/212
`0/1990 Inagami et a1.
`........................ .. 712/7
`7/1996 Blomgren ............................. .. 712/41
`
`5,481,693
`5,484,684
`5,530,881 ><
`5,542,059
`
`(List continued on next page.)
`
`14 Claims, 9 Drawing Sheets
`
`INSTRUCTION
`SET
`CONFEGURATlON
`
`EFFECT IVE
`ADDRESS
`
`
`
`SEGMENTATION
`UNIT
`
`
`
`PHYSICAL
`ADDRESS
`
`w
`
`
`
`
`
`215
`
`
`
`PAGING
`UNIT
`(FOR FIRST
`SYSTEM1
`AHCHUECUREJ
`
`
`
`LINEAR
`ADDRESS
`
`w
`
`EMC Exhibit 1027
`
`EMC V. Intellectual Ventures
`IPR2016-01106
`
`
`
`msmucncu
`551
`CDNFIGURAUON
`
`290
`
`

`

`US 6,219,774 B1
`
`Page 2
`
`............................ .. 703/26
`9/1998 Earl et a1.
`5,815,686 *
`5,854,913 * 12/1998 Goetz et a1.
`....................... .. 712/210
`5,953,520 *
`9/1999 Mallick
`703/26
`5,968,162 * 10/1999 Yard
`.. 712/203
`6,021,265 *
`2/2000 Nevill ................................. .. 712/209
`
`
`
`* Cited by examiner
`
`US. PATENT DOCUMENTS
`
`5,574,927 * 11/1996 Scantlin ............................... .. 712/41
`
`5,598,546
`1/1997 Blomgren
`712/209
`4/1998 Jaggar ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~ 712/41
`597409461 *
`5,765,206 *
`6/1998 Hohensee et a1.
`................. .. 711/203
`5,802,382 *
`9/1998 Greenberger et a1.
`712/36
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 1 0f 9
`
`US 6,219,774 B1
`
`INSTRUCTION
`SET
`ARCHITECTURE
`
`110
`
`INSTRUCTION
`SET
`‘
`ARCHITECTURE
`
`120
`
`ARCHITECTURE
`
`SYSTEM
`ARCHITECTURE
`
`SYSTEM
`
`I30
`
`140
`
`Figure 1
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 2 0f 9
`
`US 6,219,774 B1
`
`
`
`
`
`INSTRUCTION
`SET
`CONFIGURATION
`
`INSTRUCTION
`SET
`CONFIGURATION
`
` SEGMENTATION
`
`UNIT
`
`
`
`INSTRUCTION
`SET UNIT 203
`
`SYSTEM
`UNIT 20?
`
`
`
`—---——200
`
`
`
`
`
`EVENT
`HANDLING
`UNIT
`
`
`
`PAGING
`um
`
`
`
`EVENT
`HANDUNG
`um
`
`
`
`Pfigfifi
`
` 233 236
`
`
`
`
`SYSTEM CONFIGURATION 230
`
`SYSTEM CONFI URAHON 40
`
`Figure 2
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 3 0f 9
`
`US 6,219,774 B1
`
`3‘0
`
`
`
`
`OPERAUNG SYSTEM
`330
`
`USER
`PRMLEGE
`LEVEL
`340 — - - — - — -
`
`SYSTEM
`PREVILEGE
`LEVEL
`
`— - — — - ——340
`
`Figure 3
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 4 0f 9
`
`US 6,219,774 B1
`
`INSTRUCUON
`
`INSTRUCTION
`SET
`SET
`CONFtGURATION
`CONFlGURATION
`
`
`
`
`
`
`excemows
`
`
`
`EXCEPTIONS
`
`p
`WENT
`
`use nuns AND
`L
`“gleam
`EXTERNAL
`
`INTERRUPTS
`
`
`
`INTERRUPT
`
`DESCRIPTION
`TABLE
`
`MO
`
`
`P igu re 43
`
`MEHRUPT
`DESCRJPTOR
`TABLE
`“0
`
`GATE 425
` HANDL E R
`4003
`
`
`4005
`
`
`HANDLE R
`MOD
`
`FANOLER
`
`GATE 445 I
`
`*‘igure 4b
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 5 0f 9
`
`US 6,219,774 B1
`
`
`
`
`
`
` EXCEPI IONS
`EXCEPTIONS
`
`EVENT
`HANDLING
`UNIT
`
`TLB
`FAULTS
`AND
`EXTERNAL
`
`EXCEPTIONS WITH
`INTERCEPT GATES
`
`
`
`
`EVENT
`HANDLING
`UNIT
`
`
`EXCEPTIONS WITH
`
`NORMAL GATES
`
`
`
`
`
`INTERRUPT
`DESCRIPTION
`we
`
`
`410
`
`
`was
`
`Figure 53
`
`EVENT HANDLER
`REGION
`510
`
`SECTION
`520
`
`SECTION
`
`
`
`Figure 5b
`
`INT ERHUPT DESCRIPTOR
`TABLE
`410
`
`
`
`
`
`INTE RCEPT
`GATE 435
`
`EVENT
`HANDLING
`UNIT
`
`
`
`
`530
`
`243
`
`INSTRUCTION
`SET
`CONFIGURATION
`
`INSTRUCTION
`SET
`CONFIGURATION
`
`
`
`210
`
`

`

`US. Patent
`
`mhS
`
`US 6,219,774 B1
`
`6.
`
`2Em>m
`
`1.mmr4.~55:59:MEEBEUS.may4i
`
`m«c«2&5ma
`
`7,zczéaugou
`
`5mm:9:
`
`:2:
`
`QmrNCme
`
`
`
`
`:2:zgéawazoo
`
`
`
`
`
`mammogqzgzgzmsommmamas?mm
`
`
`
`
`
`:meiaw>:ow&w20.5352“
`
`
`
`
`
`w>_5w&m298352.9mammoaqwagezQEszowm3939mmM45.9%"$2;
`
`
`
`
`
`éa3E
`
`@251;
`
`E73
`
`ozoowm«5%
`
`2396
`
`.meOthonfi
`
`:23
`
`zozéacazcu
`
`
`
`m3.arm
`
`
`
`mmmmoo,‘Em
`
`
`
`¢<w23ZQSDEmZ
`
`ZOEEDQEEVU
`
`
`
`
`
`
`
`
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 7 0f 9
`
`US 6,219,774 B1
`
`700
`
`an
`
`CONTROL REGISTER 750
`
`
`
`
`
`EVENT HANDLING
`UNIT
`233
`
`
`
`
`
`PAGING UNIT
`236
`
`EVENT HANDLING
`UNIT
`243
`
`PAGING UNIT
`
`SYSTEM UNIT 207
`
`74
`
`CONFIGURATION
`SELECTOR
`740
`
`INEEUUENTITJN
`203
`
`738
`
`737
`
`734
`
`735
`
`CACHE
`
`BUS UNIT
`
`724
`
`NETWORK
`722
`
`730
`
`PROCESSOR 710
`
`DISPLAY
`
`726
`
`KEYBOARD
`
`728
`
`
`
`
`
`OPERATING SYSTEM 770
`
`EVENT
`HANDLING
`INFORMATION
`7770
`
`“SING
`INFORMATION
`785
`
`EVENT
`HANDLING
`INFORMATION
`790
`
`PAGING
`INFORMATION
`795
`
`ROUTINE
`
`760
`
`ROUTINE
`
`765
`
`TORAGE DEVICE 720
`
`Figure 7
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 8 0f 9
`
`US 6,219,774 B1
`
`Em_:2:_Empm>w
`
`O»_
`
`mammmz:
`
`2m
`
`
`
`.5sz295mm
`
`:2:
`
`0%
`
`Sc
`
`awpmfimm
`
`31
`
`m«Sufi
`
`
`
`9K$58:6528EHEE
`
`zOFéDwEZOQEm202.02".me
`
`
`
`comwz:zocuwdm
`
`o:
`
`2053:9500
`
`mokoflmm
`
`llllllulullllql'lllllllllllllllll}
`
`
`
`
`
`rl'lul‘.
`
`I
`
`8m
`
`$5.8m
`
`3....
`
`OMm
`
`awooomm
`
`mmeOQmm
`
`
`
`owe
`
`4
`
`onm1040
`
`5.0mu.
`
`x2ng‘
`
`
`
`
`
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 9 0f 9
`
`US 6,219,774 B1
`
`CONTROL REGISTER 750
`
`m
`
`CONFIGURATION
`SELECTOR
`740
`i_. _ _ _ _ _ _ . _ _ _ _ _ _ _ . __ _
`‘
`SYSTEM CONFIGURATION I
`0 k
`l
`' ' 0
`I
`I
`I
`I
`I 735
`
`
`
`20,
`
`PAGING UNIT
`235
`
`T0
`' CACHE
`I 732
`I
`I
`I
`
`I
`
`I
`
`I
`
`'
`I
`
`733
`
`TO
`'INSTRUCTION
`155T UNIT
`303
`
`I I I I I l I
`
`MUX
`935
`
`“B 9‘5
`
`PAGING UNIT
`246
`
`EVENT HANDLING
`UNIT
`233
`
`EVENT HANDUNG
`UN”
`243
`
`DEMUX
`9.30
`
`
`
`
`
`TLB FAULTS
`
`EXTERNAL INTERRUPTS
`
`7igure 9
`
`'
`‘
`I
`I
`I
`
`I
`
`I
`I
`I
`l
`
`'
`
`i
`
`I
`I
`
`I
`I
`
`I
`1
`
`I I
`
`I
`
`I I I
`
`737
`
`FROM
`INSTRUCTION
`SET UNIT
`203
`
`733
`
`FROM
`INSTRUCTION
`SET UNIT
`ECE
`
`

`

`US 6,219,774 B1
`
`1
`ADDRESS TRANSLATION WITH/BYPASSING
`INTERMEDIATE SEGMENTATION
`TRANSLATION TO ACCOMMODATE TWO
`DIFFERENT INSTRUCTION SET
`ARCHITECTURE
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This is a continuation of “Method and Apparatus for
`Providing Two System Architectures in a Processor,” appli-
`cation Ser. No. 08/482,239, filed Jun. 7, 1995, and issued as
`US. Pat. No. 5,774,686. Ser. No. 08/386,931,
`titled
`“Method and Apparatus for Transitioning Between Instruc-
`tion Sets in a Processor,” filed Feb. 10, 1995, Issued.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The invention relates to the field of electronic data pro-
`cessing devices. More specifically, the invention relates to
`the operation of processors.
`2. Background Information
`As computer systems continue to evolve, it is desirable to
`develop more technologically advanced processors which
`use new instruction sets and/or new resources for supporting
`operating system type functions. For example, it has recently
`become desirable to develop processors which incorporate
`RISC based instruction sets and/or which utilize larger
`address spaces. At the same time, it is desirable to remain
`compatible with the existing base of software (including
`operating systems) developed for previous processors. The
`term architecture is used herein to refer to all or part of a
`computer system, and may include chips, circuits, and
`system programs.
`One prior art architecture which attempted to deal with
`this limitation is implemented in the VAX-11. The VAX-11
`incorporates a new instruction set and extends the PDP—11
`architecture from using 16 addressing bits to using 32
`addressing bits. The VAX-11 is capable of executing appli-
`cation programs written in either the new VAX-11 instruc-
`tion set or the PDP-11 instruction set. However, the VAX-11
`has several
`limitations. One such limitation is that
`the
`VAX-11 cannot execute an application program written with
`instructions from both instruction sets because it lacks the
`ability to share data generated by the different instruction
`sets. Thus, the VAX-11 does not provide the option of using
`the new instruction set where justified by performance
`advantages and using the existing software where justified
`by development cost considerations. As a result, software
`developers have the difficult choice of either incurring large
`development costs to develop an entirely new application
`program or forgoing the benefits offered by the new instruc-
`tion set. Another limitation is that the VAX-11 provides one
`mechanism for supporting operating system type function-
`ality (e.g., only one memory management mechanism and
`only one event handling mechanism) and can only accept an
`operating system written in the new VAX-11 instruction set.
`As a result, previously developed operating systems were
`not compatible, and an entirely new operating system had to
`be developed. Further limitations of the VAX-11 include a
`lack of non-privileged transitions between VAX-11 and
`PDP-11 instruction set modes, PDP-11 floating-point
`instructions, privileged execution in the PDP-11 instruction
`set mode, and input/output accessing in the PDP-11 instruc-
`tion set mode.
`
`Another prior art architecture which faces this limitation
`is the Intel® 386 processor (manufactured by Intel Corpo-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`ration of Santa Clara, Calif.). The 386 processor expanded
`the Intel 286 processor (manufactured by Intel Corporation
`of Santa Clara, Calif.) architecture from 16 bits to 32 bits.
`However, the 386 processor did not include a new instruc-
`tion set, but expanded the instruction set used by the 286
`processor. In addition, the 386 processor provided only one
`method of implementing operating system type functions.
`Another prior art architecture which faces this limitation
`is implemented in the MIPS R4000 processor manufactured
`by MIPS Computer Systems, Inc. of Sunnyvale, Calif. The
`R4000 processor expanded the R3000 processor to 64 bits.
`However,
`the R4000 processor did not
`include a new
`instruction set, but just expanded the instruction set used by
`the R3000 processor.
`In addition,
`the R4000 processor
`provided only one method for providing operating system
`type functions.
`SUMMARY OF THE INVENTION
`
`A processor having two system configurations is pro—
`vided. The apparatus generally includes an instruction set
`unit, a system unit, an internal bus, and a bus unit. The
`instruction set unit, the system unit, and the bus unit are
`coupled together by the internal bus. The system unit is
`capable of selectively operating in one of two system
`configurations. The first system configuration provides a
`first system architecture, while the second system configu-
`ration provides a second system architecture. The bus unit is
`used for sending and receiving signals from the instruction
`set unit and the system unit. According to another aspect of
`the invention, the instruction set unit is capable of selec-
`tively operating in one of two instruction set configurations.
`The first instruction set configuration provides for the execu-
`tion of instruction belonging to a first instruction set, while
`the second instruction set configuration provides for the
`execution of instructions belonging to a second instruction
`set.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The invention may best be understood by referring to the
`following description and accompanying drawings which
`illustrate the invention. In the drawings:
`FIG. 1 illustrates a functional block diagram of one
`embodiment of the invention;
`FIG. 2 is a functional block diagram illustrating the
`different selectable configurations in which a processor may
`operate according to one embodiment of the invention;
`FIG. 3 is a functional block diagram illustrating software
`for use according to one embodiment of the invention;
`FIG. 4a is a functional block diagram illustrating one
`technique of event handling according to one embodiment of
`the invention;
`FIG. 4b is a functional block diagram illustrating the
`information stored when using the selectable configuration
`shown in FIG. 4a according to one embodiment of the
`invention;
`FIG. 5a is a functional block diagram illustrating another
`technique of event handling according to one embodiment of
`the invention;
`FIG. 5b is a functional block diagram illustrating the
`information stored when using the selectable configuration
`shown in FIG. 5a according to one embodiment of the
`invention;
`FIG. 6a is a functional block diagram illustrating one
`method of memory management according to one embodi-
`ment of the invention;
`
`

`

`US 6,219,774 B1
`
`3
`FIG. 6b is a functional block diagram illustrating another
`method of memory management according to one embodi—
`ment of the invention;
`FIG. 7 is a functional block diagram of a computer system
`according to one embodiment of the invention;
`FIG. 8 illustrates a functional block diagram of instruction
`set unit 203 according to one embodiment of the invention;
`and
`
`FIG. 9 illustrates a functional block diagram of system
`unit 207 according to one embodiment of the invention.
`DETAILED DESCRIPTION
`
`In the following description, numerous specific details are
`set forth to provide a thorough understanding of the inven-
`tion. However, it is understood that the invention may be
`practiced without these specific details. In other instances,
`well-known circuits, structures and techniques have not
`been shown in detail in order not to obscure the invention.
`
`Although a more detailed explanation will be provided
`below,
`it
`is thought worthwhile to first provide a brief
`overview of the invention. This application describes a
`method and apparatus for providing a processor which
`incorporates a new instruction set and advanced resources
`for providing operating system type support (e.g., event
`handling, memory management, etc.), while maintaining
`compatibility with previously developed software. In one
`embodiment, the processor can selectively operate in one of
`two instruction set configurations and in one of two system
`configurations. The first instruction set configuration and
`system configuration are similar to and compatible with
`previously developed processors, and thus are compatible
`with existing software (including operating systems).
`However, the second system configuration provides a new
`system architecture which supports different techniques for
`providing typical operating system type functions.
`In
`addition, the second instruction set configuration provides a
`new instruction set architecture for which new software
`
`(including operating systems) can be written. Furthermore,
`either instruction set configuration can be used in conjunc-
`tion with either system configuration. As a result, single
`programs may utilize both instruction sets, and operating
`systems may use both system architectures.
`FIG. 1 shows a functional block diagram illustrating an
`overview of one embodiment of the invention. FIG. 1 shows
`an instruction set architecture 110, an instruction set archi-
`tecture 120, a system architecture 130, and a system archi-
`tecture 140.
`
`Instruction set architecture 110 is used for executing
`instructions from a first instruction set, while instruction set
`architecture 120 is used for executing instructions from a
`second instruction set. Thus, instruction set architectures 110
`and 120 include all necessary software, firmware and hard-
`ware to provide for the execution of two instruction sets—
`one instruction set each. In one embodiment, instruction set
`architecture 110 is a CISC (complex instruction set
`computing) type architecture substantially compatible with
`an existing instruction set for the Intel x86 Microprocessor
`family. However, in this embodiment, instruction set archi-
`tecture 120 is an advanced instruction set architecture which
`supports a new instruction set. Of course, alternative
`embodiments may implement the instruction set architec-
`tures in any combination of CISC, RISC, VLIW, or hybrid
`type architectures. In addition, alternative embodiments may
`implement the instruction set architectures to support two
`new instruction sets (one instruction set each) or to support
`two existing instruction sets (one instruction set each).
`
`4
`technique of
`System architecture 130 supports a first
`performing operating system type functions,
`including
`memory management and event handling. In contrast, sys-
`tem architecture 140 supports a second technique of per-
`forming operating system type functions, including memory
`management and event handling. Thus, system architectures
`130 and 140 each include all necessary software, firmware,
`and hardware to provide for typical operating system func-
`tionality. In one embodiment, system architecture 130 is
`compatible with previously developed operating systems
`(such as MS-DOS and Windows available from Microsoft
`Corporation of Redmond, Wash.), while system architecture
`140 provides advanced resources which new operating sys—
`tems may utilize.
`In addition, FIG. 1 shows that both instruction set archi-
`tectures 110 and 120 may be used in conjunction with either
`of system architectures 130 and 140. In this manner, com-
`patibility is maintained with the existing software base
`(including operating systems) developed for instruction set
`architecture 110 and system architecture 130, while allowing
`for the development of new software (including operating
`systems) which uses the new instruction set architecture 120
`and system architecture. As an example, an operating system
`written in one of the instruction sets and using one of the
`system architectures can multitask applications written in
`either of the instruction sets. While one embodiment is
`described in which both instruction set architectures 110 and
`120 may interact with either of system architectures 130 and
`140, alternative embodiments may not support all of the
`interactions described in FIG. 1. For example, alternative
`embodiments may not support interaction between instruc-
`tion set architecture 120 and system architecture 130.
`One aspect of the invention is that the processor supports
`multiple system architectures. Thus, the number of instruc-
`tion sets and/or system architectures supported, as well as
`the type of instruction sets and system architectures
`supported, are not critical to this aspect of the invention.
`What is important to this aspect of the invention is that the
`processor can switch between the instruction set architec-
`tures and system architectures. For example, alternative
`embodiments may support one instruction set and two
`system architectures. As another example, alternative
`embodiments may support three instruction set architectures
`and two system architectures. Other alternative embodi-
`ments may support three instruction set architectures and
`three system architectures. An embodiment which supports
`two instruction set architectures and two system architec-
`tures is described so as not to obscure the invention.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`FIG. 2 shows a functional block diagram illustrating the
`selectable configurations or modes of a processor according
`to one embodiment of the invention. FIG. 2 shows a line 200
`
`55
`
`60
`
`65
`
`representing that the processor includes an instruction set
`unit 203 and a system unit 207. FIG. 2 also shows that
`instruction set unit 203 selectively operates in either an
`instruction set configuration 210 or in an instruction set
`configuration 220. In one embodiment, instruction set con—
`figuration 210 includes segmentation unit 215. Segmenta-
`tion unit 215 allows for compatibility with existing x86
`memory management techniques which utilize segmenta—
`tion. In addition, FIG. 2 shows system unit 207, which
`selectively operates in either a system configuration 230 or
`a system configuration 240.
`Instruction set unit 203 executes instructions from a first
`
`instruction set while instruction set configuration 210 is
`selected. In one embodiment,
`this first instruction set
`is
`based on the 16/32-bit x86 instruction set used by existing
`Intel microprocessors. This instruction set operates using
`
`

`

`US 6,219,774 B1
`
`5
`what are referred to as effective or logical addresses. Instruc-
`tion set configuration 210 sends these effective addresses to
`segmentation unit 215 which translates them into linear
`addresses. The technique of segmentation is well known in
`the prior art and is further described in the following
`reference: Shanley, Tom and Anderson, Don, ISA System
`Configuration, MindShare, Inc. (1993). Thus, instruction set
`configuration 210 with segmentation unit 215 provides a
`first instruction set architecture. Alternative embodiments
`which support other
`instruction sets may require other
`address translation techniques (rather than or in addition to
`segmentation), or may not require any address translation.
`Instruction set unit 203 executes instructions from a
`second instruction set which is different from the first
`instruction set, while instruction set configuration 220 is
`selected. In one embodiment, this second instruction set is a
`64-bit instruction set which operates using the same format
`of address generated by segmentation unit 215 (i.e., linear
`addresses). Since this 64—bit
`instruction set uses linear
`addresses, it can address the entire 64-bit Virtual address
`space and does not require segmentation. In this manner,
`instruction set configuration 220 provides a second instruc-
`tion set architecture.
`
`instruction set unit 203 includes all necessary
`Thus,
`software, firmware, and hardware to provide for the execu-
`tion of two instruction sets. In one embodiment, instruction
`set unit 203 includes at least one prefetch unit, decode unit,
`and execution unit, as well as a mechanism for switching
`between the two instruction set configurations (not shown).
`One embodiment of instruction set unit 203 will be later
`described with reference to FIG. 8. While one embodiment
`of instruction set unit 203 has been described in which it is
`
`implemented on the processor, alternative embodiments
`could implement all or part of instruction set unit 203 in
`hardware residing outside the processor, or in software.
`System unit 207 provides a first system architecture while
`system configuration 230 is selected. This first system
`architecture supports typical operating system functions
`according to a first system technique. In one embodiment,
`system configuration 230 is compatible with existing x86
`processors and includes an event handling unit 233 and a
`paging unit 236. Event handling unit 233 provides for the
`selection of the appropriate service routine or handler in
`response to each of a predefined set of events according to
`a first event handling method or technique. It is worthwhile
`to note that the term “event” is used herein to refer to any
`action or occurrence to which a computer system might
`respond (i.e., hardware interrupts, software interrupts,
`exceptions, traps, faults, etc). As will be further described
`later with reference to FIGS. 5a and 5b, in one embodiment,
`event handling unit 233 may be implemented in a corre-
`sponding fashion to that of previous x86 based Intel micro-
`processors (i.e., an interrupt descriptor table stored in
`memory containing pointers to service routines). In one
`embodiment, paging unit 236 provides for Virtual memory
`by allowing for the translation of the linear addresses
`generated by both segmentation unit 215 and instruction set
`configuration 220 into physical addresses according to a first
`paging method or technique. As will be described later with
`reference to FIG. 6a, paging unit 236 is implemented in a
`corresponding fashion to that of previous x86 based Intel
`microprocessors (i.e.,
`the linear addresses outputted by
`segmentation unit 215 and instruction set configuration 220
`are used by paging unit 236 to identify a page table, a page
`described in that table, and an offset within that page).
`In contrast, system unit 207 provides a second system
`architecture while system configuration 240 is selected. This
`
`6
`second system architecture is different than the first system
`architecture and supports typical operating system functions
`according to a second system technique. In one embodiment,
`system configuration 240 includes an event handling unit
`243 and a paging unit 246. Event handling unit 243 provides
`for the selection of the appropriate service routine or handler
`in response to an event according to a second event handling
`method or technique. As will be further described later with
`reference to FIGS. 6a and 6b, one embodiment of event
`handling unit 243 is implemented using an event handler
`region stored in memory. The event handler region is broken
`down into fixed size sections (also termed as “entries”) of
`512 bytes, each containing a 64—bit handler (if additional
`space is needed to store a handler, a jump may be made to
`another area in memory). One or more events are assigned
`to each section. In response to an event, the processor stores
`event
`information identifying the event, determines the
`section in the event handler region to which that event
`corresponds, and begins executing the handler stored in that
`entry. The handler uses the event information stored by the
`processor to determine which event has occurred and ser-
`vices that event (i.e., executes the appropriate set of
`instructions). In one embodiment, paging unit 246 provides
`for virtual memory by allowing for the translation of the
`linear addresses generated by both segmentation unit 215
`and instruction set configuration 220 into 64-bit physical
`addresses according to a second paging method or tech-
`nique. As will be further described later with reference to
`FIG. 6b, paging unit 246 is implemented using an operating
`system specific algorithm stored in memory in one embodi-
`ment of the invention. Thus, this system configuration leaves
`the definition of the translation algorithms and page data
`structures up to the operating system. In this manner, the
`addressing range is increased to 264 bytes and the operating
`system is free to implement any one of a number of paging
`schemes.
`
`Thus, system unit 207 represents all necessary firmware
`and hardware to provide for two approaches to supporting
`operating system type functions. System unit 207 includes
`memory management hardware, event handling hardware,
`and a mechanism for switching between the two system
`configurations. While one embodiment has been described
`in which system unit 207 is implemented on the processor,
`alternative embodiments could implement all or part of
`system unit 207 in hardware or software residing outside the
`processor. One embodiment of system unit 207 will be later
`described with reference to FIG. 9.
`
`FIG. 2 also shows that both instruction set configuration
`220 and instruction set configuration 210 with segmentation
`unit 215 may be selectively used in conjunction with both
`system configuration 230 and system configuration 240. In
`this manner,
`the processor provides for two alternative
`instruction set architectures and two alternative system
`architectures.
`
`It is readily understood that the number of bits for either
`instruction set architectures (e. g., a 32—bit instruction set and
`a 64-bit instruction set) and either system architectures (e. g.,
`16/32 bits and 64 bits) is a design choice. For example, an
`alternative embodiment may support 64—bit and 128—bit
`instruction set architectures and system architectures. As
`another example, an alternate embodiment may support two
`instruction set architectures and/or system architectures of
`the same size (e.g., 32-bit).
`Switching between instruction set architectures and sys-
`tem architectures may be accomplished using a variety of
`mechanisms. In one embodiment, to provide for the selec-
`tion of the different configurations, the processor contains a
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`

`

`US 6,219,774 B1
`
`7
`control register within which it stores: 1) an extension flag
`which enables the selection of instruction set configuration
`220 and system configuration 240, 2) an instruction set flag
`which allows for the selection of either of instruction set
`
`configuration 210 or 220 (while such selection is enabled by
`the extension flag), and 3) a system flag which allows for the
`selection of either of system configuration 230 or 240 (while
`such selection is enabled by the extension flag). Thus,
`depending on the status of these flags, the processor con-
`figures the hardware to operate in the selected configuration.
`The operating system can alter the states of these indications
`to select the configuration of choice.
`In this embodiment, when the computer is turned on, the
`BIOS boots the computer storing the extension flag in the
`disable state. While the extension flag indicates the disable
`state, both instruction set configuration 210 and system
`configuration 230 are selected and both the instruction set
`flag and the system flag are ignored. Thus, the processor
`boots in the mode illustrated by line 1 in FIG. 2. In this
`manner, if a previously developed operating system which
`does not support the new instruction set or system configu-
`ration is executed, the extension flag will remain in the
`disable state; thereby preventing programs from attempting
`to use the new instruction set or system configuration.
`However, the x86 based instruction set used by instruction
`set configuration 210 includes a new instruction for altering
`the state of the extension flag. This allows new operating
`systems that support the use of the new instruction set and/or
`system configuration to alter the state of the extension flag
`to the enable state, thereby causing the current configuration
`of the processor to be selected based on the instruction set
`flag and the system flag. As will be further described, both
`the x86 based instruction set and the 64-bit based instruction
`set also include instructions for altering the states of the
`instruction set flag and system flag. This allows software to
`switch between the different configurations of the processor.
`Thus, when the extension flag is in the enable state,
`the
`processor may be caused to operate in any one of the modes
`illustrated by lines 1, 2, 3, and 4 of FIG. 2. For example, the
`instruction set flag ande the system flag may be altered to
`select instruction set configuration 210 and system configu—
`ration 240 (i.e., the mode represented by line 2 of FIG. 2).
`When the processor switches system configurations, the
`processor must be re-configured. This re-configuring
`depends on the implementation, but can include purging all
`prior system configuration information, flushing one or more
`TLBs, flushing registers