Standards & Documents Search: DIMM | JEDEC
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`112 Pin MPDRAM DIMM
`
`Release No.9
`
`Document # (/standards-documents/results
`/taxonomy%3A2873?order=field_doc_full_number_value&
`sort=asc)
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`Date (/standards-documents/results
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`
`MODULE 4.4.6
`
`Jun 1997
`
`Results 1 - 20 of 63
`
`Committee(s): JC-42.3 (/committees/jc-423c-0), JC-42 (/committees/jc-423c-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE 4.4.6 (/sites/default/files/docs/4_04_06.pdf)
`
`278 Pin Buffered SDRAM DIMM MODULE 4.6.1
`
`Jun 1997
`
`Release No.9
`
`Committee(s): JC-42.3 (/committees/jc-423c-0), JC-42 (/committees/jc-423c-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE 4.6.1 (/sites/default/files/docs/4_06_01.PDF)
`
`168 Pin DRAM DIMM
`
`MODULE4_05_01
`
`Mar 1999
`
`Release No.9
`
`Committee(s): JC-42.3 (/committees/jc-423c-0), JC-42 (/committees/jc-423c-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE4_05_01 (/sites/default/files/docs/4_05_01R9.pdf)
`
`168 Pin Unbuffered DRAM
`DIMM
`
`MODULE4_05_03
`
`Release No. 9
`
`Committee(s): JC-42 (/committees/jc-423c-0)
`
`Jun 1999
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE4_05_03 (/sites/default/files/docs/4_05_03R9.pdf)
`
`DEFINITION OF CDCV857 PLL
`CLOCK DRIVER FOR
`REGISTERED DDR DIMM
`APPLICATIONS:
`
`JESD82
`
`Jul 2000
`
`This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a
`1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was
`also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333.
`
`Committee(s): JC-40 (/committees/jc-404-0)
`
`Download JESD82 (/sites/default/files/docs/JESD82.pdf)
`
`184 Pin Unbuffered SDR
`SDRAM DIMM Family
`
`MODULE4_05_11
`
`Oct 2000
`
`1 of 5
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`Standards & Documents Search: DIMM | JEDEC
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`Title (/standards-documents
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`Release No.10
`
`Document # (/standards-documents/results
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`Date (/standards-documents/results
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`
`Committee(s): JC-42 (/committees/jc-423c-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE4_05_11 (/sites/default/files/docs/4_05_11R10.pdf)
`
`STANDARD FOR
`DESCRIPTION OF A 3.3 V,
`18-BIT, LVTTL I/O REGISTER
`FOR PC133 REGISTERED
`DIMM APPLICATIONS:
`
`JESD82-2
`
`Jul 2001
`
`This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective
`of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module.
`
`Committee(s): JC-40 (/committees/jc-404-0)
`
`Download JESD82-2 (/sites/default/files/docs/JESD82-2.pdf)
`
`200 Pin SDRAM DIMM
`
`MODULE 4.5.2
`
`Oct 2001
`
`Release No.11
`
`Committee(s): JC-42.5 (/committees/jc-423c-0), JC-42 (/committees/jc-423c-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE 4.5.2 (/sites/default/files/docs/4_05_02R11.pdf)
`
`168 Pin Registered SDRAM
`DIMM Family
`
`MODULE4_5_07
`
`Release No.11
`
`Committee(s): JC-42.5 (/committees/jc-423c-0)
`
`Oct 2001
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE4_5_07 (/sites/default/files/docs/4_05_07R11.pdf)
`
`STANDARD FOR
`DESCRIPTION OF A 3.3 V,
`ZERO DELAY CLOCK
`DISTRIBUTION DEVICE
`COMPLIANT WITH THE
`JESD21-C PC133
`REGISTERED DIMM
`SPECIFICATION
`
`JESD82-5
`
`Jul 2002
`
`This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of
`the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the
`latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently
`under development for DDR2 support devices.
`
`Committee(s): JC-40 (/committees/jc-404-0)
`
`Download JESD82-5 (/sites/default/files/docs/JESD82-5.pdf)
`
`Registration - Addition of 172
`pin Micro DIMM variations and
`modification of terminal
`
`MO-214-B
`
`Sep 2002
`
`2 of 5
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`

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`postional tolerance to Micro
`DIMM registration. Item
`11.14-049.
`
`0.50 mm Lead Centers
`
`Committee(s): JC-11 (/committees/jc-1114-2), JC-11.14 (/committees/jc-1114-2)
`
`JEP95 Registrations Main Page (/category/technology-focus-area/jc-10/registered-outlines-jep95)
`
`Download MO-214-B (/sites/default/files/docs/mo-214b.pdf)
`
`184 Pin Unbuffered DDR
`SDRAM DIMM
`
`Release No.12
`
`MODULE4_05_10
`
`Apr 2003
`
`Committee(s): JC-42.3 (/committees/jc-423c-0), JC-42 (/committees/jc-423c-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE4_05_10 (/sites/default/files/docs/4_05_10R12.pdf)
`
`240-Pin Unbuffered and
`Registered DDR2 SDRAM DIMM
`Family
`
`Release No. 12
`
`MODULE4_05_14
`
`Apr 2003
`
`Committee(s): JC-42.5 (/committees/jc-423c-0), JC-42 (/committees/jc-423c-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE4_05_14 (/sites/default/files/docs/4_05_14R12.pdf)
`
`STANDARD FOR DEFINITION
`OF THE SSTV16859 2.5 V,
`13-BIT TO 26-BIT SSTL_2
`REGISTERED BUFFER FOR
`STACKED DDR DIMM
`APPLICATIONS:
`
`JESD82-4B
`
`May 2003
`
`This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859
`13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device,
`for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use
`
`Committee(s): JC-40 (/committees/jc-404-0)
`
`Download JESD82-4B (/sites/default/files/docs/JESD82-4B.pdf)
`
`Registration - 244 Pin
`DDR2/DDR3 Mini DIMM with
`0.60 mm Lead Centers Socket
`Outline. Item 11.14-122.
`
`SO-002B
`
`Oct 2003
`
`Committee(s): JC-11 (/committees/jc-1114-2), JC-11.14 (/committees/jc-1114-2)
`
`JEP95 Registrations Main Page (/category/technology-focus-area/jc-10/registered-outlines-jep95)
`
`Download SO-002B (/sites/default/files/docs/SO-002B.pdf)
`
`DIMM Design Files
`
`DIMM Homepage
`
`Dec 2003
`
`These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to
`downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure.
`
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`Standards & Documents Search: DIMM | JEDEC
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`See DIMM Homepage information (http://www.jedec.org/standards-documents/technology-focus-areas/memory-module-design-file-registrations)
`
`DEFINITION OF CU878 PLL
`CLOCK DRIVER FOR
`REGISTERED DDR2 DIMM
`APPLICATIONS
`
`JESD82-11
`
`Sep 2004
`
`This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CU878 PLL clock
`device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CU878 PLL clock device, for uniformity, multiplicity of
`sources, elimination of confusion, ease of device specification, and ease of use.
`
`Committee(s): JC-40.3 (/committees/jc-404-0), JC-40 (/committees/jc-404-0)
`
`Download JESD82-11 (/sites/default/files/docs/JESD82-11.pdf)
`
`DEFINITION OF THE
`SSTV16857 2.5 V, 14-BIT
`SSTL_2 REGISTERED BUFFER
`FOR DDR DIMM
`APPLICATIONS:
`
`JESD82-3B
`
`Nov 2004
`
`This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16857
`14-bit SSTL_2 registered buffer for DDR DIMM applications.The purpose is to provide a standard for the SSTV16857 logic device, for uniformity,
`multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
`
`Committee(s): JC-40.3 (/committees/jc-404-0)
`
`Download JESD82-3B (/sites/default/files/docs/JESD82-3B.pdf)
`
`DEFINITION OF THE
`SSTV32852 2.5 V 24-BIT TO
`48-BIT SSTL_2 REGISTERED
`BUFFER FOR 1U STACKED
`DDR DIMM APPLICATIONS:
`
`JESD82-6A
`
`Nov 2004
`
`This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852
`24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device,
`for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
`
`Committee(s): JC-40 (/committees/jc-404-0)
`
`Download JESD82-6A (/sites/default/files/docs/JESD82-6A.pdf)
`
`100-Pin DDR SDRAM
`Unbuffered 32b-DIMM Design
`Specification
`
`Release No. 14
`
`MODULE4_20_09
`
`Nov 2004
`
`Committee(s): JC-42 (/committees/jc-423c-0), JC-45 (/committees/jc-456-0)
`
`JESD21-C Solid State Memory Documents Main Page (/category/technology-focus-area/memory-configurations-jesd21-c)
`
`Download MODULE4_20_09 (/sites/default/files/docs/4_20_09R14.pdf)
`
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