`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
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`EMC CORPORATION,
`PETITIONER,
`
`V.
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`INTELLECTUAL VENTURES II LLC,
`PATENT OWNER.
`______________
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`Case IPR2016-01106
`Patent 6,516,442 B1
`______________
`
`Record of Oral Hearing
`Held: September 7, 2017
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`______________
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`Before JUSTIN T. ARBES, BRIAN J. McNAMARA, and MINN CHUNG,
`Administrative Patent Judges.
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`Case IPR2016-01106
`Patent 6,516,442 B1
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`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`PETER M. DICHIARA, ESQUIRE
`WILMER CUTLER PICKERING HALE
`and DORR LLP
`60 State Street
`Boston, MA 02109
`(617) 526-6466
`
`THEODOROS KONSTANTAKOPOULOS, ESQUIRE
`WILMER CUTLER PICKERING HALE
`and DORR LLP
`399 Park Avenue
`New York, NY 10022
`(212) 295-6367
`
`ON BEHALF OF THE PATENT OWNER:
`JOHN R. KING, ESQUIRE
`BRIDGET A. SMITH, ESQUIRE
`KNOBBE MARTENS
`2040 Main Street
`Fourteenth Floor
`Irvine, CA 92614
`(949) 760-0404
`
` ALSO PRESENT:
` TOM BROWN
` JAMES HIETALA
`
`The above-entitled matter came on for hearing on Thursday,
`September 7, 2017, commencing at 1:30 p.m. at the U.S. Patent and
`Trademark Office, 600 Dulany Street, Alexandria, Virginia, in Courtroom
`A.
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`Case IPR2016-01106
`Patent 6,516,442 B1
`P R O C E E D I N G S
` JUDGE ARBES: Good afternoon. Please be seated.
` Welcome. This is the oral hearing in Case
`IPR2016-01106 involving Patent 6,516,442.
` Can counsel please state your names for the
`record?
` MR. DICHIARA: Yes. My name is Peter Dichiara,
`and with me today is Theodoros Konstantakopoulos for
`petitioner.
` MR. KING: Good afternoon, your Honors. I am John
`King, lead counsel for the Patent Owner Intellectual
`Ventures. With me at counsel table is backup counsel Bridget
`Smith. And behind me, I'd just like to introduce James
`Hietala, representative of patent owner.
` JUDGE ARBES: Thank you.
` Per the Trial Hearing Order in this case, each
`party will have 30 minutes of time to present arguments. And
`the order of presentation is first petitioner will present
`its case regarding the challenged claims and may reserve time
`for rebuttal. Patent owner then will respond to petitioner's
`presentation and petitioner then may use any remaining time
`to respond to patent owner's presentation.
` Two reminders before we begin. To ensure that the
`transcript is clear, and because we have one judge participating
`remotely, please only speak at the podium and try to refer to
`your demonstratives by slide number.
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` Also, if either party believes that the other
`party is presenting improper argument, I would ask you to
`please raise that issue during your own presentation rather
`than interrupting the other side.
` Any questions before we begin?
` MR. DICHIARA: No, your Honor.
` JUDGE ARBES: Counsel for petitioner, you may
`proceed. Would you like to reserve time for rebuttal?
` MR. DICHIARA: Yes, I would.
` Good afternoon. May it please the board, my name
`is Peter Dichiara and with he today is Theodoros
`Konstantakopoulos and we represent the Petitioner EMC in the
`matter IPR2016-01106. With us today is Mr. Tom Brown from
`the petitioner.
` We're here today to discuss the '442 patent and
`why the challenged claims are unpatentable, and my intent is
`to first begin discussing the issues under the board's
`current construction and then to reserve any remaining time
`for rebuttal.
` And on the screen here on slide 3, I have a figure
`from the '442 patent. The '442 patent discloses what's known
`as a shared memory multiprocessor system. As you can see in
`the figure, it has a switch fabric shown in red, switch
`interfaces shown in green, processor and memory interfaces
`shown in purple and yellow, respectively, and not shown in
`the figure is that the interfaces perform error correction.
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` Reschke is our primary reference. And as we see
`on slide 5, Reschke is also a shared memory multiprocessor
`system. And we use the same color coding to depict that it
`has the same basic components as the '442 patent. Reschke's
`main thrust, in fact, is dealing with errors in switches.
` Turning to slide 6, I have identified what I
`believe are the disputes under the board's current
`construction.
` And in slide 7, I have the board's current claim
`constructions for channel, switch fabric and packet, just as
`a reminder.
` In turning to what I believe is the first issue,
`which is whether or not Reschke's channels are full duplex
`channels, on slide 8, I have our annotated figures for
`figures 4A and 4B. And as background, the patent owner does
`not dispute that Reschke's channels are bi-directional
`channels. Instead, their argument seems to be that the
`petitioner did not do enough to establish that these channels
`are specifically full duplex channels, which is a form of
`bi-directional channel, as is half duplex. Those are the two
`species, if you will, of bi-directional channels. And
`petitioner believes that patent owner is just wrong on that
`point.
` You'll recall that our petition discussed these
`figures at length, as did Dr. Clark. And in connection with
`those -- that discussion, we had discussed figure 4A for the
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`ingress portion or the forward portion of the channels, and
`that's for data coming into the switch. And in figure 4B, we
`discussed the egress portion for the same channels for data
`leaving the switch. And those portions, those two separate
`portions, are like two separate lanes of a highway. One is
`going eastbound; one is going westbound; one is going into
`the switch; one is going out of the switch. And those
`portions and those pathways are the entities that provide the
`capability for full duplex communications. You can have data
`going into the switch; you can have data going out of the
`switch simultaneously.
` And on that point, as we mentioned in our papers,
`IV has not disputed that figure 4A and 4B has two separate
`portions of a channel. Instead, turning to slide 9, they
`premise some arguments on Exhibit 2007, which is their
`exhibit, and as we maintained in our papers, this exhibit
`actually proves petitioner's point. They referred to it in
`their patent owner response at page 48 and, oddly, they
`focussed on the definition for "duplex transmission."
` And during Dr. Alpert, patent owner's expert's
`deposition, I had asked him about the other definition, one
`definition removed about duplex channel, specifically because
`we felt it was the more relevant definition, and he
`confirmed, as you can see here on the slide, that, in fact, a
`duplex channel or full duplex channel -- this dictionary
`happens to use "duplex" for "full duplex" -- is about a
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`capability; it is about something being allowed to happen.
` And in this regard, we believe that the board had
`it exactly right in their decision to institute when they
`phrased the question as whether the forward or reverse
`pathways can operate at the same time.
` Dr. Clark's testimony, both his written testimony
`and his deposition testimony, both times over, are perfectly
`on point talking about this capability, and, indeed, similar
`to before, the patent owner has not in its papers disputed
`this capability. Instead, their focus has been on whether or
`not actual transmissions happen, which, as we maintained in
`our papers, is a function of the software running at the
`time, and just like a highway can have two lanes and
`sometimes there's traffic flowing in both directions,
`sometimes there isn't, that doesn't mean the highway is not
`full duplex just because there's not cars traveling on it.
` JUDGE ARBES: Counsel, was this explanation
`regarding the capability, was that made in the petition or in
`Dr. Clark's initial declaration? I believe that patent owner
`pointed to paragraph 137 of the declaration where Dr. Clark
`made the statement that there are full duplex interconnect
`buses, but that explanation was not there. Why is that?
` MR. DICHIARA: In terms of capability and could?
` JUDGE ARBES: Yes.
` MR. DICHIARA: I don't think he used those words
`because I think this came up as a result of the patent owner
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`response where they said -- actually, it was at pages 53 and
`54 of the patent owner response where they said, quote, "The
`question is not whether Reschke can provide full duplex
`transmissions," and it's our point, no, it is precisely the
`question. We maintain that Reschke discloses, doesn't render
`obvious, actually discloses full duplex channels, and when
`you're talking about full duplex channels, you're talking
`about a two-lane highway with the capability to send data in
`and out simultaneously. So, the capability point came up in
`response to the patent owner response.
` JUDGE ARBES: I guess my question is why is it
`sufficient to only have the statement from Dr. Clark in
`paragraph 137 that there are full duplex channels without any
`explanation?
` MR. DICHIARA: I think --
` JUDGE ARBES: And is that your only evidence that
`was cited in the petition?
` MR. DICHIARA: No, your Honor, not at all, and
`I'll mention a couple of different things on that.
` One of the first things is, and I hope to get to
`it later with some more materials, is that the patents
`themselves, right, both patents, both the '442 and the
`Reschke patent, talk about these data switches and that
`they're supposed to provide multiple simultaneous
`transactions going on at any given time, which we discussed
`at some length in our petition. And the notion that somehow
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`the switch would do all of that and then the channels would
`only be one-lane highways operating one at a time is
`fundamentally inconsistent with the purpose of what these
`switches are all about, which we also discussed in our
`petition about the simultaneous transactions going through
`the switch.
` The other point I would like to raise on this,
`because, again, this is their exhibit, is if you take a look
`at that last sentence, they refer to half duplex. That's the
`other form of bi-directional communication. You can have
`uni-directional communication; you can have bi-directional.
`Bi-directional falls into two species, full duplex and half
`duplex.
` And here's the critical part. Half duplex
`requires a prohibition. You can only have communication in
`one direction at a time. And to use the highway analogy,
`that might be that one-lane road when there's construction or
`something like that and you can't have cars going on that one
`lane in opposite directions at that time or you can imagine
`why, and, so, there's either a traffic gate or a traffic
`officer or something to prevent it.
` And, so, all of Dr. Clark's testimony was
`concerned with the ingress and egress portions -- and, again,
`its portions, two separate lanes of one channel, saying the
`switch is allowing all this data to come in and out to the
`multiple destinations from the multiple initiators.
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` JUDGE ARBES: Counsel, if I have a reference like
`Reschke that says we have bi-directional communications but
`it does not say specifically whether there is full duplex or
`half duplex, why is it appropriate to just assume that it
`could be full duplex?
` MR. DICHIARA: Well, I wouldn't say you assume it
`with nothing more. What I would say is you have to take a
`look at all the facts that are going on, and what we have in
`these systems are these switch fabrics that are allowing
`massive number of transactions to go on simultaneously, and
`the notion that the channels would prevent that is
`inconsistent with it.
` I would also take a look at half duplex,
`specifically half duplexes used in instances where there's
`either not a lot of communication expected from both entities
`or there's something peculiar about the channel. Like us
`talking to each other right now, if we only had one frequency
`in which to carry our data on, we both can't drive the
`channel at the same time without a problem. Sometimes that
`happens because, whatever, your satellite or something like
`that, or in the old days with bluetooth, there would be
`master/slave relationships where one device only spoke when
`some other device said it's your turn to talk. Right? So,
`there would be something intrinsic to prevent both entities
`driving the same wire or the same frequency at the same time.
` That's not what Reschke is showing. They're
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`showing a very classic architecture with separate input
`ports, separate output ports, nothing preventing the
`communications from occurring simultaneously. The whole
`purpose of Reschke is to have massive amount of parallelism,
`just like the '442 patent. So, it would be inconsistent with
`reading Reschke to say somehow the channels are preventing
`the switch fabric from doing what it's intended to do.
` JUDGE ARBES: So, there would have to be some sort
`of limitation disclosed in Reschke for the person of ordinary
`skill in the art reading it to say that's half duplex, that's
`not full duplex.
` MR. DICHIARA: You would -- you would see, like,
`different transceivers or different control structures. You
`would see something intrinsic in the architecture to say
`there's only one wire or one frequency on which these two
`entities may communicate and we have to prevent that from
`happening or bad things can happen, distortion, things like
`that. And, so, that's not -- that's not the purpose of it.
` JUDGE McNAMARA: So, is it your position that a
`person of ordinary skill reading Reschke would understand
`that that applies to a full duplex system even though Reschke
`never actually discusses a full duplex system?
` MR. DICHIARA: Well, I would say it does discuss.
`It doesn't use the words "full duplex."
` JUDGE McNAMARA: That's the issue.
` MR. DICHIARA: But I think -- yeah, I think that
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`the description of the system is completely consistent with
`full duplex and completely inconsistent with the notion that
`they would have said let's do all this parallelism but then
`put these channels to try and somehow throttle that. You
`would have expected them to say that if there's something
`unusual. That's not the case. And maybe I --
` JUDGE CHUNG: Counsel?
` MR. DICHIARA: Yes, your Honor.
` JUDGE CHUNG: This is Judge Chung. So, patent
`owner argues that figure 2 of Reschke shows that Reschke's
`channel is half duplex -- duplex, so how do you respond to
`that? What does figure 2 show?
` MR. DICHIARA: Right. I don't think they actually
`ever say it's half duplex, and I don't think they ever made
`that allegation anyplace. I think what they said is that it
`merely shows bi-directional and then said somehow we didn't
`provide enough to show it was specifically full duplex.
` The problem with figure 2 is it's more about a
`conceptual diagram showing only one -- one of these pathways.
`And if -- and if I may, I can make this point great with this
`next slide 10.
` You'll recall that the board encouraged both
`parties to address specifically the forward and reverse
`portions, the ingress and egress portions or pathways in the
`decision to institute at page 30. And that -- to Judge
`Chung's point, it was in response to the popper just
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`mentioning figure 2.
` And what -- what we have here on this slide is
`Dr. Clark's annotations of figures 4A and 4B, and it also
`includes 4C because you actually have -- when you take a look
`at figure 4A through C, there are 8 pathways, not one like in
`figure 2, which is just trying to show data traveling through
`the switch, there are the 8 pathways.
` And what he did on this annotation and in his
`testimony is he set up a specific example where processor
`131, the one in the upper left, is trying to talk to a
`memory, 141, and simultaneously memory 141 can be sending
`data back to that same processor. And when that happens, you
`will have simultaneous communications on two channels between
`processor 131 and the switch and between the switch and the
`memory. And this is completely allowed, completely
`permissible. This is why there are eight separate pathways.
` And in the middle of that pathway -- I can't see
`the number very well, but you'll see QWD0 -- I think it's
`440A. There are buffers. Data goes into the switch. It's
`buffered. Subsequently, it's unloaded out of that buffer and
`sent on its way with the destination unload path, the egress
`channel.
` And, so, he explained exactly how simultaneous
`communications could occur on channels using this figure and
`it explained that this was just an example of that.
` If there are no further questions on full duplex,
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`I would like to turn to the next issue that I think is
`present under the board's current construction, which is
`whether or not it's obvious to modify the memory and
`processor interfaces to perform error correction. That's an
`argument that they raise in the patent owner response at
`pages 58 through 60.
` And as we noted in our reply, this argument
`doesn't enjoy the support of their expert. Their expert
`never made the comment it would be not obvious to do such an
`error correction at the processor and memory.
` And you'll recall that in our petition, we had
`mentioned that it would be obvious to do so for the very same
`reasons that the switch interfaces error correction, namely
`to correct errors on the channel, and that, indeed, this was
`textbook knowledge at the time, and we had cited Siewiorek,
`and turning to slide 12, that we had also Dr. Clark testify
`on this issue.
` Now, the patent owner at a few points in the
`patent owner response, two or three times, made the comment
`that there's -- there's no evidence or simply no evidence of
`the notion that modifying the processor and memory interfaces
`to perform error correction is obvious. And as we mentioned
`in our reply, there's plenty of evidence. There's the
`evidence we had in our petition, but even the patent's own
`file history demonstrates this point.
` And it's not just the examiner, it's the patentee,
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`the patent owner at the time, had said that the prior art of
`record, Van Doren, had both processors and memories which
`performed error correction and the reason the claims were
`allowed was that the examiner believed that Van Doren didn't
`teach switch interfaces with error correction. That's not in
`dispute here. No one disputes that Reschke's switch
`interface has such error correction.
` So, turning briefly to the next issue, which is, I
`think, the dispute whether a person of skill in the art would
`be motivated to combine the teachings of Reschke and
`Nishtala, as we mention on slide 14, Dr. Clark had testified
`about this shared memory multiprocessor systems would enjoy
`the benefit of something known as cache coherence, whether
`each of the processors are going to see the correct view of
`memory, and he testified about this at length.
` And turning to slide 14 -- 15, I apologize, we
`have the testimony from Dr. Alpert confirming that, in fact,
`shared memory multiprocessors would enjoy such benefit. A
`person of skill in the art would be motivated to turn to
`Nishtala's teachings about his techniques for obtaining cache
`coherence and we believe this combination is completely
`proper.
` And then the last issue I would like to discuss in
`this portion of the presentation is dependent claim 5, which
`is also disputed under the board's current constructions.
`And on the screen here, I have claim 5, and I have the
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`specific snippet from Nishtala concerning this P_FE or R
`signal, and as we maintained in our papers, both our petition
`and in our reply, the level of overlap is at the embodiment
`level.
` The '442 patent never uses the term "synchronous
`reset" anyplace. They do use some other signal names that go
`into their interfaces, including the power-on reset, and
`that's precisely what Nishtala is teaching. So, it's our
`position that dependent claim 5 is clearly shown.
` The one thing I would raise on this is there seems
`to have been some confusion in the patent owner response. We
`were relying on Nishtala for the signal. We were relying on
`Reschke for the interfaces. And, essentially, their attack
`was that Nishtala didn't have the three interfaces. And our
`response, as we explained in the reply, is we weren't relying
`on Nishtala for the three interfaces. We were relying on
`Reschke for the three interfaces and Nishtala for the
`power-on reset signal that would go to different places.
` And if there are no further questions, I will just
`reserve my remaining time for rebuttal.
` JUDGE ARBES: You may proceed.
` MR. KING: Good afternoon -- good afternoon, your
`Honors. During the next 30 minutes, I'm going to focus on
`three issues, first being that Reschke is not a mechanized
`system. I'll just focus briefly on that. Second is that
`Reschke does not teach performing error correction in all the
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`interfaces. And I'm going to focus specifically on the
`microprocessor interface. And, third, I'm going to discuss
`how Reschke does not disclose a full duplex bus.
` Let's move now to slide number 4. In slide number
`4, which I've highlighted here, we have a switch fabric
`configured to switch packets containing data. The board
`construed the word "packet" to mean a basic unit of transport
`over the channel. Petitioner, however, treats the
`construction to mean just a base -- to mean just a basic unit
`over the channel. No weight is given to transport, no
`meaning.
` If the word "packet" is construed to just be the
`basic unit over the channel, it would cover systems that send
`a single byte over a channel. Such systems are not viewed as
`packetized systems.
` Patent owner's expert, Dr. Alpert, stated in his
`declaration and deposition that "transport" is a -- is a
`technical word that needs to be interpreted in light of the
`specification. We've said it's a defined -- we've said that
`"packet" is a defined word, and we look at it based on the
`specification.
` Dr. Alpert states in page 195 of his deposition
`transcript, and I'll quote, "but as I recall, it's a sentence
`that's at column 6, about line 53, that says 'packet,'"
`that's in quotes, "is a basic unit of transport over the
`channel. Question: Okay. And did you testify that this
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`Case IPR2016-01106
`Patent 6,516,442 B1
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`sentence, the word 'transport' refers to the transport
`layer?" Then we have an objection. And then Dr. Alpert's
`answer, "Yes, I believe a person of ordinary -- ordinary
`skill in the art would understand that both from this
`sentence and from other disclosures in the patent that talk
`about the transport layer."
` Also, on page 89 of his deposition transcript, he
`states that -- that one of ordinary skill in the art would
`understand that the packet was being used for a transport
`layer over the network.
` In Dr. Alpert's declaration, he goes on to say
`that in order to transmit packets over a transport layer,
`quote, "control information in the packets is essential for
`packet switching to operate correctly and efficiently."
` We contend that the word "packet" is construed to
`be a basic unit of transport and the word "transport" has to
`be given its technical meaning as set forth in the
`specification. This means that the packet needs to be able
`to send data on a transport layer which receive -- which
`requires at least data and control information.
` I'd like to now move to my second argument.
` JUDGE ARBES: Counsel, can I ask you one question
`before you do?
` MR. KING: Yes.
` JUDGE ARBES: The portion of column 6 that
`petitioner has pointed to, the sentence at line 53, "A packet
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`Case IPR2016-01106
`Patent 6,516,442 B1
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`is the basic unit of transport over the channel," we have
`that sentence. And the paragraph immediately before that
`begins with the heading "Channel Overview and Terminology."
` MR. KING: Right.
` JUDGE ARBES: So, why is that sentence not a
`definition of "packet" given that -- that heading there?
` MR. KING: We argued that we thought it ought to
`be given its ordinary and customary meaning. But for the
`purposes of this oral hearing, I would like to assume that is
`the defined definition of "packet."
` JUDGE ARBES: Okay. And we just need to shed
`further light on what "transport" means then.
` MR. KING: Yeah. I think because we're given a
`defined term, a technical term as defined in the
`specification, the word "transport" is defined in the
`abstract, is defined in column 2 with respect to the
`drawings, it's defined in column 6 in other places, every
`time as associated with a transport layer that uses the
`transport protocol.
` And because it's kind of just out there, basic
`unit of transport, if you ignore the word, it means anything.
`It just means anything can be -- that's transferred -- that
`is transmitted on a channel. And we think it has a technical
`meaning.
` I'd like to move now --
` JUDGE CHUNG: Counsel?
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`Case IPR2016-01106
`Patent 6,516,442 B1
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` MR. KING: Yes. Yes, judge.
` JUDGE CHUNG: So, let me get a little technical
`here. So, if you're arguing that only, you know, packets --
`at the transport layer are data packets, what is IP
`packets? You know, I have a background in telecommunication.
`So, I mean, right, so, actually, packets get transmitted over
`IP layer. Why isn't IP packets data packets?
` MR. KING: Yeah, I think what I'm saying is in
`light of this specification, every time the word "transport"
`is used, it's referring to the transport layer, the physical
`transport layer. And when we say it's a basic unit of
`transport, we're just saying there ought to be some technical
`definition given to that word. But I don't want to spend too
`much time on this. I would like to move to the second
`argument that focusses on the microprocessor interface.
` Can we move to slide 20, please. Slide 20, we see
`the claim, and we see that there are these three interfaces.
`I'm just going to focus on the microprocessor interface.
` We see here that the plurality of microprocessor
`interfaces configure to exchange data with a plurality of
`microprocessors. Microprocessors and microprocessor
`interfaces are different. This is an interface that
`exchanges data with the microprocessor and then also
`exchanges packets with the switch interfaces or the channels
`and performs error correction of the data in the packets
`exchanged over the channels.
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`Case IPR2016-01106
`Patent 6,516,442 B1
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` I want to emphasize that these claimed interfaces
`are distinguished from the components they interface with.
`Switch interface exchanges with the switch. The
`microprocessor interface exchanges with the microprocessors.
`The memory interface exchanges with the memory.
` The important question here is not whether it was
`known or obvious to perform error correction separately in a
`switch fabric or separately in a microprocessor but whether
`it was obvious to perform error correction in the interfaces
`to those components.
` Let's move to slide 23. Slide 23 is a highlighted
`version of figure 2 from the '442 patent. In slide 23, we
`see a data source, 241, highlighted in the purple border up
`in the upper left corner. It's also blown out in more
`detail.
` We also see switch 110 bordered in red in the
`center. And then we finally see data destination 234
`highlighted in yellow in the upper right corner.
` I want to move back to the data source highlighted
`in purple in the upper left corner. It has a purple circle
`parity detector 244 kind of in the center of the box.
` To the right in the switch 110 we see a yellow --
`I'm sorry -- a green parity detector 214. We emphasize that
`these are different. They perform different functions.
` Reschke explains that the purple parity detector
`on the left performs error detection, not correction. I
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`Case IPR2016-01106
`Patent 6,516,442 B1
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`believe that everyone is in agreement that error detection is
`not error correction. Detecting whether an error has
`occurred is different than correcting that error.
` With respect to the green parity detector in
`switch, the one to the right, Reschke explains that this
`parity detector can also perform error correction. The
`patent specification states so.
` Much has been made of the fact that the switch can
`perform error correction. However, we do not believe that
`this makes it obvious to then perform error correction in the
`microprocessor interfaces.
` Let's move to slide 22. This is a complex slide.
`There's a lot of circuitry here. And I'm going to try and
`just focus on little pieces of it. This is figure 4A from
`the -- from the '442 patent. We see in -- I'm going to focus
`on the upper left corner. We see four green micro -- four
`green processors that are going to input data in the switch.
`The switch boundary is highlighted somewhat there in the
`corner in yellow, but, basically, all those registers 413 are
`in the switch. The processors in green and the memory units
`in blue are outside the switch.
` So, we have the -- we have the processors in
`green. And below them are the two memory units -- there
`could be more, but this was depicted here -- that are in
`blue. We see that the blue memory units go out to register
`413E a
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