Page 1 of 20
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`Unified Patents Exhibit 1006
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`U.S. Patent
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`Afig. 17, 1993
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`Sheet 1 of 6
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`5,237,609
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` —
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`t.E_..omm
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`Page 2 of 20
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`Page 2 of 20
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`U.S. Patent
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`Aug. 17, 1993
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`Sheet 2 of 6
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`5,237,609
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`mm_!....!........i!.,w!.IIll_
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`Page 3 of 20
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`Page 3 of 20
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`U.S. Patent
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`Aug. 17,1993
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`Sheet 3 of 5
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`5,237,609
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`-:85
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`5::
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`Page 4 of 20
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`Page 4 of 20
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`U.S. Patent
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`Aug. 17, 1993
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`sheet 4 of 6
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`5,237,609
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`F|G.4
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`50
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`’
`50b
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`500
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`ExTERNAI_
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`IDENTIFICATION
`
`INFORMATION
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`II III
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`IOOO0
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`INTERNAL
`IDENTIFICATION
`INFORMATION
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`OOOOO
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`IX
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`Page 5 of 20
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`STORAGE
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`SECTION
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`Page 5 of 20
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`U.S. Patent
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`Aug. 17, 1993
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`Sheet 5 of 6
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`5,237,609
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`Page 6 of 20
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`Page 6 of 20
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`U.S. Patent
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`Aug. 17, 1993
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`Sheet 6 of 6
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`5,237,609
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`NO
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`300
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`INSERT CARD
`INTO TERMINAL
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`TERMINAL
`POWER "ON"
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`30'
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`302
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`READ ENCIPHERED EXTERNAL
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`INFORMATION FROM
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`NONVOLATILE MEMORY
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`303
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`DETERMINE WHETHER THIS SECIRITY CHECK
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`YES OPERATION IS PERSONAL IDENTIFICATION
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`NUMBER [PIN] KEYIN METHOD OR NOT FROM
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`DECIPHERED TEXT
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`ADD PIN INPUT BY USER TO DECIPHERED
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`DECI PHER STORAGE
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`TEXT AND DECIPHER STORAGE ADDRESSES
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`ADDRESSES AND
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`_AND READOUT SEQUENCE OF CODE ARRAY
`READOUT SEQUENCE
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`OF CODE ARRAY
`IN = 8 BITS x 4 I
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`WRITE CODE ARRAY FROM INTERNAL AREA
`OF NONVOLATI LE MEMORY
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`(OR CODE ARRAY STORING ROMI
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`mo COMPARATOR SUCCESSIVELY
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`3040
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`305
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`304
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`DECIPHER comems or com-: ARRAY
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`[ADDED PIN
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`WRITE DECIPHERED CODE IN COMPARATOR
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`EFFECT COMPARISON BETWEEN CODE ARRAY
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`READ OUT FROM NONVOLATILE MEMORY
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`(OR CODE ARRAY STORING ROMI
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`AND DECIPHERED CODE ARRAY
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`306
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`307
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`308
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`309
`383%
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`ARRAYS
`N0
`MATCH
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`ACCESS
`ALLOWED
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`3; I
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`AccEss
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`REFUSED
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`Page 7 of 20
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`Page 7 of 20
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`select signal line 16, a write enable signal line 17 and an
`output enable signal
`line 18. The address, data, and
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`control lines provide access to the semiconductor mem-
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`ories 4ae:4n in conventional fashion. The card select
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`signal on line 16 is utilized to enable the semiconductor
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`memory elements in a manner which will be described
`below.
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`1
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`PORTABLE SECURE SEMICONDUCI‘OR
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`MEMORY DEVICE
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`FIELD OF THE INVENTION
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`This invention relates to portable semiconductor
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`memory devices, and more particularly to such devices
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`which include a security function intended to protect
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`the information stored in the portable memory.
`BACKGROUND OF THE INVENTION
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`Memory devices such as memory cards can be
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`thought of as divided into two classes--“smart cards”
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`which have_a microprocessor in addition to a main
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`storage unit, and “memory cards” which have only
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`memory but no programmable (or programmed) micro-
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`Because of the processing capability available in
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`smart cars as a result of the on-board microprocessor,
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`cards for protecting the integrity of the data stored on
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`the card. Thus the on-board microprocessor can per-
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`form various functions in checking PIN numbers, hand
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`shaking with a processor in an external terminal, per-
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`forming, enciphering and deciphering operations on-
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`board the smart card, and other techniques all prior to
`allowing access to the main memory on the card. Thus,
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`significant capacity is available for insuring the integrity
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`However, in memory cards which do not have the
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`power of an on-board microprocessor, the capacity for
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`performing security checks before allowing access to
`the main memory is substantially more limited. In a
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`memory card typically the data, address and control
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`lines of the main memory modules are coupled directly
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`to the card outputs and are thus available for read out
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`otherwise. Thus, the opportunity is available for some-
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`one intending to breach the security of the internal
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`memory to directly access the memory device if reason-
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`able care is taken in interfacing the data, address and
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`control lines of the memory elements which are all
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`readily available at the card connection points. Even
`when the card is used in a terminal for which it is in-
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`tended, security functions are usually desirable, such as
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`insertion of a PIN number by a user, or some means of
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`insuring, based on a check of card stored information
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`and terminal supplied processing power that the two are
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`of intended compatability before memory access is al-
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`With only hard wired logic elements at most avail-
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`able on a memory card for performing the security
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`function, insofar as applicant is aware, the techniques
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`which have been made available for securing the stored
`information are not as reliable as could be desired.
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`The security issue will be further developed with
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`reference to FIG. 7 which shows a configuration of a
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`conventional memory card having on-board semicon-
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`ductor memory which is substantially non-secure. The
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`portable semiconductor memory card 1 of FIG. 7
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`carries an on-board semiconductor memory 4, usually
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`comprised of an array of semiconductor memory de-
`vices 40-411. The address lines of the semiconductor
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`memory devices 4ae:4n are coupled together to form
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`an address bus 14, and the data lines coupled together to
`form a data bus 15. The address bus 14 and data bus 15
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`are elements of an interface bus 40 comprising address
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`lines 14, data lines 15, and control lines including a card
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`One further connection is provided from the terminal
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`into which the memory card is inserted, and that is a
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`supply of power which is coupled to power supply line
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`11. A power supply sensing and changeover circuit
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`generally indicated at 2 senses the application of power
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`to the line 11, and couples that applied power to the
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`remaining circuitry for operation. It is noted that to
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`maintain the information in the semiconductor memory
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`4 during the substantial intervals when the card is not
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`inserted in the terminal, a stand-by battery 6 is used to
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`supply power to internal power bus 9 via current limit-
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`ing resistor 7 and a reverse poled charge prevention
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`diode 8. However, whenever the card 1 is plugged into
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`a terminal and a source of power is connected to exter-
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`nal power bus 11, a sensing module 3 within the power
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`supply changeover circuit 2 senses the voltage level on
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`the bus 11 and in response thereto switches on a pass
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`transistor 12 and thereby couples the external power
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`source to the internal power bus 9. In addition, the
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`sensing module 3 within the power supply changeover
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`circuit 2 applies a high logic signal on output line 13
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`which in turn is coupled to a G input of a memory select
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`circuit 5, providing a preliminary enabling signal to the
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`circuit 5. Thus, whenever the power applied to the
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`external bus 11 is higher than that supplied by the bat-
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`tery 6, that condition is sensed by the power supply
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`changeover circuit 2 and the sensing module 3 thereof
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`performs two functions, namely (a) switches on the pass
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`transistor 12 in order to supply external power to the
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`internal bus 9 and (b) couples a high logic enabling
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`signal to the control line 13 providing the preliminary
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`enabling signal to the memory selection circuit 5.
`It is seen that the memory selection signal 5 has a
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`series of outputs S1—S,, which are coupled respectively
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`as enabling inputs 1911-1911 to associated semiconductor
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`memory devices 4a—4n. A selected one of those output
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`lines is individually driven low depending upon the
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`address signal coupled to the address inputs A,. of the
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`selector module 5. Thus, the higher order address bits
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`from the address bus 15, which are coupled to the indi-
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`vidual lines of address input A, are used to select which
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`of the semiconductor memory devices 4ae:4n will be
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`active at any given time. It is noted that the address
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`inputs and G input of selector 5 are provided with
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`pullup resistors 10 to assure that all memory devices
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`4ae:4n are disabled except when the inputs are inten-
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`tionally driven low.
`A final input to the memory select circuit 5 is the G
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`which is coupled to the card select signal line 16 which
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`is an element of the control lines of the interface bus 40.
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`Thus, whenever the particular memory card 1 is se-
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`lected, the external terminal couples a low logic signal
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`to the line 16, and thus provides an enabling signal to
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`the 5 input of selector 5.
`In summary, when power is applied to the external
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`bus 11, the G input of select circuit 5 is driven high.
`Subsequently, when the card select input 16 is driven
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`low, the G input of select circuit 5 is driven low, thus
`enabling the outputs of select circuit 5 to respond to the
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`logic levels on the address inputs. Thus, the external
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`Page 8 of 20
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`

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`3
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`terminal couples address signals to the high order bits
`on the address bus 15 which serve to individually select
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`the outputs S1-S,, of the selector 5 and in turn individu-
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`ally enable the semiconductor memory devices 4-a—4n.
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`When enabled, a semiconductor memory device re-
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`sponds to address signals on the address bus 15, to write
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`or read signals and enable signals on the control lines 17,
`18 to either write information into the addressed semi-
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`conductor memory location from the data bus 15 or
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`read the information stored in the addressed location
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`out onto the data bus 15, both for interfacing with the
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`external terminal.
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`With that understanding of a conventional memory
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`card 1, it will be appreciated that the semiconductor
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`memory 4 is in a relatively non-secure state. The data
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`lines of the semiconductor memory, the address lines of
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`the semiconductor memory and the control
`lines
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`(read/write and enable) of the semiconductor memory
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`are all available at the card output. Typically, such
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`control signals will be directly available at the card
`contacts which are intended to interface with an exter-
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`nal terminal. Even in the case where the card receives a
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`serial message which is stored in a register or the like for
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`coupling to a semiconductor memory,
`there is little
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`security associated with the serial receiver or serial to
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`parallel converter, and thus the terminals of the mem-
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`ory devices themselves can be considered as being
`available to the outside world. While smart cards hav-
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`ing on-board microprocessors can provide the desired
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`security, it has been found impractical to provide an
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`effective amount of security for the on-board memory
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`using only hard wired logic elements.
`It will also be apparent that one can utilize such a
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`semiconductor memory device in a terminal designed to
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`accept it whether or not the individual possessing the
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`card is indeed authorized to use it. There is no security
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`check provided,
`it is simply necessary to couple the
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`appropriate voltage levels or signals to the card, and the
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`individual memory devices are directly addressed for
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`writing or reading as desired.
`Even without a compatible terminal, it is relatively
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`easy to access the contents of the memory 4. It is simply
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`necessary to couple power to the external power bus 11,
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`appropriate control signals, address signals and data
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`signals to the interface bus 40, and the internal memory
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`is directly accessible. Thus, an unauthorized individual,
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`even without access to a compatible terminal, can ac-
`cess the memory and read out information which had
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`been intended to be secure. As a further example, an
`unauthorized individual can write information into the
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`semiconductor memory, and a subsequent user will be
`unaware that the security of the stored information has
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`been breached. If security is at all a factor in using a
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`portable memory device, the limitations of the device
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`illustrated in FIG. 7 will now be apparent.
`SUMMARY OF THE INVENTION
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`In view of the foregoing, it is a general aim of the
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`present invention to provide a portable memory device
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`of inexpensive construction, and requiring no on-board
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`microprocessor unit, but exhibiting a comparatively
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`high degree of security provided in large measure by
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`logic elements resident on board the card.
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`In that regard, it is an object of the present invention
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`to provide a portable memory device in which the on-
`board memory is accessible to the outside only after
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`completion of a security check which matches informa-
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`tion stored in a separate section of memory on the card,
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`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`SO
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`55
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`65
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`5,237,609
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`4
`in which the security information available to the out-
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`side is in enciphered form.
`'
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`Stated differently, an object of the present invention
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`is to provide a portable memory device in which exter-
`nal access is allowed to the on-board semiconductor
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`memory only after a security check, which includes
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`matching an identification code maintained internal to
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`the card with a code deciphered by an external terminal
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`from enciphered information received from the card.
`According to a more detailed aspect of the invention,
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`it is an object to provide a security memory on a porta-
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`ble memory card in which the security memory is parti-
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`tioned in such a way that only enciphered security in-
`formation is available to an interface bus while addi-
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`tional security information which need not be enci-
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`phered is maintained in a partition of memory which is
`accessible only within the card.
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`According to one aspect of the invention, an object is
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`to provide a secure portable semiconductor memory
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`device in which security is provided by utilization of
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`security codes stored in a partitioned on-board security
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`memory, one partition of the memory containing enci-
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`phered security information which is accessible to an
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`interface bus, and the other partition containing security
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`information which need not be enciphered but is avail-
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`able only within the card and is isolated from the inter-
`face bus.
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`In accordance with the invention there is provided a
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`portable semiconductor memory unit for interfacing
`with and exchanging information with an external ter-
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`minal. The unit includes a main memory and an inter-
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`face bus for coupling the main memory to the external
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`terminal. Enabling means selectively allows access to
`the main memory via the interface bus. The enabling
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`means includes a security memory having a first section
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`for storing enciphered external data and a second sec-
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`tion for storing internal data which is isolated from the
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`interface bus. The enabling means further includes a
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`comparator having a first
`input for receiving deci-
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`phered external data from the external terminal which
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`results from deciphering of the enciphered external data
`received from the card via the interface bus. The com-
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`parator has a second input for receiving internal data
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`from the second section of the security memory. Fi-
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`nally, the comparator has an output which causes the
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`enabling means to allow access between the external
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`terminal and the main memory upon detection of a
`match between the internal and external data.
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`It is a feature of the invention that any security infor-
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`mation which is not in enciphered form is isolated from
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`the interface bus so that the only security information
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`available outside the card is enciphered. A further fea-
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`ture of the invention is partitioning of the security mem-
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`ory in such a way as to prevent read out of the section
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`containing the non-enciphered information to the inter-
`face bus.
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`A further feature of the invention is the storage on the
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`card of two independent identification codes, an inter-
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`nal identification code which need not be enciphered
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`but which is isolated from the interface bus so that it is
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`not ascertainable from outside, and an external identifi-
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`cation code which is intended to be accessed by an
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`external
`terminal, but which is enciphered and thus
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`cannot readily reveal the internal identification code. In
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`a preferred embodiment of the invention, it is a further
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`feature that
`the enciphered external
`information in-
`cludes address identification information used to ad-
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`dress locations in the security memory at which the
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`Page 9 of 20
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`Page 9 of 20
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`

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`5,237,609
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`6
`board input/output 205. The main terminal storage
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`section 203 includes a main semiconductor memory
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`which is used for storing a program of instructions for
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`operating the processing unit 201, for storing informa-
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`tion which is to be coupled to the portable memory unit
`100 and for storing information received from the porta-
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`ble memory unit 100. The storage section 203 in effect
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`serves as the main memory for the external terminal
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`200. It can be configured as a single unit or in individual
`blocks, as desired. The main terminal 200 also includes
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`a clock generating circuit 202 which provides clock
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`signals for the CPU 201 and additionally controls the
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`timing of signals which are coupled to the portable
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`memory unit 100 when such unit is connected.
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`The input/output interface 204 is coupled to and
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`therefore drives a CRT display unit 206 for displaying
`information to a user of the external terminal. Similarly,
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`the input/output interface 205 is coupled to a keyboard
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`207 to receive information keyed into the keyboard by
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`such a user. Thus, the terminal unit 200 can be consid-
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`ered relatively conventional as including the major
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`elements familiar to those working in this art. However,
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`the main terminal storage section 203, as will be de-
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`scribed below, also includes a program module capable
`of receiving enciphered external information from the
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`security memory of the portable semiconductor device
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`100, deciphering such information and causing the CPU
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`201 to drive its address, data and control lines in such a
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`way as to cause a security check to be completed in the
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`portable semiconductor unit 100. Such program module
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`principally deciphers the enciphered external informa-
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`tion, writes the deciphered identification information
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`into a comparator in the portable semiconductor mem-
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`ory, and uses address identification information derived
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`from the deciphered information to address a security
`memory in the portable semiconductor memory unit for
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`reading out into the comparator the internal identifica-
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`tion code for comparison with the deciphered external
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`identification code.
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`Directing attention then to the structure of the porta-
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`ble semiconductor device 100, it is seen, like the prior
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`art semiconductor device, to include a main memory 4
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`having an internal power bus 9 supplied with stand-by
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`power from a battery 6 via current limiting resistor 7
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`and charge protection diode 8. The internal power bus
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`9 is connected via power supply changeover circuit 2 to
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`an external power bus 111. As with the prior portable
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`memory device, when the power bus 111 is supplied
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`with power at a voltage higher than that of the internal
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`battery 6, the changeover circuit 2 senses that condi-
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`tion, couples the external power source to the internal
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`bus 9 and couples a high enabling signal to enabling line
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`13 which is coupled in turn to input G] of the memory
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`selection circuit 5a. -
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`The main memory 4 is shown to have an interface bus
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`140, which is illustrated as a single bus in FIG. I, but
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`which includes data lines, address lines and control lines
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`as will be described in greater detail below. Those lines
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`are coupled directly to the main memory 4, but in prac-
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`ticing the invention are not allowed to directly access
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`the main memory until after successful completion of a
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`security check routine which is controlled by informa-
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`tion in the portable device 100, at least some of which is
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`inaccessible to the interface bus and therefore practi-
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`cally inaccessible outside the card.
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`In practicing the security aspects of the invention, a
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`security memory 50, preferably a non-volatile memory,
`is provided for storing security related information. A
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`5
`internal identification code is stored, so that the value
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`and sequence of the identification codes provide a fur-
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`ther measure of security for the portable semiconductor
`memory.
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`As a further feature of the invention, a PIN identifica-
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`tion number input by a user into an external terminal
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`can be combined with the external security information
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`in order to provide further security and further limit
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`access to only those who are in possession of the PIN
`number.
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`Other objects and advantages will become apparent
`upon references to the following detailed description
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`when taken in conjunction with the drawings in which:
`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a block diagram showing a secure memory
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`system including an external terminal unit coupled via
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`an interface bus to a portable memory device;
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`FIG. 2 is a block diagram illustrating additional de-
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`tails of the security aspects of the portable memory
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`device of FIG. 1;
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`FIG. 3 is a block diagram illustrating additional de-
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`tails of a comparator circuit useful in connection with
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`the embodiments of the present invention;
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`FIG. 4 is a diagram illustrating memory partitioning
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`for the security memory of the system of FIG. 1;
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`FIG. 5 is a block diagram illustrating a second exem-
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`plary portable memory device exemplifying the present
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`invention;
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`FIG. 6 is a flowchart illustrating the operation of the
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`secure memory system according to the present inven-
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`tion; and
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`FIG. 7 is a block diagram illustrating a memory card
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`exemplifying the prior art.
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`While the invention will be described in connection
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`with certain preferred embodiments, there is no intent
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`to limit it to those embodiments. On the contrary, the
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`intent
`is to cover all alternatives, modifications and
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`equivalents included within the spirit and scope of the
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`invention as defined by the appended claims.
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`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENTS
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`Turning now to the drawings, FIG. 1 shows a porta-
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`ble memory card 100 exemplifying the present inven-
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`tion and interfaced to an external terminal 200. The
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`electrical connection between the devices is schemati-
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`cally illustrated by connector 150. In practice, the exter-
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`nal terminal will preferably include a slot or other close
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`fitting receptacle into which the memory device 100 is
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`inserted and which will cause mating of electrical
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`contacts between the portable card 100 and the external
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`terminal 200, such mating being illustrated by the afore-
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`mentioned connector 150. As illustrated in FIG. 1, the
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`connections include those made to an interface bus 140
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`as well as a power bus 111. It is seen that the external
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`terminal includes a similar power bus 211 and interface
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`bus 240 coupled to the connector 150, such that the
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`terminal unit 200 supplies DC power to the portable
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`card 100. In addition, the coupling of busses 140, 240
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`causes the connection of data lines, address lines and
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`control lines between the portable memory card 100
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`and the external terminal 200.
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`The external terminal will be not described in great
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`detail as its structure can be relatively conventional. It is
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`shown to include a central processing unit 201 coupled
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`by means of an internal bus 210 to a main terminal stor-
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`age section 203, a display input/output 204 and a key-
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`10
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`45
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`50
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`65
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`Page 10 of 20
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`Page 10 of 20
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`7
`security control circuit 51 is coupled to the interface bus
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`140 and performs the function of controlling access to
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`the security memory 50, receiving security related in-
`formation which originated from the security memory
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`50, and performing a security comparison of internal
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`and external security information before allowing ac-
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`cess between the interface bus 140 and the main mem-
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`ory 4. In FIG. 1, the interface bus 140 is shown inter-
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`connecting the security control circuit 51 and security
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`memory 50, illustrating that the external terminal has
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`the ability for limited access to the security memory in
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`performance of the security check. Also shown con-
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`necting those modules is an internal bus 152 which is
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`provided only between the security memory 50 and
`security control circuit 51. Such bus, as will be de-
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`scribed in greater detail below, provides a means for
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`readout of security information which is not necessarily
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`enciphered for coupling to the security control circuit
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`in performance of the security check. The fact that the
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`bus 152 is internal only and not coupled to the main
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`interface bus 140 provides a significant degree of secu-
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`rity when it is appreciated t