`B. BRIEF RESUME
`
`1. Education
`
`
`
`2. Professional Experience
`
`
`• Doctor of Philosophy, Electrical and Electronic Engineering 1989, University of
`Adelaide, Australia . Advisor: Kamran Eshraghian.
`• Bachelor of Engineering with First Class Honours, Electrical and Electronic En-
`gineering: 1984, University of Adelaide, Australia
`• Bachelor of Science, Physics and Mathematics: 1983, University of Adelaide,
`Australia.
`
`PAUL D. FRANZON
`
`• Assistant Professor, Associate Professor, Professor, and Distinguished Professor
`North Carolina State University, Department of Electrical and Computer
`Engineering, Raleigh, North Carolina, January 1989 – present
`• Technical Director, Rambus (part time/consulting), 2009-11, Chapel Hill, NC.
`• Cofounder, LightSpin Technologies Inc., 2001-. Vice-President of Engineering,
`2001-2002, Raleigh NC.
`• PhD Candidate, University of Adelaide, Department of Electrical and Electronic
` Engineering, Adelaide, South Australia, Australia, April 1987 - December 1988.
`• Director and Co-Founder, Network Communications Pty. Ltd., Adelaide, South
`Australia, Australia, April 1987 - April 1989.
`• Consultant, AT&T Bell Laboratories, Holmdel NJ, January 1986 - April 1987.
`• PhD Candidate, University of Adelaide, Department of Electrical and Electronic
`Engineering, Adelaide, South Australia, Australia, August 1984-December 1985.
`• Engineer, Defence Science and Technology Organization, Salisbury, South Aus-
` tralia, Australia, January 1984--July 1984
`Intern, Defense Science and Technology Organization, Salisbury, South Austra-
`•
`lia, Australia, December 1982--March 1983.
`Intern, Telecom Australia, Adelaide, South Australia, Australia, December 1981-
`•
` March 1982.
`Infantry Soldier and Officer, (Ranks held: Private - Captain), Royal Australian
`•
` Infantry Corps, Australian Army Reserve, December 1979 - December 1991.
`
`
`3. Scholarly and Creative activities
`
`Number
`
`
`
`Type
`
`-------------------------------------------------------
`Books
`
`
`
`3
`Solution Manuals
`
`
`1
`Edited Book chapter
`
`
`15
`Refereed Journal article
`
`88
`
`Page 1 of 60
`
`Unified Patents Exhibit 1010
`
`

`

`Paul D. Franzon
`
`220
`10
`
`Conference Paper (refereed)
`Patents granted
`
`
`
`4. Membership in professional organizations
`
`Fellow, Institute of Electrical and Electronic Engineers, 1984-
`Member, IMAPS
`Member, SPIE
`Member, Association of Computing Machinery
`
`5. Scholarly and professional honors
`
`
`• NCSU Innovator of the Year Award, 2015
`• College of Engineering Board of Governor’s Award, 2014
`• NRL Alan Berman Research Publication Award, 2008
`• Babbage Award, Synopsys, 2008
`• Fellow of the IEEE, 2006
`• Alcoa Research Award, 2005
`• ECE Graduate Teacher of the year award, 2007
`• ECE Most Helpful Teacher of the year award, 2007
`• ECE Teacher of the year award, 2006
`• ECE Graduate Advisor of the year award, 2006
`• Alumni Undergraduate Distinguished Professor, 2003-2005.
`• Graduate teacher of the year, ECE department, 2005
`• NSW Australia Expatriate Scientist Award, 2003
`• Selected to the NCSU Academy of Outstanding Teachers, 2001
`• First round prize winner, SRC copper challenge, 2000.
`• Teacher of the Year Award, presented by the IEEE Student Branch, 1997
`• National Science Foundation Young Investigator's Award, 1993.
`• 13 prizes while a student at the University of Adelaide
`
`
`6. Professional service on campus
`
`
`• Member, STRAG 2003-2005
`Instructor, PE preparation course 1995-2000
`•
`
`
`7. Professional service off campus
`• Consultant to DARPA, Thermal issues, 2012-14
`• Consultant to Paul Hastings, OMM, KL Gates, Samsung, Micron and SK Hynix,
`2015-, Patent issues including IPR, (District of Delaware, CA N. 14-cv-01432-
`LPS-CJB and related cases)
`• Consultant to LDKM and AVT, Patent issues, 2013- (New York Southern District,
`1:11-cv-06604-CM, with 08908 and 00918)
`• Consultant to Skiermont Puckett and Spherix, Patent issues including IPR, 2014-
`2015, (Texas Northern District, 3:13-cv-3494-M and 3496)
`
`
`
`2
`
`Page 2 of 60
`
`

`

`Paul D. Franzon
`
`• Consultant to Haliburton, 2014
`• Consultant to DARPA, Exascale Computing Study, 2006-9.
`• Consultant to Rambus, Semiconductors, 2009-12
`• Consultant to Techsearch, 2008.
`• Consultant, NTU, 2004-9. ASIC Design.
`• Consultant to Tessera, 2009. 3DIC advising.
`• Consultant, Irvine Sensors, 2006. Secure chip design.
`• Consultant, Cisco Systems, 2006, Signal Integrity.
`• Consultant, Talon Logic, 2005. Secure system Design.
`• Consultant to O'Malveny and Meyers, 2000-2002, Patent issues.
`• Consultant to Venture 2000, 2000, Due Diligance.
`• Consultant to CAPPS, 1999-2000, IP Development.
`• Consultant to Sofrent, 1999-2000, IP Development.
`• Consultant to Ericsson, 1997, Synthesis Methodology.
`• Consultant to Cadence, 1996. Evaluated possible company acquisition.
`• Consultant to Polychip, 1994 - 2000. Circuit Design.
`• Consultant to Square-D, 1996. Interconnect Design.
`• Consultant to Mentor Graphics, 1995, 1996. Technical advisory board.
`• Consultant to Cadence Design Systems, 1992, 1996. Technical advisory board.
`• Consultant to DCT, 1995-1996. ASIC Design.
`• Consultant to Techsearch International, 1989-1991. Report Preparation.
`• Consultant to BNR, HP, Sun. 1992-4. Interconnect Design.
`• Consultant to MCNC, 1989. CAD
`
`
`
`II. TEACHING AND MENTORING OF UNDERGRADUATE AND
`GRADUATE STUDENTS
`
`A. TEACHING EFFECTIVENESS
`
`1. Courses Taught
`
`Course
`
`When
`
`Enrollment
`
`ECE 464-001
`ECE 520-001
`ECE 520-601
`ECE 520-603
`ECE 520-651
`ECE 733-001
`ECE 464-002
`ECE 520-002
`ECE 520-601
`ECE 634-602 ASIC Design
`
`S 15
`S 15
`S 15
`S 15
`SuI 15
`S 15
`F 15
`F 15
`F 15
`F 2014
`
`19
`119
`11
`3
`16
`50
`21
`129
`7
`2
`
`
`
`3
`
`Instructor
`effectiveness
`4.3
`4.3
`4.8
`
`4.6
`4.5
`4.6
`4.6
`5.0
`
`
`Course
`excellence
`4.3
`4.3
`5.0
`
`4.6
`4.3
`4.5
`4.5
`5.0
`
`
`Page 3 of 60
`
`

`

`ECE 520-601
`ECE 464-001
`ECE 520-001
`ECE 520-601
`ECE 733-001
`ECE 520-601
`ECE 520-651 ASIC Design
`ECE 464-051 ASIC Design
`ASIC Design OOC
`ECE 733 Digital Electronics
`ECE 520-001 ASIC Design
`ECE 464 ASIC Design
`
`ECE 520-651 ASIC Design
`
`ECE 733 Digital Electronics
`ECE 520-601
`ECE 520-001 ASIC Design
`ECE 464 ASIC Design
`ECE 406 Des. Complex
`Systems
`ECE 520-651 ASIC Design
`
`ECE 733 Digital Electronics
`ECE 520-601
`ECE 520-001 ASIC Design
`ECE 464 ASIC Design
`ECE 406 Des Complex
`Systems
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 520 ASIC Design 620
`ECE 464 ASIC Design
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`
`S1 2014
`S 2014
`S 2014
`S 2014
`S 2014
`F 2013
`SII ‘13
`SII ‘13
`SII ‘13
`S 2013
`S 2013
`S 2013
`
`Sum
`‘12
`S 2012
`S 2012
`S 2012
`S 2012
`F 2011
`
`Sum
`‘11
`S 2011
`S 2011
`S 2011
`S 2011
`F 2010
`
`S 2010
`S 2010
`S 2010
`S 2010
`S 2010
`S 2009
`S 2009
`S 2009
`S 2009
`S 2009
`S 2009
`S 2008
`S 2008
`S 2008
`S 2008
`S 2008
`
`9
`10
`111
`9
`49
`2
`7
`6
`635
`62
`136
`(with
`above)
`18
`
`52
`12
`116
`14
`58
`
`13
`
`18
`12
`75
`25
`75
`
`36
`3
`57
`17
`9
`57
`7
`128
`17
`1
`16
`67
`2
`101
`15
`27
`
`
`
`4
`
`Paul D. Franzon
`
`
`4.5
`4.5
`4.5
`4.4
`
`4.3
`4.5
`
`4.3
`4.5
`4.3
`
`
`
`4.2
`4.2
`4.3
`4.3
`4.6
`
`4.2
`
`4.5
`4.2
`4.5
`4.5
`4.6
`
`4.2
`5.0
`4.4
`4.4
`4.4
`4.5
`4.2
`4.4
`4.20
`
`4.4
`4.64
`
`4.59
`4.20
`4.59
`
`
`4.5
`4.5
`4.5
`4.7
`
`4.3
`4.5
`
`4.5
`4.6
`4.3
`
`
`
`4.2
`4.3
`4.3
`4.3
`4.6
`
`4.2
`
`4.5
`4.3
`4.5
`4.5
`4.6
`
`4.3
`5.0
`4.3
`4.2
`4.3
`4.6
`4.4
`4.6
`4.5
`
`4.6
`4.64
`
`4.76
`4.5
`4.76
`
`Page 4 of 60
`
`

`

`58
`129
`6
`17
`20
`43
`65
`8
`17
`30
`5
`44
`34
`2
`15
`13
`45
`76
`17
`69
`84
`81
`30
`63
`167
`239
`
`39
`
`ECE 733
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 745 ASIC Verification
`ECE 733 Digital Circuits 001
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design 001
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 002
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design 001
`ECE 464 ASIC Design 002
`ECE 733 Digital circuits
`ECE 520 ASIC Design
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 733 Digital Circuits
`ECE 520 ASIC Design
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 406 Design Complex DS
`ECE 520 ASIC Design
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 406 Des. Complex Dig
`Sys
`ECE 704 Design For Test
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 002
`ECE 520 ASIC Design 601
`ECE 492B ASIC Design
`ECE 342 Des. Complex Dig
`Sys
`ECE 520 ASIC Design 005
`ECE 520 ASIC Design 006
`ECE 342 Des. Complex Dig
`Sys
`ECE 520 ASIC Design
`ECE 492B ASIC Design
`ECE 342 Des. Complex Dig
`Sys
`
`S 2007
`S 2007
`S 2007
`S 2007
`F 2006
`S 2006
`S 2006
`S 2006
`S 2006
`S 2005
`S 2005
`S 2005
`S 2005
`S 2005
`S 2005
`S 2005
`S 2004
`S 2004
`S 2004
`S 2004
`S 2003
`S 2003
`S 2003
`S 2003
`F 2002
`S 2002
`S 2002
`S 2002
`F 2000
`
`F 2000
`S 2000
`S 2000
`S 2000
`S 2000
`F 1999
`
`S 1999
`S 1999
`F 1998
`
`S 1998
`S 1998
`F 1997
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5
`
`Paul D. Franzon
`
`
`
`
`
`4.46
`4.68
`
`4.68
`4.6
`4.6
`
`
`4.1
`4.6
`
`4.3
`4.5
`
`4.1
`4.1
`4.2 (3.9)
`4.3 (3.9)
`
`4.0 (3.9)
`4.2 (3.8)
`3.9 (3.8)
`
`3.5 (3.8)
`3.8 (3.9)
`4.2 (3.9)
`
`3.6 (3.9)
`4.5 (3.7)
`
`4 (3.8)
`4.4 (3.9)
`4.3 (3.9)
`
`4.3 (3.9)
`4 (3.9)
`
`4.5 (4.0)
`4.3 (4.0)
`4.1 (3.9)
`
`4.4 (3.9)
`4.8 (4.1)
`4.4 (4.0)
`
`
`
`
`
`4.64
`4.75
`
`4.75
`
`4.5
`
`
`4.4
`4.5
`
`4.6
`4.6
`
`4.9
`4.9
`4.2 (4.1)
`4.4 (4.1)
`
`4.5 (4.1)
`4.3 (4.0)
`4.2 (4.0)
`
`3.9 (4.0)
`4.2 (4.1)
`4.4 (4.1)
`
`4.1 (4.1)
`4.7 (4.0)
`
`4.6 (4.0)
`4.5 (4.1)
`4.6 (4.1)
`
`4.5 (4.1)
`4.4 (4.1)
`
`4.6 (4.2)
`4.5 (4.2)
`4.3 (4.1)
`
`4.6 (4.1)
`4.7 (4.1)
`4.6 (4.0)
`
`Page 5 of 60
`
`

`

`ECE 520 ASIC Design
`ECE 492B ASIC Design
`AVERAGE
`
`S 1997
`S 1997
`
`
`
`
`
`
`4.7 (4.1)
`4.7 (4.1)
`
`
`4.7 (3.9)
`4.4 (3.9)
`
`
`Paul D. Franzon
`
` •
`
` ECE 342 Design of Complex Digital Systems, Fall 1996, Overall Rating: 4.6/5.0.
`• ECE 592B ASIC Design, Spring 1996, Overall Rating: 4.75/5.0. (With Dr. Liu.)
`• ECE 492B ASIC Design, Spring 1996, Overall Rating: 4.00/5.0. (With Dr. Liu.)
`• ECE 544, Design of Electronic Packaging and Interconnects, Spring 1999, Overall
`Rating : 4.60/5.0.
`• ECE 520, Fundamentals of Logic Systems, Fall 1995, Overall Rating: 4.50/5.0.
`• ECE 218, Computer Organization and Microprocessors, Both Sections, Spring,
`1995: Section 001: 4.45/5.0; Section 002: 4.62/5.0.
`• ECE 592V, VLSI Microprocessor Project, Spring 1995. (13 students but not rated).
`• ECE 681/693A, Computer Engineering Seminar. Spring 1996 and Fall 1996.
`• ECE 521 Computer Design and Technology, Fall 1994, Overall Rating: 4.24/5.0.
`• ECE 691F, High Speed VLSI, Fall 1994, Overall Rating: 4.45/5.0.
`• ECE 691P, Superscalar Processor Design, Spring 1994, Overall Rating: 4.67/5.0.
`• ECE 591F, Design of Electronic Packaging and Interconnects, Spring 1994, Overall
`Rating: 4.60/5.0.
`
`
`
`B. INSTRUCTIONAL DEVELOPMENT
`
`
`
`1. NSF-funded CISE Infrastructure effort, “Experimental High Performance
`Computing and Communications Systems''. (Total: $1,338,283 including $503,046 in
`matching.) Approximately $283,000 of this funding went towards outfitting the ECE
`Design Center.
`
`2. CAD Tools. Modern design is done with sosphisticated Computer – Aided Design
`Tools, not with pencil and paper. I have spent considerable effort bringing such tools
`into the Unity environment, gaining the `corporate knowledge' about how to use these
`tools effectively and obtaining additional computers for use with these tools. Students tell
`me that knowledge of these tools is highly regarded by potential employers. In fact one
`student stated that `Dr. Franzon teaches courses that gets jobs'. In addition , in 1999, we
`won the Cadence University Alliance Best Web site Awards. Through my funded
`research efforts and Corporate Donations introduced the following Computer Aided
`Design Tools into the curricula:
`• Cadence Design Systems. A complete suite of over 4 GB of executables
`that facilitate chip, board and system design, with a retail value of over
`$100,000,000. Cadence donates these tools because of the widespread
`recognition of our contributions to CAD. (i.e. It waives the $5,000 fee.)
`• Synopsys. The industry leading chip (ASIC) synthesis tool,with a retail
`value of over $7,000,000.
`
`
`
`6
`
`Page 6 of 60
`
`

`

`Paul D. Franzon
`
`•
`
`•
`
`In 2008, NCSU won the “Babbage Award” from Sun and Synopsys, in
`recognition of our contributions towards lab infrastructure. The award comes
`in the form of $15,000 of computers.
`• Mentor. We integrate some mentor graphics tools with the other tools above.
`The tools have a retail value of over $5,000,000. Mentor donates these tools
`because of the widespread recognition of our contributions to CAD.
` Mentor donates $30,000 annually to the University to assist in CAD
`infrastructure development.
`As well as obtaining these tools, my group has spent considerable effort making these tools
`useful to us by writing integration scripts and generating `know-how'. Much of this `know-
`how' has been published on the Web and in our own lockers. Most of this learning was
`conducted driven by research needs and serves as an excellent example of the integration
`of research and teaching. This work is ongoing. For example, over 2000 organizations
`world-wide, use our “Physical Design Kit”..
`
`3. ECE 745. ASIC Verification. I introduced this course in 2007, though it was taught by
`Meeta Yadav.
`
` 4. ECE 342, Design of Complex Digital System, Fall 1996:
`• Completely redesigned and updated course to reflect modern design practices,
`and use of modern Hardware Description Languages and Design Tools.
`• Completed a new laboratory course ECE 342L for use with this course.
`
` 5. ECE 520 ASIC Design (formerly `Fundamentals of Logic Systems'), Spring 1997:
`• Based on my teaching of ECE592B in Spring 1995, this course has been
`completely updated to reflect modern design practices, modern tools, and
`emphasize an understanding of algorithms used in modern tools. (`ASIC' stands
`for `Application Specific Integrated Circuit'. For example the chips in a satellite
`dish receiver are ASICs. ASIC engineering is the fastest growing area of ECE
`today.)
`• Once the course action forms are approved, this course will be taught concurr-
`ently with ECE 420 ASIC Design.
`
`
`
`
`
`
`
`6. ECE 544, Design of Electronic Packaging and Interconnects, Spring 1995. New c-
`ourse emphasizing `transmission line effects' in electronic packages and how to design
``deep sub-micron interconnect'. I receive tremendous demand from ind-
` ustry
`for graduates from this course.
`
`7. ECE 691/693A, Computer Engineering Graduate Seminar
`• Created new seminar course (with Dr. Tom Conte) for computer engineering
`students.
`• Recruited and scheduled weekly speakers.
`
`
`8. ECE CAD Lab. $75,000. Provost Office, 1995.
`
`C. MENTORING ACTIVITIES
`
`
`
`7
`
`Page 7 of 60
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`

`

`Paul D. Franzon
`
`
`UNDERGRADUATE STUDENT SUPERVISION
`1. 2012. Spring advisor to two undergraduates.
`2. 2010. Summer REU supervisor to three Undergraduates
`3. 2009. Summer REU supervisor to one Undergraduate.
`4. 2009. Supervised Senior Design Team
`5. 2008. Summer REU supervisor to two Undergraduates.
`6. 2005 Andrew Pita, SRC Undergraduate Research Fellowship
`7. 1999 Ecoh Oh, NSF Undergraduate Research Award
`8. 1999 Ben Hughes, NSF Undergraduate Research Award
`9. 1993- Numerous Senior Design projects
`
`
`GRADUATE STUDENT SUPERVISION
`
`GRADUATE COMMITTEES
`
`Currently member of several PhD and MS committees.
`
`GRADUATE COMMITTEES
`
`For a list of graduate committees I chair, see below. I am on numerous committees as a
`member, but I do not track the numbers.
`
`
`
`D. MASTER’S AND DOCTORAL THESES DIRECTED AND BEING
`DIRECTED
`
` I
`
` am actively directing the theses of 20 Ph.D. students and 3 Master with thesis option
`(MST) students. I have graduated 50 Ph.D. students and 50 MST students.
`
`Masters and Doctoral Theses under direction
`
`
`Student Name
`
`Degree [date]
`
`Weiyi Qui
`Josh Schabel
`Weifu Li
`Sumon Dey
`David Winick
`Gary Charles
`Marcus Tshibangu
`Randy Widialaksono
`Zenquian Zhang
`Wenxu Zhao
`Jong Beom Park
`
`PhD [12/16]
`PhD [12/16]
`PhD [12/16]
`PhD [12/16]
`PhD [12/15]
`PhD [03/15]
`PhD [12/16]
`PhD [05/16]
`PhD [12/16]
`PhD [05/16]
`PhD [08/16]
`
`
`
`8
`
`Page 8 of 60
`
`

`

`Paul D. Franzon
`
`Luther Blackwood
`Lee Baker
`Zhao Zhang
`Kirti Bhanushali
`
`MS to PhD [12/16]
`PhD [12/16]
`PhD [07/17]
`PhD [12/16]
`
`Interconnect Design
`
`
`Doctoral Theses Directed
`
`1. Sarkar, Biplap, “Atomic Layer Deposition Techniques for Novel Memory
`Applications,” August 2015. Cochair
`2. Winick, David, “Electroactive Polymer Refreshable Braille Display, December
`2015 (Posthumous).
`3. Gary Charles, “Design, Model and Analysis of TSV-based On-Chip PDN Interconnects
`for 3-D Integrated Circuits. “, March 2015.
`4. Zhao Yan, “S-Parameter Based Binary Multimode
`Methodology and Implementation,” December, 2014 .
`5. W.S. Pitts, “High quality CMOS Integratable Varactors,” March 2014.
`6. Peter Gadfort, “Packaging and Integration of Three Dimensional Microsensors,”
`December, 2013.
`7. Evan Erickson, “Multi-Gbps Inductively Coupled Connectors,” December, 2013.
`8. Akalu Lentiro, “Low-Density, Ultra-Low Power and Smart Radio Frequency
`Telemetry Sensor,” October, 2013.
`9. Shivam Priyadarshi, “System and Gate Level Dynamic Electrothermal Simulation
`of Three Dimensional Integrated Circuits,” June, 2013.
`10. Eric Wyers, “Direct Search Calibration Algorithms for Digitally Reconfigurable
`Radio Frequency Integrated Circuits,” March 2013.
`11. Ojas Ashok BOpat, “A Generic Scalable Architecture For a Large Acoustic Model
`and Large Vocabularly Speech Recognition Accelerator,” October, 2012.
`12. Won Hao Choi, “System Level Power Prediction Methodology for Mobile 3-D
`Graphic Engines,” May 2012.
`13. Hsuan-Jung Su, “Continuous-Time Fractionally Spaced Equalization and Its
`Application in Capacitively Coupled Chip-To-Chip Interconnect,” May, 2012.
`14. Hsuan-Jung Su, “Continuous-Time Fractionally Spaced Equalizatoin and its
`Application to Capactively Coupled Chip-TO-Chip Interconnect”, January 2012.
`15. Matthew Hamlett, “A Novel Approach to IP Protection Using Automated Hardware
`Techniques to Secure a Design,” March 2012.
`16. Mustafa Berke Yelten, “Variability and Reliability in Nanoscale Circuits:
`Simulation, Desgin, Monitoring and Characterization,” January, 2012.
`17. Hoon Seok Kim, “Advanced Multi Mode Interconnect,” December, 2011.
`18. Xiangzhong Xue, “Electronic System Optimization Via Convex Programming,”
`December, 2011.
`19. Zhu, A Surrogae Model-based Framework for Design and Macromodeling of Self-
`calibrated Analog Circuits,” October, 2011.
`20. Chanyoun Won, “Multimode Interconnect for High-Density Links: Implementation,
`Design Methodology and New Crosstalk Cencallation Scheme,” July 2011
`21. Thor Thorolfsson, “Three Dimensional Integration of Synthetic Aperture Radar
`Processors,” April 2011
`
`
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`Paul D. Franzon
`
`22. Daniel Schinke, “Computing with Novel Floating Gate Devices,” April 2011
`23. Yongjin Choi, “Design of Multimodel Signaling Transceiver for High-Density and
`High-Speed Links,” May 2010.
`24. Eun Chu Julie Oh, Ph.D. Dissertation, “Design and Applications of Three-
`Dimensional Circuits”, December, 2009.
`25. Karthik Chandrashekhar, Ph.D. Dissertation, “Inductively Coupled Connectors,”
`December, 2008
`26. Dhruba Chandra, Ph.D. Dissertation, Speech Recognition CoProccessor, December,
`2007.
`27. Meeta Yadav, “Hardware Architecture of behavior Modeling Coprocessor for
`Network Intrusion Detection,” Ph.D. Dissertation, March, 2007.
`28. Ullas Pazhayaveetil, “Hardware Implementation of a Low Power Speech
`Recognition System,” Ph.D. Dissertation, February, 2007.
`29. Jian Xu, “AC Coupled Interconnect for Inter-Chip Communications,” Ph.D.
`Dissertation, December, 2006.
`30. Ambrish Varma, “Improved behavioral modeling based on Input Output Buffer
`Information Specification,” Ph.D. Dissertation, NCSU, October, 2006.
`31. Sachin Sonkusale, “Planar edge defined alternate layer process (PEDAL) – an
`unconventional technique for the fabrication of wafer scale sub-25 nm nanowires
`and nanowire template,” PhD, October, 2006.
`32. Liang Zhang, “Driver Pre-emphasis Signaling for on-chip global interconnects,”
`Ph.D. Dissertation, September, 2006.
`33. Monther Al Dwairi, “Hardware Efficient Pattern Matching Algorithms and
`Architectures for Fast Intrusion Detection,” Ph.D., November, 2006.
`34. John Damiano, “Active body bias for low-power silicon-on-insulator design,”
`Ph.D., March 2006.
`35. Neil DiSpigna, “Electronic Devices and Interface Strategies for Nanotechnology,”
`Ph.D., April 2006.
`36. Christian Amsinck, “Molecular Electronic Memories,” Ph.D., March 2006.
`37. Lei Luo, “Capacitively Coupled Chip to Chip Interconnect Design, Ph.D.,
`December, 2005.
`38. Leon Zhang, “Driver pre-emphasis signaling for on-chip global interconnects,”
`Ph.D., December, 2005.
`39. Steve Lipa, “Phase Noise Analysis of Rotary Oscillators,” Ph.D. May 24, 2005
`40. David Nackashi, Circuit and Integration Technologies for Molecular Electronics,
`Ph.D. 2004
`41. Stephen Mick, AC Coupled Interconnect, Ph.D. 200
`42. John Wilson, Linearly Tunable RF MEMS Capacitors Implemented Using an
`Integrated Removable Self-Masking Technique, Ph.D. 2004
`43. Andrew Stanaski, Sensor Circuits for Flip Chip Debug, Ph.D. 2004
`44. Pronita Mehrotra, High Performance Hardware Memory Algorithms, Ph.D. 2003
`45. Bruce Duewer, MEMS Switch Fabric, Ph.D.
`46. Toby Schaffer, Chip-package Codesign, Ph.D.
`47. Mouna Nakkar, Dynamically Programmable Cache, Ph.D.
`48. Mir Azam, Custom CMOS Design and Architecture for Low-Power High-
`Performance Circuits, PhD.
`
`
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`Paul D. Franzon
`
`49. Debu Ghosh (co-chair), Synthesis of Benchmarking Expiriments, Ph.D.
`50. Chris Harvatis, Performance Driven Partitioning for MCMs, PhD.
`51. Slobodan Simovich, Computer-Aided Analysis of Interconnect,PhD.
`52. Scott Washabaugh, Low energy FSM Design, PhD.
`53. Sharad Mehrotra, Automated Synthesis of High Speed Digital Circuits and Package-
`Level Interconnect, PhD.
`54. Todd Cook, Instruction Set Architecture Specification, PhD.
`55. Robert Evans, Energy Consumption for Modeling and Optimization of SRAMs,
`PhD.
`
`Masters Theses directed
`
`1. Abhishek Bhattacharya, “Design and Power Optimization of a16 nm Dual Floating
`Gate FET Memory Array and Peripheral Circuits,” Octover, 2013.
`2. Joshua Schabel, “An Analysis of Subthreshold SRAM Bitcells for Operation in Low
`Power RF only Technologies,” July 2013.
`3. Vinod Kotipllai, “Impact of Process Variations on 16-nm Dual Floating Gate FET
`using TCAD simulations,” December 2012.
`4. Wenxu Zhao, “Headphone Deiver Design with Inductive Coupled Interconnection,”
`November, 2012.
`5. Shiney Gupta, “Multi-Storey Stacked Driver Topolo9gy for Reduced Swing and
`Low Power Bus Operation,”, May 2012.
`6. Pattabhiraman Ravindran, “Harvesting Thermal Energy to Power Agricultural
`Sensors,” October, 2011.
`7. Alex Leaonard, “Implementation of a System-on-Chip for self-healing of analog
`receiver components in a 65 nm CMOS process”, May 2011
`8. Seema Kumar, “Memory Diesgn for Sensor IC,” May 2010.
`9. Mihir Shiveshwarkar, “A Nanocrystal Floating Gate Flash Analog to Digital
`Converter,” December, 2009.
`10. Ojas Bapat. “Design of DDR2 Interface for Tezzaron TSC8200A Octupus Memory
`intended for Chip Stacking Applications,” April 2009.
`11. Peter Gadfort, “Low power driver for silicon carrier interconnects,” April 2009.
`Interconnect
`for Chip
`to Chip
`12. Chintan Shah, “Inductively Coupled
`Commmunication over Transmission Line,” Feb 2009.
`13. Kiran Gonsalves, “Memory Design for FFT Processor in 3DIC Technology,”
`March, 2009.
`14. Vinay Honnavara, “Cost optimization by method of allocating software component
`units to electronic control units for model-driven designs,” October, 2008.
`15. Wei Cao, “Design of temperature sensors for validation of aseptic food processing,”
`Sept. 2008.
`16. Akalu Lentiro, “Implemention of AC Coupled Interconnect Test Vehicle,” May,
`2008.
`17. Vinayak Devasthali, “Application of body biasing and supply voltage scaling
`techniques for leakage reduction and performance improvement of CMOS Circuits,”
`December 2007.
`
`
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`Paul D. Franzon
`
`18. Paul Fernando, “Adding scalability to IBIS using AMS Languages,” September
`2007.
`19. Vivek Jayadav, “Hardware-Software Codesign of a Large Vocabularly Speech
`Recognition System,” February, 2007.
`20. Srivatsan Parthasarathy, “Interfacing AC Coupled Interconnect Design with Rocket
`I/O compatible FPGA Systems,” December 2006.
`21. Janani Mukundan, “Instruction Cache Checkpoints Using Phase Tracking and
`Prediction,” June 2006.
`22. Yasaswini Sudarsanam, “Implementatin of Double Precision Floating Point
`Arithmetic for Matrix Multiplication,” October 2006
`23. Itisha Tyagi, “Design of array based row decoders and self-referencing sense
`amplifier for large scale resistance change style molecular memories,” June 2006.
`24. Indraneel Kelkar, “Tradeoffs involved in the design of SRAMs,” December 2005.
`25. Wallace Pitts, “Partially depleted silicon on insulator phase lock loop design,”
`January, 2006.
`26. Janani Mukundan, “Instruction cache checkpoints using phase tracking and
`prediction,” December 2006.
`27. Deepak Kumar, ”Design of fully integrated wireless CMOS MEMS device for
`intraocular pressure measurement,” March 2006.
`28. Manav Shah, “Design of a self-test vehicle for AC Coupled Interconnect
`Technology,” May 2006.
`29. Andrew Morgan, Design Flow based on Sensitivity Analysis for High Speed Digital
`Circuits, MS, 2004
`30. Brian Phelp, Hardware Realization and Implementation Issues for the Sliding
`Window Packet Switch, MS, 2004
`31. Ishdeep Sawhney, Hardware Forwarding for IPV6, MS, 2003
`32. Kaustabh Bhate, MEMS Design for textiles sensor, MS
`33. Praveen Prasad, Reconfigurable Computing for Network Security, MS
`34. Patrick Lall, Verification of a Network Processor, MS
`35. Ambrish Varma, SHOCC Design Tools, MS
`36. Karthik Chandrasekhar, Hardware to support multicast in all-optical networks, M
`37. V. Parameshawara (co-chair), Enhancement of NC Agricultural Automated Weather
`Network and Development of Advanced Communication, Data Acquisitions amd
`Dissemation System, MS.
`38. Jeremy Palmer, Design and Analysis of a VLSI-MEMS-Based Diffractive Optical
`Beam Steering System, MS.
`39. Som Chaudry, MEMS devices for laser radar, MS.
`40. Srisai Rao, Design, place and route of an IDEA processor, MS.
`41. Kevin Mock, IDEA Implementation, MS.
`42. Sibi Kuruvilli, Synthesized SAND Issue Unit, MS
`43. Tom Mills, Macromodelling of high speed digital drivers and receivers, MS.
`44. Matreiya Sengupta, Managing Crosstalk in Interconnect Design, MS.
`45. Andrew Stanaski, Optimizing Memory Design for Packagability, MS.
`46. Jonathon Schaeffer, A 400 MHz CMOS Multiplier, MS.
`47. Harsh Deshmane, MCM Extractor in Magic, MS.
`48. Sha Ma, Circuits for Low Energy Computing, MS.
`
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`Paul D. Franzon
`
`49. Shauki Elassaad, Placement tools for multi-chip modules, MS.
`50. Alex Dalal, CAD tools for yield estimation, MS.
`
`
`Committee Memberships: Do not track
`
`III. SCHOLARSHIP IN THE REALMS OF FACULTY
`RESPONSIBILITY
`
`A. PUBLICATIONS AND AWARDS
`
`BOOKS
`
`1. Smith and P. Franzon: Verilog Styles for Synthesis of Digital Systems, 2000, by
`Prentice Hall.
`
`2. D. Doane and P. Franzon: Multichip Modules: Basics and Alternatives, 1993, by
`Van Nostrand Rheinhold.
`
`3. J-D Cho and P.D. Franzon, High Performance Design Automation for Multi-Chip
`Modules and Packages, 1996, World Scientific.
`
`
`BOOK CHAPTERS
`
`1. G. Burr, P. Franzon, “Storage Class Memories”, in “Emerging Nanoelectronic Devices,”
`An Chen, J. Hutchby, V. Zhrinov, G. Bourianoff, (Wiley), 2014.
`
`2. P. Franzon, M. Swaminathan, “Chip Package Codesign,” in The Handbook for EDA of
`Electronic Circuits, Lou Scheffer, Luciano Lavagno and Grant Martin (editors), CRC
`Press, 2015. (Second Edition.)
`
`3. Eric Wyers, Tim Kelley, and Paul Franzon, “Optimization for Self-Calibrating
`Circuits,” in Semiconductor Devices in Harsh Conditions, (CRC), 2015.
`
`
`4. P. Franzon, “Use of AC Coupled Interconnect in Contactless Packaging,” appear in
`“Coupled Data Communications,” Ron Ho (ed), Springer-Verlag, Fall 2009
`
`
`5. P. Franzon, Design for 3-D Integration, 3-D IC Integration: Technology and
`Applications, P. Garrou, P. Ramm, C. Bower, (editors), Wiley VCH, May 2008.
`
`
`6. P. D. Franzon, D. Nackashi, C. Amsinck, N. DiSpigna, S. Sonkulale, “Molecular
`Electronics – Devices and Circuits Technology”, in Vlsi-Soc: From Systems To Silicon,
`(Springer Boston), Oct. 2007.
`
`
`7. P. Franzon, Chip-Package Codesign, in The Handbook for EDA of Electronic Circuits,
`Lou Scheffer, Luciano Lavagno and Grant Martin (editors), CRC Press, 2005.
`
`
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`Paul D. Franzon
`
`
`8. P. Franzon, Multichip Module Technology, to appear in the The Electronic Handbook,
`J. Whitaker (editor), (CRC Press), 1996.
`
`
`9. S. Mehrotra and P. Franzon, Performance Driven Global Routing and Wiring Rule
` Generation for High Speed PCBs and MCMs , in Advanced Routing of Electronic
` Modules, M. Pecht (editor), (Kluwer), 1995.
`
`10. P. Franzon and Michael Steer: Tools and Techniques for the Design of High Speed
`Multichip Modules}, Chapter 7 in Electronics Packaging Forum,Volume 3, J. Mor-
`ris (ed), 1993 by IEEE Press.
`
`11. P. Franzon, Comparison of Reconfiguration Schemes for Defect Tolerant Mesh
`
`Arrays , in Defect and Fault Tolerance in VLSI Systems, Volume 2, V.K. Jain
`
`(editor), (Plenum), 1989.
`
`
`12. M. Hatamian, L.A. Hornak, T. Little, S.K. Tewksbury and P. Franzon: Fundamen-
`tal interconnection issues in, Electronic Materials Handbook,Volume 1:Packaging,
`
` Article 1BA (ASM International), 1989, pages 1-11.
`
`
`13. P. Franzon and S.K. Tewksbury: ‘Chip Frame’ scheme for reconfigurable mesh-
`
`connected arrays, in Wafer Scale Integration II, R.M. Lea (editor), (North Holl-
`
`and), 1988.
`
`
`14. P.D. Franzon: Yield Modeling for Fault Tolerant VLSI ,in Systolic Arrays, W.
` Moore, A. McCabe and R. Urquhart (editors), (Adam Hilger), 1987.
`
`
`JOURNAL PUBLICATIONS
`
`
`1. Charles, G.; Franzon, P.D., "A Multitier Study on Various Stacking Topologies of TSV-
`Based PDN Systems Using On-Chip Decoupling Capacitor Models," in Components,
`Packaging and Manufacturing Technology, IEEE Transactions on , vol.5, no.4, pp.541-
`550, April 2015
`
`2. Wyers, E.J.; Morton, M.A.; Sollner, T.C.L.G.; Kelley, C.T.; Franzon, P.D., "A
`Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing
`RFICs," in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on ,
`vol.PP, no.99, pp.1-1
`
`3. Gadfort, P.; Franzon, P.D., "Millimeter-Scale True 3-D Antenna-in-Package Structures
`for Near-Field Power Transfer," in Components, Packaging and Manufacturing
`Technology, IEEE Transactions on , vol.4, no.10, pp.1574-1581, Oct. 2014
`
`
`
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`Paul D. Franzon
`
`4. Priyadarshi, S.; Davis, W.R.; Steer, M.B.; Franzon, P.D., "Thermal Pathfinding for 3-D
`ICs," in Components, Packaging and Manufacturing Technology, IEEE Transactions
`on , vol.4, no.7, pp.1159-1168, July 2014
`
`
`5. Bapat, O.A.; Franzon, P.D.; Fastow, R.M., "A Generic and Scalable Architecture for a
`Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using
`Logic on Memory," Very Large Scale Integration (VLSI) Systems, IEEE Transactions
`on , vol.PP, no.99, pp.1,1, 2014.
`
`6. Xi Chen; Ting Zhu; Davis, W.R.; Franzon, P.D., "Adaptive and Reliable Clock
`Distribution Design for 3-D Integrated Circuits," Components, Packaging and
`Manufacturing Technology, IEEE Transactions on , vol.4, no.11, pp.1862,1870, Nov.
`2014
`
`
`7. Priyadarshi, S.; Davis, W.R.; Steer, M.B.; Franzon, P.D., "Thermal Pathfinding for 3-D
`ICs," Components, Packaging and Manufacturing Technology, IEEE Transactions on ,
`vol.4, no.7, pp.1159,1168, July 2014
`
`8. Sarkar, B.; Ramanan, N.; Jayanti, S.; Di Spigna, N.; Bongmook Lee; Franzo