Trials@uspto.gov
`571.272.7822
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` Paper No. 7
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` Filed: February 9, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`CISCO SYSTEMS, INC.,
`Petitioner,
`
`v.
`
`TQ DELTA, LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01466
`Patent 8,611,404 B2
`____________
`
`
`Before SALLY C. MEDLEY, KALYAN K. DESHPANDE, and
`TREVOR M. JEFFERSON, Administrative Patent Judges.
`
`DESHPANDE, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`571.272.7822
`
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`
`
`
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` Paper No. 7
`
`
` Filed: February 9, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`CISCO SYSTEMS, INC.,
`Petitioner,
`
`v.
`
`TQ DELTA, LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01466
`Patent 8,611,404 B2
`____________
`
`
`Before SALLY C. MEDLEY, KALYAN K. DESHPANDE, and
`TREVOR M. JEFFERSON, Administrative Patent Judges.
`
`DESHPANDE, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`IPR2016-01466
`Patent 8,611,404 B2
`
`
`INTRODUCTION
`I.
`Cisco Systems, Inc. (“Petitioner”) filed a Petition requesting an inter
`partes review of claims 6, 10, 11, 15, 16, and 20 of U.S. Patent
`No. 8,611,404 B2 (Ex. 1001, “the ’404 patent”). Paper 1 (“Pet.”). TQ
`Delta, LLC (“Patent Owner”) filed a Preliminary Response. Paper 6
`(“Prelim. Resp.”). We have jurisdiction under 35 U.S.C. § 314(a), which
`provides that an inter partes review may not be instituted “unless . . . there is
`a reasonable likelihood that the petitioner would prevail with respect to at
`least 1 of the claims challenged in the petition.” After considering the
`Petition, the Preliminary Response, and associated evidence, we conclude
`that Petitioner has demonstrated a reasonable likelihood that it would prevail
`in showing the unpatentability of claims 6, 10, 11, 15, 16, and 20 of the ’404
`patent. Thus, we authorize institution of an inter partes review of claims 6,
`10, 11, 15, 16, and 20 of the ’404 patent as unpatentable over Bowie,
`Yamano, and ANSI T1.413.
`A. Related Proceedings
`Petitioner indicates that the ’404 patent is the subject of several
`
`district court proceedings. See Pet. 1. Petitioner further indicates that the
`’404 patent is involved in ARRIS Group, Inc. v. TQ Delta, LLC., Case
`IPR2016-01160 (PTAB Dec. 14, 2016). Id.
`B. The ʼ404 Patent (Ex. 1001)
`The ’404 patent discloses a method and apparatus for establishing a
`
`power management sleep state in a multicarrier system. Ex. 1001, 1:31‒33.
`The ’404 patent discloses an asynchronous digital subscriber loop (ADSL)
`system having a first transceiver located at the site of a customer’s premises
`(“CPE transceiver”) and a second transceiver located at the local central
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`telephone office (“CO transceiver”). Id. at 3:62‒67. The transceivers
`include a transmitter section for transmitting data over a digital subscriber
`line and a receiver section for receiving data from the line. Id. at 4:14‒17.
`The transceivers further include a clock, controller, frame counter, and a
`state memory. Id. at 4:58‒5:15. Typically, data is communicated in the
`form of a sequence of data frames, sixty-eight frames for ADSL, followed
`by a synchronization frame. Id. The sixty-nine frames comprise a
`“superframe.” Id.
`The power down operation of the CPE transceiver begins on receipt of
`a power-down indication. Id. at 6:27‒30. The CPE transceiver responds to
`the power down indication by transmitting to the CO transceiver an “Intend
`to Enter Sleep Mode” notification. Id. at 6:39‒42. The CO transceiver
`responds by transmitting an “Acknowledge Sleep Mode” notification to the
`CPE transceiver, and the CPE transceiver transmits an “Entering Sleep
`Mode” notification to the CO transceiver. Id. at 6:53‒65. The CO
`transceiver detects the notification and transmits its own “Entering Sleep
`Mode” notification. Id. at 6:65‒67. The CO transceiver stores its state in its
`own state memory corresponding to the state memory of the CPE
`transceiver. Id. at 6:67‒7:2. The CO transceiver continues to advance the
`frame count and the superframe count during the period of power-down in
`order to ensure synchrony with the CPE transceiver when communications
`are resumed. Id. at 7:9‒12. The CO transceiver further continues to monitor
`the subscriber line for an “Exiting Sleep Mode” notification, and the CPE
`transceiver transmits this signal when it receives an “Awaken” indication.
`Id. at 7:57‒64. In response to the “Awaken” signal, CPE transceiver
`retrieves its store state from state memory and restores full power to its
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`circuitry. Id. at 7:64‒66. CO Transmitter detects “Exit Sleep Mode”
`notification and restores its state and power. Id. at 8:1‒4.
`C. Illustrative Claim
`Petitioner challenges claims 6, 10, 11, 15, 16, and 20 of the ’404
`patent. Pet. 12–62. Claims 6, 11, and 16 are independent claims. Claim 6 is
`illustrative of the claims at issue and is reproduced below:
`6.
`An apparatus comprising a transceiver operable to:
`receive, in a full power mode, a plurality of superframes,
`wherein the superframe comprises a plurality of data frames
`followed by a synchronization frame;
`receive, in the full power mode, a synchronization signal;
`transmit a message to enter into a low power mode;
`store, in a low power mode, at least one parameter
`associated with the full power mode operation wherein the at
`least one parameter comprises at least one of a fine gain
`parameter and a bit allocation parameter;
`receive, in the low power mode, a synchronization signal;
`
`exit from the low power and restore the full power mode
`by using the at least one parameter and without needing to
`reinitialize the transceiver.
`Ex. 1001, 10:29‒43.
`D. The Alleged Ground of Unpatentability
`The information presented in the Petition sets forth a proposed ground
`of unpatentability of claims 6, 10, 11, 15, 16, and 20 of the ’404 patent under
`35 U.S.C. § 103(a) as follows (see Pet. 12–62):1
`
`and
`
`
`1 Petitioner supports its challenge with the Declaration of Sayfe Kiaei, Phd.
`(Ex. 1003).
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`References
`Bowie,2 Yamano,3 and
`ANSI T1.4134
`
`Claims
`Challenged
`6, 10, 11, 15, 16, and 20
`II. ANALYSIS
`A. Claim Construction
`The Board interprets claims of an unexpired patent using the broadest
`reasonable construction in light of the specification of the patent in which
`they appear. See 37 C.F.R. § 42.100(b); see Cuozzo Speed Techs., LLC v.
`Lee, 136 S. Ct. 2131, 2142–46 (2016). Under the broadest reasonable
`construction standard, claim terms are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in the
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007).
`1. “Synchronizing Signal”
`Petitioner argues that the ’404 patent specification does not define
`“synchronization signal.” Pet. 11 (citing Ex. 1003, 20). Rather, Petitioner
`argues that the ’404 patent describes a “timing reference signal 62[] is
`transmitted from the transmitter with which the receiver 16 communicates
`(e.g., the CO transmitter).” Id. (citing Ex. 1001, 5:39‒41). Petitioner argues
`that the signal may be “a pure tone of fixed frequency and phase which is
`synchronized with the Master Clock in the transmitter.” Id. (citing Ex. 1001,
`
`
`2 U.S. Patent No. 5,956,323; issued Sep. 21, 1999 (Ex. 1005) (“Bowie”).
`3 U.S. Patent No. 6,075,814; issued Jun. 13, 2000 (Ex. 1006) (“Yamano”).
`4 Network and Customer Installation Interfaces – Asymmetric Digital
`Subscriber Line (ADSL) Metallic Interface, AMERICAN NATIONAL
`STANDARDS INSTITUTION (ANSI) T1.413-1995 STANDARD (Ex. 1007)
`(“ANSI T1.413”).
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`5:41‒45). Petitioner argues that the ’404 patent describes a synchronizing
`pilot tone that is used “to maintain synchronization during the power down
`or idle state” between a CO transceiver and CPE transceiver. Id. (citing Ex.
`1001, 7:13‒15). Accordingly, Petitioner proposes that “synchronization
`signal” should be interpreted to include “a signal used to maintain timing
`between transceivers.” Id. at 12. Patent Owner argues that “[i]t is not
`necessary at this stage of the proceeding to construe these limitations,” but
`proposes that the broadest reasonable interpretation of “synchronization
`signal” is “an indication used to establish or maintain a timing relationship
`between transceivers.” Prelim. Resp. 6‒7.
`We are persuaded by Petitioner and Patent Owner. Both Petitioner
`and Patent Owner argue that “synchronization signal” should be interpreted
`to mean a signal or indication used to maintain the timing between
`transceivers. The ’404 patent discloses that “[t]he timing reference signal
`‘synchronizes frame counter of the CPE transceiver to the corresponding
`frame counter of the CO transceiver.’” Ex. 1001, 5:50‒52. Accordingly, the
`’404 specification does not limit whether the synchronization signal
`establishes or maintains timing between the transceivers. Accordingly, we
`interpret “synchronization signal” to mean “a signal allowing frame
`synchronization between the transmitter of the signal and the receiver of the
`signal.”
`2. “store/storing, in a/the low power mode”
`Petitioner argues that the Specification of the ’404 patent does not
`recite these exact same terms as above, but discloses “a CO transceiver and a
`CPE transceiver that store their respective states in memory upon ‘Entering
`Sleep Mode’ and retain these states in memory while in sleep mode.”
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`Pet. 9‒10 (citing Ex. 1001, 6:67‒7:9, 7:35‒42; Ex. 1003, 18‒19). Petitioner
`argues that also upon entering “Sleep Mode” both the CO and CPE
`transceivers reduce power. Id. (citing Ex. 1001, 7:15‒16, 7:44‒47).
`Petitioner argues that the CO and CPE transceivers retrieve their states from
`memory and restore their states upon exiting “Sleep Mode.” Id. (citing
`Ex. 1001, 7:65‒66, 8:1‒4; Ex. 1003, 20). Petitioner, accordingly, argues that
`“store/storing, in a/the low power mode” should be interpreted to mean
`“maintaining in memory while in a reduced power consumption mode.” Id.
`at 11 (citing Ex. 1003, 20). Patent Owner argues that “[i]t is not necessary at
`this stage of the proceeding to construe these limitations,” but proposes that
`the broadest reasonable interpretation of “store/storing, in a/the low power
`mode” is “maintaining in memory . . . while in a low power mode.” Prelim.
`Resp. 6‒7.
`We are persuaded by Petitioner and Patent Owner. The construction
`proposed by Patent Owner is not inconsistent with the construction provided
`by Petitioner, and because Petitioner’s construction is based in light of the
`’404 patent specification, on this record, we interpret “store/storing, in a/the
`low power mode” to mean “maintaining in memory while in a reduced
`power consumption mode.”
`B. Obviousness of Claims 6, 10, 11, 15, 16, and 20 over Bowie, Yamano,
`and ANSI T1.413
`Petitioner contends that claims 6, 10, 11, 15, 16, and 20 of the ’404
`patent are unpatentable under 35 U.S.C. § 103(a) as obvious over Bowie,
`Yamano, and ANSI T1.413. Pet. 12–62. For the reasons discussed below,
`the evidence, on this record, indicates there is a reasonable likelihood that
`Petitioner would prevail in showing that claims 6, 10, 11, 15, 16, and 20 of
`the ’404 patent are unpatentable under 35 U.S.C. § 103(a) as obvious.
`
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`1. Bowie (Ex. 1005)
`Bowie discloses a power conservation system for transmission
`systems in which data is modulated over a communications loop from a
`central office location to a customer premise. Ex. 1005, 1:4‒8. Bowie
`discloses that to provision ADSL service, ADSL units are located at each
`end of a wire loop, a first ADSL unit at the customer premises (CPE) and a
`second ADSL unit at the telephone company central office (COT). Id. at
`3:51‒58. Data is arranged in a structure known as a “frame” prior to
`transmission. Id. at 3:66‒67.
`ADSL units enter a low power mode to reduce power requirements.
`Id. at 5:6‒8. CPE unit initiates low power mode by sending a “shut-down”
`signal to the COT unit. Id. at 5:8‒10. Both the CPE unit and COT unit may
`store loop characteristics that enable rapid resumption of user data
`transmission when units return to full power mode. Id. at 5:18‒25. Each
`unit then enters low power mode by shutting off the now unnecessary
`sections of the signal processing, transmitting, and receiving circuitry. Id. at
`5:26‒28. After shutdown, the loop is in an inactive state. Id. at 5:28‒29.
`The units return to full power mode after the CPE unit transmits to the
`COT unit a resume signal. Id. at 5:48‒59. The stored loop characteristics
`are used to restore the loop parameters. Id. at 5:60‒66.
`2. Yamano (Ex. 1006)
`Yamano discloses a method for the reduction of single processing in a
`modulator and demodulator transferring packet-based data. Ex. 1006, 1:9‒
`13. Yamano discloses an embodiment where a transmitter circuit transmits a
`predetermined non-idle state signal to indicate that packet data is about to be
`transmitted prior to the transmission of packet data. Id. at 13:56‒59. If the
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`non-idle state signal is not transmitted, the transmitter does not transmit any
`signals on the communication channel, and, therefore, the transmitter does
`not transmit any idle information. Id. at 13:59‒63. Upon detection of the
`predetermined non-idle state signal, the receiver enters full processing mode
`and performs full demodulation of the incoming signal. Id. at 14:25‒29.
`After the packet data has been received, the receiver detects the absence of
`the predetermined non-idle state signal and the receiver enters a reduced
`processing mode by disabling several components of the receiver. Id. at
`14:29‒42.
`3. ANSI T1.413 (Ex. 1009)
`ANSI T1.413 discloses electrical characteristics of Asymmetric
`Digital Subscriber Line (ADSL) signals appearing at a network interface.
`Ex. 1009, Abstract. ADSL allows for the provision of Plain Old Telephone
`Service (POTS) and a variety of digital channels. Id. at 1. Digital channels
`consist of full duplex low-speed channels and simplex high-speed channels
`in the direction from the network to the customer premises, and low-speed
`channels in the opposite direction. Id.
`4. Analysis
`The evidence set forth by Petitioner indicates there is a reasonable
`likelihood that Petitioner will prevail in showing that claims 6, 10, 11, 15,
`16, and 20 are unpatentable under 35 U.S.C. § 103(a) as obvious. Pet. 12–
`62.
`
`For example, claim 6 recites “[a]n apparatus comprising a
`transceiver.” Petitioner argues that Bowie discloses this limitation.
`Petitioner argues that Bowie discloses a modulated data transmitting and
`receiving unit, and circuitry to transmit and receive modulated data signal
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`that includes Asymmetric Digital Subscriber Line (ADSL) circuitry. Pet.
`29‒31 (citing Ex. 1005, 2:30‒37, 2:41‒43, 3:33‒41, 3:51‒58, Fig. 1; Ex.
`1003, 40‒41).
`Claim 6 further recites “receive, in a full power mode, a plurality of
`superframes, wherein the superframe comprises a plurality of data frames
`followed by a synchronization frame.” Petitioner argues that the
`combination of Bowie and ANSI T1.413 disclose this limitation. Petitioner
`argues that Bowie discloses single processing, transmitting, and receiving
`circuitry “can be placed in a low power state when inactive, and then re-
`energized to resume full power operation as needed.” Pet. 31 (quoting Ex.
`1005, 3:2‒5) (emphasis omitted). Petitioner specifically argues that Bowie
`discloses that in the full power state, Bowie’s ADSL unit receives modulated
`data signals in high frequency ranges that require substantial amounts of
`power. Id. at 31‒32 (citing Ex. 1003, 41‒42; Ex. 1005, 2:1‒4). Petitioner
`further argues that Bowie discloses that “[d]ata to be transmitted by an
`ADSL unit is arranged in a structure known as a ‘frame’ prior to be
`transmitted.” Id. at 32 (quoting Ex. 1005, 3:66‒67). Petitioner argues that
`ANSI T1.413 discloses that data streams are organized into superframes and
`“[e]ach superframe is composed of 68 ADSL data frames, numbered from
`0‒67, which shall be encoded and modulated into DMT symbols, followed
`by a synchronization symbol.” Id. at 32‒33 (quoting Ex. 1007, 42).
`Petitioner argues that a person with ordinary skill in the art would have
`combined Bowie’s frames with ANSI T1.413’s organization of frames into
`superframes including a synchronization symbol because ANSI T1.413
`discloses the ADSL communication standard that Bowie implements,
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`thereby allowing Bowie’s ADSL units to interoperate with ADSL models of
`other manufacturers. Id. at 34 (citing Ex. 1003, 46).
`Claim 6 also recites “receiv[ing], in the full power mode, a
`synchronization signal.” Petitioner argues that the combination of Bowie
`and ANSI T1.413 discloses this limitation. Petitioner argues that, as
`discussed above, Bowie discloses ADSL units that transmit and receive data
`in frames in full-power mode and ANSI T1.413 discloses that a
`synchronization symbol is included in the frames transmitted and received
`by ADSL units. Id. at 34‒35 (citing Ex. 1003, 46‒47; Ex. 1007, 42, 64, Fig.
`5). Petitioner explains that ANSI T1.413 uses a synchronization symbol in
`order to maintain timing by correcting timing errors in communication
`between DSL transceivers. Id. (citing Ex. 1007, 64). Petitioner argues that a
`person with ordinary skill in the art would have combined Bowie’s frames
`with ANSI T1.413’s superframes, which include a synchronization symbol,
`in order to correct timing errors. Id. at 34 (citing Ex. 1003, 48‒49).
`Claim 6 additionally recites “transmit[ting] a message to enter into a
`low power mode.” Petitioner argues that Bowie discloses this limitation.
`Specifically, Petitioner argues that Bowie discloses that the ADSL unit
`initiates the low-power state by sending a shutdown signal, and a person
`with ordinary skill in the art would have understood that such a signal
`includes data, thereby making it a message. Pet. 36‒38 (citing Ex. 1005,
`5:6‒13; Ex. 1003, 51). As such, a person with ordinary skill in the art would
`have understood Bowie to disclose transmitting a message to enter a low-
`power mode. Id.
`Claim 6 also recites “stor[ing], in a low power mode, at least one
`parameter associated with the full power mode operation.” Petitioner argues
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`that Bowie discloses this limitation. Petitioner argues that Bowie discloses
`that the COT and CPE units store “loop characteristic parameters” upon
`receipt of a shutdown signal. Pet. 38‒39 (citing Ex. 1005, 5:17‒27; Ex.
`1003, 51). Petitioner further argues that Bowie discloses that the storing of
`loop characteristic parameters “enables rapid resumption of data
`transmission when the units are returned to full power mode.” Id. (quoting
`Ex. 1005, 17‒27; citing Ex. 1005, 60‒66).
`Claim 6 additionally recites “wherein the at least one parameter
`comprises at least one of a fine gain parameter and a bit allocation
`parameter.” Petitioner argues that the combination of Bowie and ANSI
`T1.413 discloses this limitation. Petitioner argues that, as discussed above,
`Bowie discloses storing loop characteristic parameters before entering a low-
`power mode. Pet. 39 (citing Ex. 1003, 53). Petitioner further argues that
`ANSI T1.413 discloses that “fine gain (e.g., power level for each sub-
`carrier) and bit allocation (e.g., number of bits for each sub-carrier) are
`parameters of the communication loop that are determined upon
`initialization.” Id. at 40 (citing Ex. 1003, 53). Petitioner asserts that ANSI
`T1.413 discloses that “each receiver communicates to its far-end transmitter
`the number of bits and relative power levels to be used on each DMT sub-
`carrier, as well as any messages and final data rate information.” Id.
`(quoting Ex. 1007, 103;5 citing Ex. 1003, 54) (emphasis omitted). Petitioner
`further argues that a person with ordinary skill in the art “would understand
`that the relative power levels per DMT subcarrier are fine gain parameters
`
`
`5 Petitioner provides a citation to page 105. See Pet. 40. However, Petitioner
`quotes a passage from page 103. See id. We understand this to be a
`typographical error.
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`and the number of bits to be used on each DMT sub-carrier are bit allocation
`parameters,” and “these parameters are determined in order to initialize the
`DSL communication loop.” Id. (citing Ex. 1003, 54). Petitioner concludes
`that a person with ordinary skill in the art would have found it obvious to
`include these parameters in Bowie’s “loop characteristics” in order to “allow
`the DSL unit to more quickly retrain the units when returned to full power
`mode rather than having to reinitialize the units.” Id. (citing Ex. 1003, 54).
`Claims 6 further recites “receive, in the low power mode, a
`synchronization signal.” Petitioner argues that the combination of Bowie
`and Yamano discloses this limitation. Petitioner argues that Yamano
`discloses a low-power mode, where a receiving circuit of a modem operates
`in either a full-power mode or standby mode depending on whether data is
`being received. Pet. 41 (citing Ex. 1006, 14:25‒33; Ex. 1003, 54). In
`particular, Petitioner argues that Yamano discloses that the receiving circuit
`reduces power by disabling components when a “RECEIVE” signal is not
`transmitted. Id. (citing Ex. 1006, 14:25‒33, 14:40‒42, 15:54‒55).
`Petitioner argues that Yamano further discloses that the receive unit receives
`“an easily detected signal, such as a pure tone” that “can be used to signal
`the presence of packet data,” and upon received of such a signal the receiver
`enters full processing mode. Id. at 42 (quoting Ex. 1006, 14:20‒24; citing
`Ex. 1006, 14:25‒29). Petitioner argues that Yamano discloses this signal
`periodically in order to maintain synchronization of the time intervals
`between the receiver and transmitter units. Id. (citing Ex. 1006, 26:32).
`Petitioner asserts that a person with ordinary skill in the art would have
`understood a periodic or timing signal used to maintain synchronization
`between the receiver and transmitter units is a synchronization signal. Id. at
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`42‒43 (citing Ex. 1003, 56‒57). Petitioner concludes that a person with
`ordinary skill in the art would have combined these elements of Yamano
`with Bowie in order to achieve more efficient power usage. Id. at 43 (citing
`Ex. 1003, 57).
`Claim 6 also recites “exit from the low power and restore the full
`power mode by using the at least one parameter and without needing to
`reinitialize the transceiver.” Petitioner argues that Bowie discloses this
`limitation. Petitioner argues that Bowie discloses that “[u]pon receipt of the
`resume signal, the receiving ADSL unit returns the signal processing,
`transmitting, and receiving circuitry to full power mode.” Pet. 43 (quoting
`Ex. 1005, 60‒62) (reference numerals omitted). Petitioner argues that
`Bowie further discloses that “[i]f loop transmission characteristics had been
`stored, these parameters are retrieved from memory and used to enable data
`transmission to resume quickly by reducing the time needed to determine
`loop transmission characteristics.” Id. at 43‒44 (quoting Ex. 1005, 5:62‒64;
`citing Ex. 1003, 58) (reference numerals omitted).
`Petitioner argues that a person with ordinary skill in the art would
`have found it obvious to combine Bowie and Yamano because such a
`combination would have been “nothing more than the use of Yamano’s
`known techniques of deactivating circuits in a modem not used for
`communication with another DSL modem to improve Bowie’s DSL modem
`in the same way.” Pet. 25 (citing Ex. 1003, 34). Petitioner argues that both
`Bowie and Yamano are directed to “DSL communication systems and
`reducing the power consumption of DSL modems,” and, therefore, a person
`with ordinary skill in the art would have considered both Bowie and
`Yamano “when looking to reduce the power consumption of modems in
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`DSL systems.” Id. (citing Ex. 1003, 34). Petitioner explains that Yamano
`deactivates only the circuit not being used, thereby resulting in more defined
`power savings. Id. at 26 (citing Ex. 1003, 35). Accordingly, a person with
`ordinary skill in the art would have looked to Yamano when “seeking to
`further reduce power utilization in Bowie’s system.” Id. (citing Ex. 1003,
`35).
`
`Petitioner further argues that a person with ordinary skill in the art
`would have found it obvious to combine Bowie and Yamano with ANSI
`T1.413 because “Bowie and Yamano describe DSL communication systems,
`and ANSI T1.413 defines an ADSL communication standard that allow DSL
`modems to communicate.” Pet. 27 (citing Ex. 1003, 37). Petitioner explains
`that a person with ordinary skill in the art would have been motivated to
`implement systems according to a standard because “it would have been
`desirable for these modems to be interchangeable with other modems in
`order to make replacement and scaling easier.” Id. at 28‒29 (citing
`Ex. 1003, 38).
`Petitioner has provided a similar detailed analysis of claims 10, 11,
`15, 16, and 20. See Pet. 44‒62. Notwithstanding Patent Owner’s
`arguments, which we address below, we are persuaded that Petitioner has
`demonstrated a reasonable likelihood that it would prevail in showing that
`claims 6, 10, 11, 15, 16, and 20 are unpatentable under 35 U.S.C. § 103(a) as
`obvious.
`Patent Owner argues that (a) the combination of Bowie, Yamano, and
`ANSI T1.413 fails to disclose “transmitting, in a full power mode” both “a
`synchronization frame” and “a synchronization signal,” (b) the “storing”
`limitation, (c) the “exiting” limitation, (d) Petitioner fails to provide a
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`reasoned analysis to support a finding that it would have been obvious to
`combine Bowie and Yamano, and (e) Petitioner fails to provide a reasoned
`analysis to support a finding that it would have been obvious to combine
`Bowie and Yamano with ANSI T1.413. Prelim. Resp. 18–59. We address
`each argument in the order presented by Patent Owner.
`a. “Synchronization Frame” and “Synchronization Signal”
`Claim 6 recites “the super frame comprises a plurality of data frames
`followed by a synchronization frame” and “receive, in the full power mode,
`a synchronization signal.” Independent claims 11 and 16 recite similar
`limitations. Patent Owner argues that Petitioner asserts that ANSI T1.413
`discloses both the “synchronization frame” and the “synchronization signal,”
`as required by claims 6, 10, 11, 15, 16, and 20. Prelim. Resp. 19‒22. Patent
`Owner argues that “Petitioner improperly relies on a single disclosed feature
`in ANSI Standard [ANSI T1.413] to teach the two claimed elements of a
`‘synchronization frame’ and a ‘synchronization signal.’” Id.
`We are not persuaded by Patent Owner’s argument. As discussed
`above, Petitioner relies on ANSI T1.413 as disclosing “the super frame
`comprises a plurality of data frames followed by a synchronization frame.”
`Specifically, Petitioner argues that ANSI T1.413 discloses that data streams
`are organized into superframes and “[e]ach superframe is composed of 68
`ADSL data frames, numbered from 0‒67, which shall be encoded and
`modulated into DMT symbols, followed by a synchronization symbol.”
`Pet. 32‒33 (quoting Ex. 1007, 42). Petitioner further argues ANSI T1.413
`discloses that a synchronization symbol is included in the frames transmitted
`and received by ADSL units. Id. at 34‒35 (citing Ex. 1003, 46‒47;
`Ex. 1007, 42, 64, Fig. 5).
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`As such, Petitioner argues that a superframe is organized to include a
`synchronization symbol as the last frame of a superframe, and the
`synchronization symbol is also a signal that is used to maintain
`synchronization between ADSL units. That is, the synchronization symbol
`is included in the structure of a superframe and has the function of a
`synchronization signal. Although Patent Owner cites to several decisions
`that articulate that a single structure cannot meet two claimed structures,
`Patent Owner does not provide any evidence that ANSI T1.413’s disclosure
`of a synchronization symbol cannot be included in the structure of a
`superframe and function as a synchronization signal that is received in full
`power mode. Absent credible evidence to the contrary, we unpersuaded, on
`this record, by Patent Owner’s argument.
`b. The “Storing” Limitation
`Independent claim 6 recites “stor[ing], in a low power mode, at least
`one parameter associated with the full power mode operation” and “wherein
`the at least one parameter comprises at least one of a fine gain parameter and
`a bit allocation parameter.” Independent claims 11 and 16 recite similar
`limitations. Patent Owner argues that “Bowie does not teach or suggest
`storing, in a low power mode, fine gain or bit allocation parameters – and
`Petitioner does not contend otherwise.” Prelim. Resp. 22‒23 (citing Pet. 39‒
`41). Patent Owner argues that Petitioner relies on a section of ANSI T1.413
`that discloses “the number of bits and relative power levels to be used in
`each DMT sub-carrier.” Id. at 23 (quoting Ex. 1007, 103; citing Pet. 40).
`Patent Owner argues that this section of ANSI T1.413 is in the context of
`communicating parameters, whereas the claims recite “storing” the
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`parameters. Id. Patent Owner further argues that ANSI T1.413 does not
`disclose storing these parameters “in low power mode.”
`We are not persuaded by Patent Owner’s argument. As discussed
`above, Petitioner argues that Bowie discloses “stor[ing], in a low power
`mode, at least one parameter associated with the full power mode
`operation.” See Pet. 38‒39. Petitioner argues that ANSI T1.413 discloses
`“wherein the at least one parameter comprises at least one of a fine gain
`parameter and a bit allocation parameter.” See id. at 39‒40. That is,
`Petitioner relies on Bowie as disclosing the storing the parameter in low
`power mode, and relies on ANSI T1.413 as disclosing the parameter is one
`of a fine gain parameter and a bit allocation parameter. As such, Patent
`Owner’s argument that ANSI T1.413 fails to disclose the storing of the
`parameter in low power mode is not persuasive because Petitioner did not
`rely on ANSI T1.413 as disclosing these limitations. Nonobviousness
`cannot be established by attacking the references individually when the
`rejection is predicated upon a combination of prior art disclosures. See In re
`Merck & Co. Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
`Patent Owner further argues that Petitioner’s “bifurcation of the
`Storing Limitation is improper.” Prelim. Resp. 24‒25. Patent Owner
`specifically argues that the stored “parameter” is the same as the “at least
`one of a fine gain parameter and a bit allocation parameter,” and “cannot be
`separated for the purposes of an invalidity analysis.” Id. Patent Owner
`argues that such an analysis “runs afoul of the maxim that obviousness be
`analyzed against the claim ‘as a whole’ and not with respect to ‘component
`part.’” Id. (citing Princeton Biochemicals, Inc. v. Bechman Coulter, Inc.,
`411 F.3d 1332, 1337 (Fed. Cir. 2005)).
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`We are not persuaded by Patent Owner’s argument. As discussed
`above, Petitioner relies on Bowie as disclosing the storing the parameter in
`low power mode, and relies on ANSI T1.413 as disclosing the parameter is
`one of a fine gain parameter and a bit allocation parameter. Petitioner
`argues that a person with ordinary skill in the art would have modified
`Bowie such that the parameter that is stored in low power mode is either a
`fine gain parameter or a bit allocation parameter, where these known
`parameters as evidenced by ANSI T1.413. Pet. 39‒40. Petitioner further
`argues that a person with ordinary skill in the art would have made such a
`modification in order to more quickly retrain the units and avoid
`initialization of the units. Id. As such, Petitioner accounts for the claim as a
`whole, and Patent Owner at this stage of the proceeding does not provid
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