throbber
Trials@uspto.gov
`571.272.7822
`
`
`
`
`
`Paper No. 11
` Filed: January 18, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`_____________
`
`Case IPR2016-01567
`Patent 5,894,441
`_____________
`
`
`
`Before BART A. GERSTENBLITH, BARBARA A. PARVIS, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`
`PARVIS, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`I.
`
`INTRODUCTION
`
`A.
`
`Background
`
`Apple Inc. (“Petitioner”) filed a Petition (Paper 1, “Pet.”) requesting
`
`institution of inter partes review of claims 6–12, 14, and 15 (“challenged
`
`claims”) of U.S. Patent No. 5,894,441 (Ex. 1003, “the ’441 Patent”).
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`Limestone Memory Systems LLC (“Patent Owner”) filed a Preliminary
`
`Response (Paper 8, “Prelim. Resp.”).
`
`For the reasons set forth below, on behalf of the Director (see
`
`37 C.F.R. § 42.4(a)), we decline to institute an inter partes review of the
`
`challenged claims of the ’441 Patent.
`
`B.
`
`Related Proceedings
`
`The parties indicate that the ’441 Patent is asserted against Petitioner
`
`in Limestone Memory Sys. LLC v. Apple Inc., No. 8:15-cv-01274 (C.D.
`
`Cal.). Pet. 1; Paper 4, 5. The parties indicate that other proceedings may be
`
`related. Pet. 1–2; Paper 4, 1–5.
`
`C.
`
`Real Parties-in-Interest
`
`The Petition identifies Apple Inc. as the real party-in-interest. Pet. 1.
`
`Patent Owner identifies Limestone Memory Systems LLC and Acacia
`
`Research Group LLC as the real parties-in-interest. Paper 4, 1.
`
`D.
`
`The References
`
`Petitioner relies on the following references:
`
`U.S. Patent No. 5,265,055, issued November 23, 1993 (Ex. 1005,
`
`“Horiguchi”); and
`
`U.S. Patent No. 5,126,973, issued on June 30, 1992 (Ex. 1006,
`
`“Gallia”).
`
`
`
`2
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`
`E.
`
`The Asserted Grounds of Unpatentability
`
`Petitioner asserts the following grounds of unpatentability (Pet. 4):
`
`Challenged Claims
`
`Basis
`
`Reference(s)
`
`6–12, 14, and 15
`
`§ 102(b) Horiguchi
`
`6, 7, 9, 11, 12, 14, and 15
`
`§ 102(b) Gallia
`
`8 and 10
`
`§ 103(a) Gallia and Horiguchi
`
`Petitioner supports its challenge with a declaration executed by
`
`Dr. Pinaki Mazumder on August 12, 2016 (Ex. 1001).
`
`F.
`
`The ’441 Patent
`
`The ʼ441 Patent is directed to a “SEMICONDUCTOR MEMORY
`
`DEVICE WITH REDUNDANCY CIRCUIT.” Ex. 1003, [54]. The
`
`’441 Patent explains:
`
`The semiconductor memory device according to this
`invention comprises a plurality of column selection lines, at least
`one redundant column selection line, a column decoder which
`activates one line out of the plurality of column selection lines in
`response to a column address, a first circuit which generates a
`detection signal when the column address of a defect-related
`column selection line is supplied, and a second circuit which
`receives at least a part of a row address and activates the
`redundant column selection line in response to at least a part of
`the row address and the detection signal. With this arrangement,
`when a defect occurs in one bit, instead of replacing all of the
`many bit lines included in the column selection line to which the
`defective bit line belongs, it is possible to relieve a larger number
`of defective bit lines using a single redundant column selection
`line by replacing only a part of these bit lines.
`
`Id. at 2:13–28.
`
`
`
`3
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`
`G.
`
`Illustrative Claim
`
`Claim 6 is the only independent claim challenged in this proceeding.
`
`Claims 7–12, 14, and 15 depend, directly or indirectly, from claim 6.
`
`Independent claim 6 is illustrative of the claimed subject matter and is
`
`reproduced below.
`
`6.
`
`A semiconductor memory device comprising:
`a plurality of word lines including at least first and second
`word lines;
`a plurality of bit lines including at least first and second bit
`
`lines;
`
`a plurality of redundant bit lines including at least first and
`second redundant bit lines;
`a plurality of memory cells each of which is disposed on
`intersections of said word lines and bit lines;
`a plurality of redundant memory cells each of which is
`disposed on intersections of said word lines and redundant bit
`lines;
`
`a plurality of column selection lines including at least a
`first column selection line; said first and second bit lines being
`selected when said first column selection line is activated;
`a redundant column selection line; said first and second
`redundant bit lines being selected when said redundant column
`selection line is activated;
`a column decoder activating said first column selection
`line in response to a first column address when said first word
`line is activated; and
`a column redundancy decoder activating said redundant
`column selection line in response to said first column address
`when said second word line is activated.
`
`Ex. 1003, 13:55–14:13.
`
`II.
`
`CLAIM CONSTRUCTION
`
`A.
`
`Legal Standard
`
`Petitioner contends “[t]he claim terms of the ’441 patent should be
`
`construed to have their plain and ordinary meaning in view of the
`
`
`
`4
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`specification.” Pet. 5. Petitioner does not propose that we construe any
`
`specific claim terms. Id. at 4–5. Patent Owner responds that it “agrees for
`
`purposes of this preliminary response that no construction is necessary to
`
`analyze whether trial should be instituted.” Prelim. Resp. 25.
`
`Only terms that are in controversy need to be construed, and only to
`
`the extent necessary to resolve the controversy. Wellman, Inc. v. Eastman
`
`Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs., Inc. v. Am.
`
`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). We determine that
`
`no express construction of a claim term is needed to resolve a dispute in this
`
`proceeding.
`
`III. ANALYSIS
`
`A.
`
`Independent Claim 6
`
`Petitioner asserts that claim 6 is anticipated by either Horiguchi or
`
`Gallia. Pet. 26–36, 51–62. The Petition includes discussion identifying
`
`where each of Horiguchi and Gallia allegedly describes the elements of
`
`claim 6. Id.
`
`1.
`
`Principles of Law
`
`Anticipation, under 35 U.S.C. § 102, requires a lack of novelty.
`
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
`
`2001). To establish anticipation, each and every element in a claim,
`
`arranged as is recited in the claim, must be found in a single prior art
`
`reference. Id.
`
`2.
`
`Horiguchi
`
`Horiguchi is directed to a semiconductor memory and in particular to
`
`“a technique for repairing a semiconductor memory in such a manner that
`
`
`
`5
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`defective memory cells are replaced by spare memory cells.” Ex. 1005, 1:9–
`
`13. Horiguchi discloses that
`
`FIG. 26 shows the eighth embodiment of a semiconductor
`memory according to the present invention. The present
`embodiment is different from the embodiments of FIGS. 21 and
`23 in that a memory array is divided into a plurality of memory
`mats (in the figure, four memory mats 130 to 133) in a direction
`parallel to bit lines. Each memory mat includes a region 140,
`141, 142, or 143 where regular memory cells are arranged, and a
`region 150, 151, 152, or 153 where spare memory cells are
`arranged.
`
`Id. at 21:52–61.
`
`3.
`
`Gallia
`
`Gallia is directed to a semiconductor memory device and in particular
`
`to “devices which include repair circuitry for eliminating defects in memory
`
`devices.” Ex. 1005, 1:5–8. Gallia explains that “each data block 12 is
`
`partitioned into sixteen sub-blocks 14.” Id. at 4:52–53.1 Gallia further
`
`explains:
`
`Within each sub-block 14, there are 256 row or word
`lines R and 256 column select lines Ys. For simplicity of
`illustration, only one row line R and one column select line Ys
`are shown in FIGS. 2 and 3. A row line is selectable based on
`row address information input to a one of sixteen row decoder
`stage 16 and a one of 256 row decoder stage 18 (See FIG. 2).
`There are 16 of the one of 256 stages 18, one for each sub-block
`14. In each data block 12, column address decoders 20 turn on a
`select line Ys to control read/-write data transfer for two columns.
`
`Id. at 5:10–20.
`
`
`1 Boldface omitted from reference numerals in patents throughout.
`
`
`
`6
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`
`4.
`
`Asserted Anticipation by Horiguchi
`
`For the reasons set forth below, applying the standard set forth in
`
`35 U.S.C. § 314(a), we are not persuaded that Petitioner has demonstrated a
`
`reasonable likelihood that it would prevail is showing that claim 6 is
`
`anticipated by Horiguchi. Regarding “a plurality of column selection lines
`
`including at least a first column selection line; said first and second bit lines
`
`being selected when said first column selection line is activated” recited in
`
`claim 6, Petitioner provides the following annotations to Figure 26 of
`
`Horiguchi.
`
`
`
`Figure 26 illustrates a circuit diagram of a
`semiconductor device with annotations.
`
`Petitioner’s annotations include two horizontal lines in pink with the
`
`following notations “First column selection line Ys[0],” and “Second
`
`column selection line Ys[1],” respectively. Pet. 30. Petitioner contends:
`
`Horiguchi discloses “[a]n output YS[j] of the Y-decoder is
`applied to each memory mat through a wiring conductor which
`is indicated by a dot-dash line in FIG. 26.” Ex. 1005, 22:7-10.
`Fig. 26 shows column selection lines YS[j] running horizontally
`
`
`
`7
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`
`through all of the sub-arrays 130-133. For each value of “j”,
`column selection line YS[j] selects bit line B[j,n] in each of the
`sub-arrays. Ex. 1005, 22:8–10. Ex. 1001, ¶ 152.
`
`Id.
`
`Patent Owner contends that the “annotated reproduction of FIG. 26
`
`. . . includes pink lines added by the Petition,” but “the Petition offers no
`
`support whatsoever for the idea that there exists multiple column selection
`
`lines YS[0] and YS[1] in Horiguchi.” Prelim. Resp. 42. Patent Owner also
`
`contends that “[t]he Petition cites to a single passage of Horiguchi to support
`
`this claim limitation, which recites ‘[a]n output YS[j] of the Y-decoder is
`
`applied to each memory mat through a wiring conduction which is indicated
`
`by a dot-dash line in FIG. 26.’” Id. at 41.
`
`We find that Petitioner does not offer sufficient, persuasive evidence
`
`for its contention that “Fig. 26 shows column selection lines YS[j] running
`
`horizontally through all of the sub-arrays 130-133” (Pet. 30). Comparing
`
`Petitioner’s annotated Figure 26 (Pet. 30) and Figure 26 without annotations
`
`reveals that, although the first of the pink lines added by Petitioner
`
`corresponds to YS(j) in Horiguchi, the second of the pink lines does not
`
`have a corresponding column selection line YS in Figure 26.
`
`Additionally, Petitioner’s citation to Horiguchi’s description of
`
`Figure 26 (see Pet. 30 (citing Ex. 1005, 22:7–10)) does not support
`
`Petitioner’s argument that Horiguchi discloses multiple column selection
`
`lines. That portion, as well as the immediately preceding sentence, are
`
`reproduced below.
`
`Circuit blocks 230 to 233 each including sense amplifiers
`and input-output lines are provided so as to correspond to the
`memory maps 130 to 133, respectively. However, only a single
`Y-decoder 40 is provided in an end portion. An output YS[j] of
`
`
`
`8
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`
`the Y-decoder is applied to each memory mat through a wiring
`conductor which is indicated by a dot-dash line in FIG. 26.
`
`Ex. 1005, 22:3–10 (emphasis added). The emphasized language above is
`
`consistent with the illustration of only a single output in Figure 26.
`
`Furthermore, Horiguchi’s description of failure of the decoder
`
`circuitry also is consistent. In particular, Horiguchi describes the “plurality
`
`of memory mats use one Y-decoder in common” (id. at 22:15–16) and
`
`“where the Y-decoder is defective” the address signals “are not compared
`
`with any data” resulting in the “corresponding bit lines in four memory mats
`
`are simultaneously replaced by spare bit lines” (id. at 22:38–42). The expert
`
`testimony cited by Petitioner (Pet. 30 (citing Ex. 1001 ¶ 152)) does not offer
`
`additional persuasive supporting evidence.
`
`Based on the record before us, we are not persuaded that Petitioner
`
`has shown sufficiently that Horiguchi discloses “a plurality of column
`
`selection lines including at least a first column selection line; said first and
`
`second bit lines being selected when said first column selection line is
`
`activated,” as recited in claim 6. Accordingly, we determine that Petitioner
`
`has not shown a reasonable likelihood that it would prevail in establishing
`
`that claim 6 is anticipated by Horiguchi.
`
`5.
`
`Asserted Anticipation by Gallia
`
`For the reasons set forth below, we exercise our discretion under
`
`35 U.S.C. § 325(d) to deny institution of review on the basis of anticipation
`
`of claim 6 by Gallia. Petitioner acknowledges that on October 27, 2015,
`
`Micron Technology, Inc. filed a petition challenging claim 6, as well as
`
`other claims, of the ’441 Patent on the basis of obviousness over U.S. Patent
`
`No. 5,270,975 (Ex. 1008, “McAdams”) and Japanese Patent Appl. No. H06-
`
`052696 (“Minami”). Pet. 11 (citing Ex. 1007). As Petitioner further
`
`
`
`9
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`acknowledges, that inter partes review was not instituted. See Micron Tech.,
`
`Inc. v. Limestone Memory Sys. LLC, Case IPR2016-00094, Paper 8
`
`(submitted in the instant case as Ex. 1011). As relevant here, Gallia and
`
`McAdams share essentially the same disclosure.
`
`Patent Owner contends:
`
`In sum, the Petition suffers much the same problem as the
`‘094 petition, which the Board held did not adequately show that
`this claim limitation was satisfied by the identical McAdams
`disclosure. (See Ex. 1011 at 8–10.) Indeed, the ‘094 petition
`conceded that “[w]hat McAdams does not explicitly disclose is
`whether activating the column redundancy decoder occurs when
`a word line is activated.” (Ex. 1011 at 11; Ex. 1007 at 52.) The
`instant Petition has not offered any evidence to suggest that the
`‘094 petition was wrong on that point.
`
`Prelim. Resp. 49.
`
`Consistent with Patent Owner’s contentions, according to the Petition
`
`filed in the earlier proceeding (Ex. 1007, “the ’094 Petition”), McAdams
`
`does not disclose that the column decoder activates the first column selection
`
`line when the word line is activated. Ex. 1007, 48. Furthermore, the
`
`’094 Petition relied on, as supporting evidence, a declaration executed by
`
`Dr. R. Jacob Baker on October 22, 2015. See IPR2016-00094, Paper 1; Ex.
`
`1003. Consistent with Patent Owner’s contentions in the instant proceeding
`
`(Prelim Resp. 49), in the earlier proceeding, Dr. Baker testified “[w]hat is
`
`not expressly disclosed in McAdams is that the column decoder activates the
`
`first column selection line in response to a first column address when said
`
`word line is activated.” See IPR2016-00094, Ex. 1003, A-38.
`
`We turn to the limitation conceded in the ’094 Petition, i.e., “a column
`
`decoder activating said first column selection line in response to a first
`
`column address when said first word line is activated” recited in claim 6. In
`
`
`
`10
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`the instant proceeding, Petitioner provides the following contentions for this
`
`limitation:
`
`Gallia describes that when a non-defective memory
`location memory is accessed, e.g., at a first row and first column
`address, address decoding is performed as follows: the first row
`decoder stage 16 decodes the least significant four bits of the row
`address to determine which of the 16 sub-arrays is being
`accessed. Then, a second row decoder stage 18 decodes the
`upper 8 bits of the row address to determine which of the 256
`rows is being accessed, and activates the corresponding word
`line R (i.e., first word line). Finally, column decoder 20 decodes
`an 8-bit column address (i.e., first column address) to activate a
`column selection line YS. Ex. 1006, 5:56-66; Fig. 2; Ex. 1001,
`¶ 209.
`
`Pet. 60–61 (emphases added).
`
`The emphasized language above in Petitioner’s contention suggests
`
`that the timing of events is staggered, i.e., “[t]hen” a second row stage
`
`decodes and “[f]inally” the column decoder decodes. Id. Additionally, the
`
`portion of Gallia identified in the Petition (Pet. 61 (citing Ex. 1006, 5:56–
`
`66)) describes “first row decoder stage 16” and “second row decoder
`
`stage 18” (Ex. 1006, 5:58–60 (emphases added)).
`
`Consistent with Patent Owner’s contentions (Prelim. Resp. 8–16),
`
`with respect to the disclosures relied upon by Petitioner, Gallia and
`
`McAdams share substantially the same disclosures. Compare, e.g.,
`
`Ex. 1006, Figs. 1–3, 5, with Ex. 1008, Figs. 1–3, 5. With respect to the only
`
`disclosure Petitioner relies on in Gallia for the requirement that the column
`
`decoder activate the first column selection line “when said first word line is
`
`activated” (Pet. 60–61 (citing Ex. 1006, 5:17–20, 5:56–66, Figs. 1, 2)), the
`
`corresponding disclosure of McAdams is the same as that in Gallia.
`
`Compare Ex. 1006, 5:17–20, 5:56–66, Figs. 1, 2, with Ex. 1008, 5:38–46,
`
`
`
`11
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`6:10–30, Figs. 1, 2. The expert testimony cited by Petitioner (Pet. 61 (citing
`
`Ex. 1001 ¶ 209)) is substantially the same as the argument presented in the
`
`Petition and does not offer additional persuasive supporting evidence.
`
`In determining whether to institute inter partes review, we may “deny
`
`some or all grounds for unpatentability for some or all of the challenged
`
`claims.” 37 C.F.R. § 42.108(b); see 35 U.S.C. § 314(a). Our discretionary
`
`determination of whether to institute review is guided by 35 U.S.C. § 325(d),
`
`which states, in relevant part, that “[i]n determining whether to institute or
`
`order a proceeding under this chapter, chapter 30, or chapter 31, the Director
`
`may take into account whether, and reject the petition or request because, the
`
`same or substantially the same prior art or arguments previously were
`
`presented to the Office (emphasis added).”
`
`In the instant proceeding, Petitioner does not identify new arguments
`
`based on additional references in combination with Gallia. Also, Petitioner
`
`does not make persuasive assertions that differentiate its Petition from the
`
`’094 Petition, or explain sufficiently why Gallia, which is substantially the
`
`same prior art as that previously presented, does not have the earlier-noted
`
`deficiency. Accordingly, we exercise our discretion under 35 U.S.C.
`
`§ 325(d) to deny institution of review on the basis of anticipation of claim 6
`
`by Gallia.
`
`B.
`
`Claims 7–12, 14, and 15
`
`Petitioner asserts that claims 7, 9, 11, 12, 14, and 15 are anticipated by
`
`each of Horiguchi and Gallia. Pet. 4. Petitioner also asserts that claims 8
`
`and 10 are anticipated by Horiguchi or obvious over Horiguchi and Gallia.
`
`Id. Each of claims 7–12, 14, and 15 depends, directly or indirectly, from
`
`independent claim 6. Petitioner’s challenges do not remedy the deficiencies
`
`
`
`12
`
`

`
`IPR2016-01567
`Patent 5,894,441
`
`noted above for independent claim 6. Accordingly, we decline to institute
`
`review of any of claims 7–12, 14, and 15 of the ’441 Patent for the reasons
`
`set forth above.
`
`For the foregoing reasons, it is:
`
`IV. ORDER
`
`ORDERED that the Petition is denied and no inter partes review is
`
`instituted.
`
`
`
`PETITIONER:
`
`John R. Hutchins
`ANDREWS KURTH KENYON LLP
`jhutchins@kenyon.com
`
`PATENT OWNER:
`
`Nicholas T. Peters
`Paul Henkelmann
`FITCH EVEN TABIN & FLANNERY LLP
`ntpete@fitcheven.com
`phenkelmann@fitcheven.com
`
`13

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