`571.272.7822
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`Paper No. 11
` Filed: January 18, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC,
`Patent Owner.
`_____________
`
`Case IPR2016-01567
`Patent 5,894,441
`_____________
`
`
`
`Before BART A. GERSTENBLITH, BARBARA A. PARVIS, and
`ROBERT J. WEINSCHENK, Administrative Patent Judges.
`
`PARVIS, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
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`I.
`
`INTRODUCTION
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`A.
`
`Background
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`Apple Inc. (“Petitioner”) filed a Petition (Paper 1, “Pet.”) requesting
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`institution of inter partes review of claims 6–12, 14, and 15 (“challenged
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`claims”) of U.S. Patent No. 5,894,441 (Ex. 1003, “the ’441 Patent”).
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`IPR2016-01567
`Patent 5,894,441
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`Limestone Memory Systems LLC (“Patent Owner”) filed a Preliminary
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`Response (Paper 8, “Prelim. Resp.”).
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`For the reasons set forth below, on behalf of the Director (see
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`37 C.F.R. § 42.4(a)), we decline to institute an inter partes review of the
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`challenged claims of the ’441 Patent.
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`B.
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`Related Proceedings
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`The parties indicate that the ’441 Patent is asserted against Petitioner
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`in Limestone Memory Sys. LLC v. Apple Inc., No. 8:15-cv-01274 (C.D.
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`Cal.). Pet. 1; Paper 4, 5. The parties indicate that other proceedings may be
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`related. Pet. 1–2; Paper 4, 1–5.
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`C.
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`Real Parties-in-Interest
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`The Petition identifies Apple Inc. as the real party-in-interest. Pet. 1.
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`Patent Owner identifies Limestone Memory Systems LLC and Acacia
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`Research Group LLC as the real parties-in-interest. Paper 4, 1.
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`D.
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`The References
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`Petitioner relies on the following references:
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`U.S. Patent No. 5,265,055, issued November 23, 1993 (Ex. 1005,
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`“Horiguchi”); and
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`U.S. Patent No. 5,126,973, issued on June 30, 1992 (Ex. 1006,
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`“Gallia”).
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`2
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`Patent 5,894,441
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`E.
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`The Asserted Grounds of Unpatentability
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`Petitioner asserts the following grounds of unpatentability (Pet. 4):
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`Challenged Claims
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`Basis
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`Reference(s)
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`6–12, 14, and 15
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`§ 102(b) Horiguchi
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`6, 7, 9, 11, 12, 14, and 15
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`§ 102(b) Gallia
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`8 and 10
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`§ 103(a) Gallia and Horiguchi
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`Petitioner supports its challenge with a declaration executed by
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`Dr. Pinaki Mazumder on August 12, 2016 (Ex. 1001).
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`F.
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`The ’441 Patent
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`The ʼ441 Patent is directed to a “SEMICONDUCTOR MEMORY
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`DEVICE WITH REDUNDANCY CIRCUIT.” Ex. 1003, [54]. The
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`’441 Patent explains:
`
`The semiconductor memory device according to this
`invention comprises a plurality of column selection lines, at least
`one redundant column selection line, a column decoder which
`activates one line out of the plurality of column selection lines in
`response to a column address, a first circuit which generates a
`detection signal when the column address of a defect-related
`column selection line is supplied, and a second circuit which
`receives at least a part of a row address and activates the
`redundant column selection line in response to at least a part of
`the row address and the detection signal. With this arrangement,
`when a defect occurs in one bit, instead of replacing all of the
`many bit lines included in the column selection line to which the
`defective bit line belongs, it is possible to relieve a larger number
`of defective bit lines using a single redundant column selection
`line by replacing only a part of these bit lines.
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`Id. at 2:13–28.
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`3
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`Patent 5,894,441
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`G.
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`Illustrative Claim
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`Claim 6 is the only independent claim challenged in this proceeding.
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`Claims 7–12, 14, and 15 depend, directly or indirectly, from claim 6.
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`Independent claim 6 is illustrative of the claimed subject matter and is
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`reproduced below.
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`6.
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`A semiconductor memory device comprising:
`a plurality of word lines including at least first and second
`word lines;
`a plurality of bit lines including at least first and second bit
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`lines;
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`a plurality of redundant bit lines including at least first and
`second redundant bit lines;
`a plurality of memory cells each of which is disposed on
`intersections of said word lines and bit lines;
`a plurality of redundant memory cells each of which is
`disposed on intersections of said word lines and redundant bit
`lines;
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`a plurality of column selection lines including at least a
`first column selection line; said first and second bit lines being
`selected when said first column selection line is activated;
`a redundant column selection line; said first and second
`redundant bit lines being selected when said redundant column
`selection line is activated;
`a column decoder activating said first column selection
`line in response to a first column address when said first word
`line is activated; and
`a column redundancy decoder activating said redundant
`column selection line in response to said first column address
`when said second word line is activated.
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`Ex. 1003, 13:55–14:13.
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`II.
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`CLAIM CONSTRUCTION
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`A.
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`Legal Standard
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`Petitioner contends “[t]he claim terms of the ’441 patent should be
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`construed to have their plain and ordinary meaning in view of the
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`Patent 5,894,441
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`specification.” Pet. 5. Petitioner does not propose that we construe any
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`specific claim terms. Id. at 4–5. Patent Owner responds that it “agrees for
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`purposes of this preliminary response that no construction is necessary to
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`analyze whether trial should be instituted.” Prelim. Resp. 25.
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`Only terms that are in controversy need to be construed, and only to
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`the extent necessary to resolve the controversy. Wellman, Inc. v. Eastman
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`Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs., Inc. v. Am.
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`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). We determine that
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`no express construction of a claim term is needed to resolve a dispute in this
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`proceeding.
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`III. ANALYSIS
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`A.
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`Independent Claim 6
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`Petitioner asserts that claim 6 is anticipated by either Horiguchi or
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`Gallia. Pet. 26–36, 51–62. The Petition includes discussion identifying
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`where each of Horiguchi and Gallia allegedly describes the elements of
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`claim 6. Id.
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`1.
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`Principles of Law
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`Anticipation, under 35 U.S.C. § 102, requires a lack of novelty.
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`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
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`2001). To establish anticipation, each and every element in a claim,
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`arranged as is recited in the claim, must be found in a single prior art
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`reference. Id.
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`2.
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`Horiguchi
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`Horiguchi is directed to a semiconductor memory and in particular to
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`“a technique for repairing a semiconductor memory in such a manner that
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`5
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`defective memory cells are replaced by spare memory cells.” Ex. 1005, 1:9–
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`13. Horiguchi discloses that
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`FIG. 26 shows the eighth embodiment of a semiconductor
`memory according to the present invention. The present
`embodiment is different from the embodiments of FIGS. 21 and
`23 in that a memory array is divided into a plurality of memory
`mats (in the figure, four memory mats 130 to 133) in a direction
`parallel to bit lines. Each memory mat includes a region 140,
`141, 142, or 143 where regular memory cells are arranged, and a
`region 150, 151, 152, or 153 where spare memory cells are
`arranged.
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`Id. at 21:52–61.
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`3.
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`Gallia
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`Gallia is directed to a semiconductor memory device and in particular
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`to “devices which include repair circuitry for eliminating defects in memory
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`devices.” Ex. 1005, 1:5–8. Gallia explains that “each data block 12 is
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`partitioned into sixteen sub-blocks 14.” Id. at 4:52–53.1 Gallia further
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`explains:
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`Within each sub-block 14, there are 256 row or word
`lines R and 256 column select lines Ys. For simplicity of
`illustration, only one row line R and one column select line Ys
`are shown in FIGS. 2 and 3. A row line is selectable based on
`row address information input to a one of sixteen row decoder
`stage 16 and a one of 256 row decoder stage 18 (See FIG. 2).
`There are 16 of the one of 256 stages 18, one for each sub-block
`14. In each data block 12, column address decoders 20 turn on a
`select line Ys to control read/-write data transfer for two columns.
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`Id. at 5:10–20.
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`1 Boldface omitted from reference numerals in patents throughout.
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`4.
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`Asserted Anticipation by Horiguchi
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`For the reasons set forth below, applying the standard set forth in
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`35 U.S.C. § 314(a), we are not persuaded that Petitioner has demonstrated a
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`reasonable likelihood that it would prevail is showing that claim 6 is
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`anticipated by Horiguchi. Regarding “a plurality of column selection lines
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`including at least a first column selection line; said first and second bit lines
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`being selected when said first column selection line is activated” recited in
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`claim 6, Petitioner provides the following annotations to Figure 26 of
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`Horiguchi.
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`
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`Figure 26 illustrates a circuit diagram of a
`semiconductor device with annotations.
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`Petitioner’s annotations include two horizontal lines in pink with the
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`following notations “First column selection line Ys[0],” and “Second
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`column selection line Ys[1],” respectively. Pet. 30. Petitioner contends:
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`Horiguchi discloses “[a]n output YS[j] of the Y-decoder is
`applied to each memory mat through a wiring conductor which
`is indicated by a dot-dash line in FIG. 26.” Ex. 1005, 22:7-10.
`Fig. 26 shows column selection lines YS[j] running horizontally
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`through all of the sub-arrays 130-133. For each value of “j”,
`column selection line YS[j] selects bit line B[j,n] in each of the
`sub-arrays. Ex. 1005, 22:8–10. Ex. 1001, ¶ 152.
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`Id.
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`Patent Owner contends that the “annotated reproduction of FIG. 26
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`. . . includes pink lines added by the Petition,” but “the Petition offers no
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`support whatsoever for the idea that there exists multiple column selection
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`lines YS[0] and YS[1] in Horiguchi.” Prelim. Resp. 42. Patent Owner also
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`contends that “[t]he Petition cites to a single passage of Horiguchi to support
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`this claim limitation, which recites ‘[a]n output YS[j] of the Y-decoder is
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`applied to each memory mat through a wiring conduction which is indicated
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`by a dot-dash line in FIG. 26.’” Id. at 41.
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`We find that Petitioner does not offer sufficient, persuasive evidence
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`for its contention that “Fig. 26 shows column selection lines YS[j] running
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`horizontally through all of the sub-arrays 130-133” (Pet. 30). Comparing
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`Petitioner’s annotated Figure 26 (Pet. 30) and Figure 26 without annotations
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`reveals that, although the first of the pink lines added by Petitioner
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`corresponds to YS(j) in Horiguchi, the second of the pink lines does not
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`have a corresponding column selection line YS in Figure 26.
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`Additionally, Petitioner’s citation to Horiguchi’s description of
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`Figure 26 (see Pet. 30 (citing Ex. 1005, 22:7–10)) does not support
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`Petitioner’s argument that Horiguchi discloses multiple column selection
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`lines. That portion, as well as the immediately preceding sentence, are
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`reproduced below.
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`Circuit blocks 230 to 233 each including sense amplifiers
`and input-output lines are provided so as to correspond to the
`memory maps 130 to 133, respectively. However, only a single
`Y-decoder 40 is provided in an end portion. An output YS[j] of
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`the Y-decoder is applied to each memory mat through a wiring
`conductor which is indicated by a dot-dash line in FIG. 26.
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`Ex. 1005, 22:3–10 (emphasis added). The emphasized language above is
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`consistent with the illustration of only a single output in Figure 26.
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`Furthermore, Horiguchi’s description of failure of the decoder
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`circuitry also is consistent. In particular, Horiguchi describes the “plurality
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`of memory mats use one Y-decoder in common” (id. at 22:15–16) and
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`“where the Y-decoder is defective” the address signals “are not compared
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`with any data” resulting in the “corresponding bit lines in four memory mats
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`are simultaneously replaced by spare bit lines” (id. at 22:38–42). The expert
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`testimony cited by Petitioner (Pet. 30 (citing Ex. 1001 ¶ 152)) does not offer
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`additional persuasive supporting evidence.
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`Based on the record before us, we are not persuaded that Petitioner
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`has shown sufficiently that Horiguchi discloses “a plurality of column
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`selection lines including at least a first column selection line; said first and
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`second bit lines being selected when said first column selection line is
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`activated,” as recited in claim 6. Accordingly, we determine that Petitioner
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`has not shown a reasonable likelihood that it would prevail in establishing
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`that claim 6 is anticipated by Horiguchi.
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`5.
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`Asserted Anticipation by Gallia
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`For the reasons set forth below, we exercise our discretion under
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`35 U.S.C. § 325(d) to deny institution of review on the basis of anticipation
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`of claim 6 by Gallia. Petitioner acknowledges that on October 27, 2015,
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`Micron Technology, Inc. filed a petition challenging claim 6, as well as
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`other claims, of the ’441 Patent on the basis of obviousness over U.S. Patent
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`No. 5,270,975 (Ex. 1008, “McAdams”) and Japanese Patent Appl. No. H06-
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`052696 (“Minami”). Pet. 11 (citing Ex. 1007). As Petitioner further
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`acknowledges, that inter partes review was not instituted. See Micron Tech.,
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`Inc. v. Limestone Memory Sys. LLC, Case IPR2016-00094, Paper 8
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`(submitted in the instant case as Ex. 1011). As relevant here, Gallia and
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`McAdams share essentially the same disclosure.
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`Patent Owner contends:
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`In sum, the Petition suffers much the same problem as the
`‘094 petition, which the Board held did not adequately show that
`this claim limitation was satisfied by the identical McAdams
`disclosure. (See Ex. 1011 at 8–10.) Indeed, the ‘094 petition
`conceded that “[w]hat McAdams does not explicitly disclose is
`whether activating the column redundancy decoder occurs when
`a word line is activated.” (Ex. 1011 at 11; Ex. 1007 at 52.) The
`instant Petition has not offered any evidence to suggest that the
`‘094 petition was wrong on that point.
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`Prelim. Resp. 49.
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`Consistent with Patent Owner’s contentions, according to the Petition
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`filed in the earlier proceeding (Ex. 1007, “the ’094 Petition”), McAdams
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`does not disclose that the column decoder activates the first column selection
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`line when the word line is activated. Ex. 1007, 48. Furthermore, the
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`’094 Petition relied on, as supporting evidence, a declaration executed by
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`Dr. R. Jacob Baker on October 22, 2015. See IPR2016-00094, Paper 1; Ex.
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`1003. Consistent with Patent Owner’s contentions in the instant proceeding
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`(Prelim Resp. 49), in the earlier proceeding, Dr. Baker testified “[w]hat is
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`not expressly disclosed in McAdams is that the column decoder activates the
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`first column selection line in response to a first column address when said
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`word line is activated.” See IPR2016-00094, Ex. 1003, A-38.
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`We turn to the limitation conceded in the ’094 Petition, i.e., “a column
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`decoder activating said first column selection line in response to a first
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`column address when said first word line is activated” recited in claim 6. In
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`the instant proceeding, Petitioner provides the following contentions for this
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`limitation:
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`Gallia describes that when a non-defective memory
`location memory is accessed, e.g., at a first row and first column
`address, address decoding is performed as follows: the first row
`decoder stage 16 decodes the least significant four bits of the row
`address to determine which of the 16 sub-arrays is being
`accessed. Then, a second row decoder stage 18 decodes the
`upper 8 bits of the row address to determine which of the 256
`rows is being accessed, and activates the corresponding word
`line R (i.e., first word line). Finally, column decoder 20 decodes
`an 8-bit column address (i.e., first column address) to activate a
`column selection line YS. Ex. 1006, 5:56-66; Fig. 2; Ex. 1001,
`¶ 209.
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`Pet. 60–61 (emphases added).
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`The emphasized language above in Petitioner’s contention suggests
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`that the timing of events is staggered, i.e., “[t]hen” a second row stage
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`decodes and “[f]inally” the column decoder decodes. Id. Additionally, the
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`portion of Gallia identified in the Petition (Pet. 61 (citing Ex. 1006, 5:56–
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`66)) describes “first row decoder stage 16” and “second row decoder
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`stage 18” (Ex. 1006, 5:58–60 (emphases added)).
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`Consistent with Patent Owner’s contentions (Prelim. Resp. 8–16),
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`with respect to the disclosures relied upon by Petitioner, Gallia and
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`McAdams share substantially the same disclosures. Compare, e.g.,
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`Ex. 1006, Figs. 1–3, 5, with Ex. 1008, Figs. 1–3, 5. With respect to the only
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`disclosure Petitioner relies on in Gallia for the requirement that the column
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`decoder activate the first column selection line “when said first word line is
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`activated” (Pet. 60–61 (citing Ex. 1006, 5:17–20, 5:56–66, Figs. 1, 2)), the
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`corresponding disclosure of McAdams is the same as that in Gallia.
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`Compare Ex. 1006, 5:17–20, 5:56–66, Figs. 1, 2, with Ex. 1008, 5:38–46,
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`6:10–30, Figs. 1, 2. The expert testimony cited by Petitioner (Pet. 61 (citing
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`Ex. 1001 ¶ 209)) is substantially the same as the argument presented in the
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`Petition and does not offer additional persuasive supporting evidence.
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`In determining whether to institute inter partes review, we may “deny
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`some or all grounds for unpatentability for some or all of the challenged
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`claims.” 37 C.F.R. § 42.108(b); see 35 U.S.C. § 314(a). Our discretionary
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`determination of whether to institute review is guided by 35 U.S.C. § 325(d),
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`which states, in relevant part, that “[i]n determining whether to institute or
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`order a proceeding under this chapter, chapter 30, or chapter 31, the Director
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`may take into account whether, and reject the petition or request because, the
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`same or substantially the same prior art or arguments previously were
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`presented to the Office (emphasis added).”
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`In the instant proceeding, Petitioner does not identify new arguments
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`based on additional references in combination with Gallia. Also, Petitioner
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`does not make persuasive assertions that differentiate its Petition from the
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`’094 Petition, or explain sufficiently why Gallia, which is substantially the
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`same prior art as that previously presented, does not have the earlier-noted
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`deficiency. Accordingly, we exercise our discretion under 35 U.S.C.
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`§ 325(d) to deny institution of review on the basis of anticipation of claim 6
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`by Gallia.
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`B.
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`Claims 7–12, 14, and 15
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`Petitioner asserts that claims 7, 9, 11, 12, 14, and 15 are anticipated by
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`each of Horiguchi and Gallia. Pet. 4. Petitioner also asserts that claims 8
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`and 10 are anticipated by Horiguchi or obvious over Horiguchi and Gallia.
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`Id. Each of claims 7–12, 14, and 15 depends, directly or indirectly, from
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`independent claim 6. Petitioner’s challenges do not remedy the deficiencies
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`noted above for independent claim 6. Accordingly, we decline to institute
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`review of any of claims 7–12, 14, and 15 of the ’441 Patent for the reasons
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`set forth above.
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`For the foregoing reasons, it is:
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`IV. ORDER
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`ORDERED that the Petition is denied and no inter partes review is
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`instituted.
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`PETITIONER:
`
`John R. Hutchins
`ANDREWS KURTH KENYON LLP
`jhutchins@kenyon.com
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`PATENT OWNER:
`
`Nicholas T. Peters
`Paul Henkelmann
`FITCH EVEN TABIN & FLANNERY LLP
`ntpete@fitcheven.com
`phenkelmann@fitcheven.com
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