PINAKI MAZUMDER1
`
`Room Number: 4765, Computer Science and Engineering Building, Department of Electrical Engineering
`and Computer Science, 2260 Hayward Avenue, University of Michigan, Ann Arbor, MI 48109-2121.
`Phone: 734-763-2107 (Office), and Fax: 734-763-8094. E-Mail: mazum@eecs.umich.edu
`
`Please see Mazumder’s homepage at http://www.eecs.umich.edu/~mazum
`
`Immigration Status: US Citizen since 1995.
`
`I. Educational Qualification
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`Ph.D. in Computer Engineering
`M. Sc. in Computer Science
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`B.S. in Electrical Engineering
`
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`University of Illinois, Urbana-Champaign
`University of Alberta, Edmonton, Canada
`Indian Institute of Science, Bangalore, India
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`
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`1988
`1985
`1976
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` I
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` also received a degree in B.Sc. Physics Honors securing the first rank in Gauhati University, India amongst
`estimated 100,000 students in all disciplines of liberal arts and basic sciences.
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`II. Work Experience
`
`US Government (National Science Foundation):
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`2007-2008
`
`Program Director for Emerging Models and Technologies Program (funding areas:
`Nanoelectronics, Quantum Computing, and Biologically Inspired Computing with
`an annual budget of $18 Million) in the Directorate for Computer and Information
`and Science and Engineering, National Science Foundation, Arlington, Virginia.
`
`
`2009
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`1996-1997
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`1996-1997
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`1997
`1992-1998
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`Academic Teaching and Research:
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`1998- to date
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`Program Director in Electrical, Communications and Cyber Systems Division
`(funding areas: Quantum, Molecular and High Performance Computing, Adaptive
`Intelligent Systems, Electronic and Photonic Devices, and Major Research
`Instrumentation) of the Engineering Directorate at National Science Foundation.
`
`Tenured Professor, Division of Computer Science and Engineering, Department of
`Electrical Engineering and Computer Science, University of Michigan, Ann Arbor,
`USA.
`Research Fellow, Division of Electrical and Computer Engineering, Department of
`Electrical Engineering and Computer Science, University of California, Berkeley,
`USA.
`Visiting Associate Professor, Department of Computer Science and Engineering,
`Stanford University, Palo Alto, California, USA.
`Visiting Professor, NTT Research Laboratories, Atsugi-shi, Japan.
`Tenured Associate Professor, Division of Computer Science and Engineering,
`Department of Electrical Engineering and Computer Science, University of
`Michigan, Ann Arbor, USA.
`
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`1 Fellow of AAAS, Fellow of IEEE, Member of Sigma Xi, and Member of Phi Kappa Phi
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`Apple – Ex. 1002
`Apple Inc., Petitioner
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`1987-1992
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`Assistant Professor, Division of Computer Science and Engineering,
`Department of Electrical Engineering and Computer Science, University
`of Michigan, Ann Arbor, USA.
`Research Assistant, University of Illinois at Urbana-Champaign, USA.
`Teaching Assistant at University of Alberta, Edmonton, Canada.
`Research Assistant at Indian Institute of Science, Bangalore, India.
`
`Member of Technical Staff, AT&T Bell Laboratories, Indian Hill, Chicago.
`Senior R&D Engineer, Bharat Electronics Ltd., Bangalore, India.
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`1985-1987
`1982-1984
`1974-1975
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`Industrial Research and Development:
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`1985, 1986
`1976-1982
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`III. Major Fields of Research
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`1) VLSI design, testing and layout automation; 2) Nanoelectronics and nanomagnetics: multiscale
`modeling, simulation tools, circuits and architectures; 3) Terahertz technology and applications in signal
`processing, computing and communications.
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`IV. Awards and Recognitions
`
`
`• Fellow of American Association for the Advancement in Science (AAAS), 2007 for
`“distinguished contributions to the field of very large scale integrated (VLSI) systems”. The
`honor of being elected a Fellow of AAAS is given to those whose “efforts on behalf of the
`advancement of science or its applications are scientifically or socially distinguished.”
`• Fellow of IEEE, 1999 for “contributions to the field of VLSI Design.”
`•
`IEEE Distinguished Lecturer
`• Digital Equipment Corporation Faculty Award: Excellence in Research
`• Departmental Research Excellence Award (1995), The University of Michigan
`• BF Goodrich National Collegiate Invention Award
`• DARPA Research Excellence Award for the work in Quantum MOS Project
`• Best Undergraduate Student Medal
`•
`IETE Best Student Paper Award, and IETE Best Paper Presentation Award
`• NSF Research Initiation Award
`• Bell Northern Research Laboratory Faculty Development Grant
`• Commendation Letter from the Dean of College of Engineering, University of Michigan, for
`Excellence in Teaching
`• Member, Sigma Xi
`• Member, Phi Kappa Phi
`
`
`V. Research Funding
`
`
`1. National Science Foundation (RIA): $69,948; 1988 – 1991 (Single PI)
`2. Bell Northern Research Laboratory: $20,900; 1988 – 1989 (Single PI)
`3. National Science Foundation: $90,620; 1989 – 1990 (Single PI)
`4. Digital Equipment Corporation: $180,000; 1989 – 1992 (Single PI)
`5. Office of Naval Research: $420,000; 1988 - 1991, (Co-PI)
`6. National Science Foundation: $125,000; 1991 – 1993 (Single PI)
`7. Rackham Faculty Research Grant: $9,980; 1991 – 1993 (Single PI)
`8. U.R.I. Program (US Army): $6,000,000 (total); $250,000 (my portion); 1988 - 1992
`9. General Motors: $20,000; 1992 – 1992 (Single PI)
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`10. International Business Machines: $45,000 (student fellowship); 1990 – 1993
`11. National Science Foundation: $47,000; 1992 – 1993 (Single PI)
`12. Hewlett Packard: $81,400; 1993 – 1995 (Single PI)
`13. Office of Vice President Research: $52,300; 1995 - 1996
`14. Defense Advanced Research Projects Agency (DARPA): $825,000; 1993 -1997 (Co-PI)
`15. National Science Foundation: $182,400; 1994 – 1998 (Single PI)
`16. U.R.I. Program (US Army): $5,000,000; $200,000; 1993 - 1997
`17. State of Michigan Display Technology Center: $2,000,000; My portion: $200,000; 1995 - 1998
`18. Texas Instruments (subcontract of a DARPA project): $304,000; 1995 – 1998 (Single PI)
`19. Army Research Office’s MURI-95 (Co-PI with 7 others): $4,000,000; 1995-2000 + 1 year.
`20. Army Research Office’s MURI-96 (Co-PI with 13 others): $5,000,000; 1996-2001 + 1 year.
`21. Defense Advanced Research Projects Agency: $750,000; June 1997- May 2000 (PI)
`22. National Science Foundation: $300,000; 1998 – 2002 (Single PI)
`23. Nippon Electric Company, Japan: $40,000; 1998 (Single PI)
`24. National Science Foundation: $195,000; 1998 – 2002 (Single PI)
`25. Hughes Research Laboratory (Office of Naval Research project); $270,000; 1998-2001 (Single
`PI)
`26. NanoLogic Inc. $10,000; 1999-2000 (Single PI)
`27. Air Force Office of Scientific Research: $5,000,000: 2001-2006 (Co-PI with 9 other investigators)
`28. Office of Naval Research: $303,000: 2001-2002; (Single PI)
`29. National Science Foundation: $210,000: 2001-2004 (Single PI)
`30. Korean Government Nanoelectronics Research: $200,000: 2001-2002 (PI: Prof. G.I. Haddad).
`31. Office of Naval Research: $820,000: 2002-2005 (PI)
`32. Tera-Level Nanoelectronics Project, Korean Government: $170,000: 2003-2006; (Single PI)
`33. National Science Foundation: $120,000: 2004-2007 (Single PI)
`34. Air Force Office of Scientific Research, $480,000: 2006-2009 (Single PI)
`35. National Science Foundation IPA Assignment Grant: $620,000; 2007-2009 (Single PI)
`36. DARPA SyNAPSE Program on Brain Plasticity: $807,812; Co-PI: Hughes Research Laboratory
`37. National Science Foundation, NIRT: $1,000,000: 2006-2012 (Co-PI).
`38. SRC NRI Center (MIND): ~$200,000: 2008-2011 (Single PI)
`39. National Science Foundation: EAGER Grant, $200,000; 2009-2012. (Single PI)
`40. National Science Foundation: $400,281; 2010-2014. (Single PI)
`41. Army Research Office: $580,000; 2010-2013. (Single PI)
`42. National Science Foundation: $149,111; 2011-2012. (Single PI)
`43. Army Research Office, MURI: $6,500,000; 2010-2015. (Co-PI)
`44. National Science Foundation: $400,415; 2011-2014. (Single PI)
`45. National Science Foundation: $1,750,000; 2011-2015. (Co-PI)
`46. Defense Advanced Research Projects Agency (DARPA): $150,000; 2011-2013 (Single PI)
`47. Air Force Office of Scientific Research: $449,772; 2012-2015 (Single PI)
`48. National Science Foundation: $480,000; 2012-2015 (Co-PI)
`49. National Science Foundation: $400,000; 2014-2017 (PI)
`50. National Science Foundation: $900,000; 2015-2018 (PI).
`51. Air Force Office of Scientific Research: $150,000; 2016-2017 (Single PI)
`
`Pending Proposals:
`
`1. Engineering Research Center (ERC): Foundation for Integrative Research on Short-range
`Terahertz in Wireless Communication and Signal Processing, National Science Foundation,
`$18,000,000 for 5 years (Mazumder, PI; University of Michigan, Massachusetts Institute of
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`Technology, University of California at Los Angeles, New Jersey Institute of Technology,
`University of Central Florida, and Cornell University).
`2. Nanoarchitectures for Adaptive Control and Intelligence Processing Chips, Office of Naval
`Research, $450,000 (PI)
`3. Ultra-Low-Power Bio-inspired Nanoelectronics for Navigation in Autonomous Insect-Scale
`Robots, Air Force Office of Scientific Research, $790,000 (PI)
`
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`VI. Committees and Professional Activities
`
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`1. Member of Board of Editors, Proceedings of the IEEE
`2. Associate Editor, IEEE Transactions on VLSI Systems, 1997-2000
`3. Guest Editor, IEEE Transactions on VLSI Systems - A Special Issue on Impact of Emerging
`Technologies on VLSI Systems, December 1997
`4. Guest Editor (with Prof. A. Seabaugh), Proceedings of the IEEE - A Special Issue on
`Nanoelectronic Devices and Circuits, June 1998
`5. Guest Editor (with Prof. A. Benso and Prof. Y. Makris), IEEE Transaction on Computer – A
`Special Issue on Architectures for Emerging Technologies and Applications, June 2008
`6. Guest Editor, Journal of Electronic Testing - Theory and Application - A Special Issue on Multi-
`megabit Memory Testing, April 1994
`7. Guest Editor (with Prof. J.P. Hayes), IEEE Design & Test Magazine - A Special Issue on
`Memory Testing, 1993
`8. Editorial Advisory Board, The Arabian Journal for Science and Engineering, King Fahd
`University of Petroleum and Minerals, Saudi Arabia.
`9. Council of Editors, International Society for Genetic and Evolutionary Computation (ISGEC)
`10. As lead NSF Program Director, organized the Emerging Models and Technology Workshop on
`Bio-Inspired Computing and Bio-Computing at Princeton University on July 24-25, 2008.
`11. As lead NSF Program Director, organized the EMT Workshop on Nanoelectronics on October
`29-30, 2007.
`12. As lead NSF Program Director, held the EMT Workshop on Quantum Information Science and
`Engineering on September 10-11, 2007.
`13. Member, University of Michigan Research Policies Committee of Senate Assembly, 2002-05.
`14. Member, Electrical Engineering and Computer Science Curriculum Committee, 2002-03.
`15. Member, Electrical Engineering and Computer Science DCO Committee, 2002-03.
`16. Member, Computer Science and Engineering Graduate Curriculum Committee, 1988-89, 1998-
`00, 2002-06.
`17. Counselor, Computer Engineering Undergraduate Students, 1990-95.
`18. Member, Computer Science and Engineering Graduate Admission Committee, 1995-96.
`19. Member, IEEE Standards Subcommittee for Semiconductor Memories, 1989-90.
`20. Member, IEEE Test Technologies Committee
`21. Member, IEEE VLSI Technical Committee
`22. General Chair, 2007 High Performance Computing (HPC) for Nanotechnology
`23. General Chair, 1999 IEEE Great Lakes VLSI Conference
`24. Program Committee, 1992 Fault-Tolerant Computing Symposium Workshop
`25. Program Committee, 1992 IEEE Defects and Fault Tolerance Workshop
`26. Program Committee, 1993 IEEE Intl. Conference on Memory Testing
`27. Program Committee, 1994 IEEE Intl. Conference on Memory Testing
`28. Program Committee, 1994 IEEE Asian Testing Symposium
`29. Program Committee, 2000 IEEE Great Lakes VLSI Conference
`30. Serving on organizing committee for Department of Defense Nano Conference, 2009
`31. Served regularly on NSF panels in Engineering and CISE Directorates
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`32. Proposals Reviewed for: US National Science Foundation, The Israel Science Foundation,
`Louisiana University Board of Regents, and US Army Research Office, New Jersey Center for
`Science and Technology, Saudi Arabia King Fahd University Research Foundation, and private
`venture capitalist firms.
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`VII. Professional Experience
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`Details of My Professional Accomplishments
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`US Government at National Science Foundation (3 years)
`
`
`In 2007 and 2008, I worked as the lead Program Director for Emerging Models and Technologies
`(EMT) program in the Division of Computing and Communication Foundations (having nearly $140
`Million annual budget) of the Directorate for Computer and Information and Science and Engineering,
`National Science Foundation, Arlington, Virginia. My mandate was to manage research grants in
`Nanoelectronic Modeling and Systems, Quantum Computing, and Biologically Inspired Computing for
`which I had an operating annual budget of about $18 Million. Additionally, I participated in several NSF
`crosscutting programs such as Cyber-Enabled Discovery and Innovation (CDI), Expeditions in
`Computing, Major Research Instrumentation (MRI), Computing Research Infrastructure (CRI) and Cyber
`Physical Systems (CPS). In 2009, I worked as a Program Director in the Engineering Directorate where I
`managed research in three broad areas: Adaptive Intelligent Systems (Machine Learning), Quantum,
`Molecular and High-Performance Modeling, and Electronic and Photonic Devices. During these three
`years, I interacted with several program managers and administrators of NSF, DARPA, ARO, ONR, and
`AFOSR to help launch national-level major research initiatives. I consider that serving the US
`government for a stint of three years has provided me an exceptional opportunity to acquire a vast amount
`of knowledge in various fields of science and engineering, to network with numerous researchers around
`the nation, and to gain divergent administrative experience.
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`Teaching Experience (29 years)
`
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`Since 1988, I have been teaching at the Department of Electrical Engineering and Computer
`Science of the University of Michigan, Ann Arbor, Michigan.
`
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`Graduate courses developed and taught: 1) VLSI System Design, 2) Optimization and Synthesis
`of VLSI Layout, 3) Testing of Digital Circuits and Systems, 4) Advanced Computer Architectures, 5)
`Nanocircuits and Nanoarchitectures, 6) Ultra-Low-Power Subthreshold CMOS Circuits, and 7) Terahertz
`Technology and Applications.
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`Undergraduate courses upgraded and taught: 1) Introduction to Digital Logic Design
`(sophomore level), 2) Digital Integrated Circuit Design (junior level), and 3) VLSI System Design (senior
`level).
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`Industrial Experience (6.5 years)
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`After my baccalaureate degrees in Physics and Electrical Engineering, I worked for six years
`(1976-1982) as a Senior R&D Engineer at Bharat Electronics Ltd. (BEL) in its Integrated Circuits
`Division. I designed several bipolar and CMOS analog and digital integrated circuits for consumer
`electronic systems. I was associated with the following chip development projects: i) Raster-scan
`vertical deflection system microchip for TV display, ii) Sync processing and horizontal deflection system
`microchip for TV display, iii) Video and audio IF stage IC’s for vestigial-AM and FM signal detection in
`TV receiver, iv) High-gain audio amplifier microchip for TV audio stage, v) Tape Recorder IC with
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`automatic gain adjustments, vi) Hearing-aid IC, vii) Analog clock driver IC, and viii) LCD and AC
`Plasma display drive IC’s. Several million commercial chips were fabricated based on these designs.
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`After finishing my MSc degree in Computer Science and while working towards my PhD degree
`in Electrical and Computer Engineering, I worked during the summers of 1985 and 1986 as a Member of
`Technical Staff at AT&T Bell Laboratories. I was one of the two engineers who started the Bell
`Laboratory Cones/Spruce project - a new behavioral synthesis and layout automation tool for rapid
`prototyping of digital circuits. The main contribution of this effort was to demonstrate how a restricted
`version of C language could be used to model digital hardware much before commercial hardware
`description language (HDL) software tools like Verilog and System C were designed.
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`Research Accomplishments:
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`
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`In 1984, when I started my MS thesis at University of Alberta in the field of VLSI, I was inspired
`by the local (Edmonton, Canada) hockey legend, Wayne Gretzky whose famous quote (“A good hockey
`player plays where the puck is. A great hockey player plays where the puck is going to be”) defined the
`compass of my research work for the next 28 years as explained below. In Evolutionary CMOS research,
`I solved numerous use-inspired research problems that were 10 to15 years ahead of their time and
`eventually Moore’s Law has vindicated the practical merits of my research by impacting the memory and
`FPGA industry as pointed out below. In Revolutionary emerging technologies such as quantum tunneling
`devices, THz plasmonic devices (in THz regime), ionic devices (as non-volatile memories), and electron
`spin based devices (as ultra-low-power nonvolatile memories) I have made sustained impact for the past
`23 years by collaborating with multiple leading researchers in universities and companies. In my research
`career, I have endeavored to emulate the Vannevar Bush model of triad synergy between University,
`Industry and Government establishments that was conceived at the aftermath of the Second World War to
`challenge academics to undertake enterprising and leadership role for catalyzing innovations, accelerated
`economic growth, and sustained US leadership in science and engineering.
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`VIII. Publications
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`Summary of Significant Publications
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`Books: 9; Journal Publications: 105; Reviewed Conference Papers: 179; Book Chapters: 6; US
`Patents: 12.
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`A. Books
`
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`1. P. Mazumder and K. Chakraborty, “Testing and Testable Design of Random-Access Memories”,
`Kluwer Academic Publishers, 1996 (428 pages).
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`2. P. Mazumder and E. Rudnick, “Genetic Algorithms for VLSI Layout and Test Automation”,
`Prentice Hall, 1999 (460 pages).
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`3. K. Chakraborty and P. Mazumder, ”Fault Tolerance and Reliability Aspects of Random-Access
`Memories,” Prentice Hall, 2002. (440 pages).
`
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`4. P. Mazumder, “Introduction to Digital Systems”, Video Book on DVD, produced at MGM Studio
`(Orlando, Florida), Laureate Education, Inc., 2005.
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`5. P. Mazumder, “Models and Techniques for VLSI Routing”, Springer Verlag, (under preparation)
`
`6. R. Rajasuman (Editor) and P. Mazumder (Editor), “Semiconductor Memories: Testing and
`Reliability”, Computer Science Press, May 1998.
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`7. R. J. Lomax (Editor) and P. Mazumder (Editor), “Great Lakes Symposium on VLSI, 1999”,
`Computer Science Press, March 1999.
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`8. P. Mazumder, “Principle of Digital Logic Design”, Pan Stanford Publishing, 2017.
`
`9. P. Mazumder and K. Shahookar, “MathGuru Tutorial” for K-12 Education Software.
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`B. Reviewed Journal Publications
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`EVOLUTIONARY TECHNOLGY (CMOS)
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`CMOS MEMORY TESTING & RELIABILITY
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`10. P. Mazumder, J. H. Patel and W. K. Fuchs, “Methodologies for Testing Embedded Content-
`Addressable Memories”, IEEE Transactions on Computer-Aided Design of Integrated Circuits
`and Systems, Jan. 1988, pp. 11-20.
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`11. P. Mazumder, “Parallel Testing of Parametric Faults in a Three-Dimensional Dynamic Random-
`Access Memory”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 4, Aug. 1988, pp. 933-942.
`
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`12. P. Mazumder and J. H. Patel, “Parallel Testing of Pattern-Sensitive Faults in Random-Access
`Memory”, IEEE Transactions on Computers, Vol. 38, No 3, Mar. 1989, pp. 394-404.
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`13. P. Mazumder and J. H. Patel, “An Efficient Built-In Self-Testing Algorithm for Random-Access
`Memory”, IEEE Transactions on Industrial Electronics (Special Issue on Testing) Vol. 36, No. 3,
`May 1989, pp. 394-407.
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`14. J. S. Yih and P. Mazumder, “Circuit Behavior Modeling and Compact Testing Performance
`Evaluation”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, Jan. 1991, pp. 62-65.
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`15. P. Mazumder and J. H. Patel, “A Comprehensive Study of Random Testing for Embedded RAM’s
`Using Markov Chains”, Journal of Electronic Testing: Theory and Applications, Vol. 3 No. 4, Nov.
`1992, 235-250.
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`16. S. Mohan and P. Mazumder, “Analytical and Simulation Studies of Failure Modes in SRAM’s
`Using High-Electron Mobility Transistors”, IEEE Transactions on Computer-Aided Design of
`Integrated Circuits and Systems, Vol. 12, No. 12, Dec. 1993, pp. 1885-1896.
`
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`17. P. Mazumder and J. P. Hayes, “Testing and Improving the Testability of Multi-megabit Memories”,
`IEEE Design and Test of Computers, Mar. 1993, pp. 6-7.
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`18. K. Chakraborty and P. Mazumder, “Technology and Layout Related Testing in Static Random-
`Access Memories”, Journal of Electronic Testing: Theory and Applications, Aug. 1994.
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`19. P. Mazumder, J. H. Patel and J. A. Abraham, “A Reconfigurable Parallel Signature Analyzer for
`Concurrent Error Correction in Dynamic Random-Access Memory”, IEEE Journal of Solid-State
`Circuits, Vol. 25, No. 3, Jun. 1990, pp. 866-870.
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`20. P. Mazumder and J. Yih, “Restructuring of Square Processor Arrays by Built-in Self-Repair
`Circuit,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
`12, No. 9, Sept. 1993, pp. 1255-1265.
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`21. P. Mazumder, “A New On-Chip ECC Circuit for Correcting Soft Errors in DRAM’s with Trench
`Capacitors,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, Nov. 1992, pp. 1623-1633.
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`22. R. Venkateswaran, P. Mazumder and K. G. Shin, “On Restructuring of Hexagonal Arrays,” IEEE
`Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 12, Dec.
`1992, pp. 1574-1585.
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`23. P. Mazumder and J. Yih, “A New Built-in Self-Repair Approach to VLSI Memory Yield
`Enhancement by Using Neural-Type Circuits,” IEEE Transactions on Computer-Aided Design of
`Integrated Circuits and Systems, Vol. 12, No. 1, Jan. 1993, pp. 124-136.
`
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`24. P. Mazumder, “Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory
`with On-Chip Error-Correcting Circuit,” IEEE Transactions on Computers, Vol. 42, No. 12, Dec.
`1993, pp. 1453-1468.
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`25. M.D. Smith and P. Mazumder, “Analysis and Design of Hopfield-type Network for Built-in Self-
`Repair of Memories,” IEEE Transactions on Computers, Vol. 45, No. 1, Jan. 1996, pp. 109-115.
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`26. K. Chakraborty and P. Mazumder, “New March Tests for Multi-port RAM Devices,” JETTA:
`Journal on Electronic Testing: Theory and Applications, Vol. 16, No. 4, Aug. 2000, pp. 389-396.
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`27. A. F. Gonzalez, M. Bhattacharya, S. Kulkarni, and P. Mazumder, ”CMOS Implementation of a
`Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices,”
`IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, June 2001, pp. 924-932.
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`CMOS VLSI LAYOUT AUTOMATION
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`28. K. Shahookar and P. Mazumder, “A Genetic Approach to Standard Cell Placement with Meta-
`Genetic Parameter Optimization,” IEEE Transactions on Computer-Aided Design of Integrated
`Circuits and Systems, Vol. 9, No. 5, May 1990, pp. 500-511.
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`29. R. Venkateswaran and P. Mazumder, “Hexagonal Array Machine for Multi-Layer Wire Routing,”
`IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 10,
`Oct. 1990, pp. 1096-1112.
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`30. J. Yih and P. Mazumder, “A Neural Network Design for Circuit Partitioning,” IEEE Transactions
`on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 12, Dec. 1990, pp.
`1265-1271.
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`31. K. Shahookar and P. Mazumder, “VLSI Cell Placement Techniques,” ACM Computing Surveys,
`Vol. 23, No. 2, June 1991, pp. 143-220.
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`32. K. Shahookar and P. Mazumder, Japanese translation of VLSI Cell Placement Techniques, Bit:
`Computer Science ‘91, Kyoritsu Shuppan Co., Ltd., Tokyo, Japan, 1991.
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`33. P. Mazumder, “Decomposition Strategies for Quad-tree Data Structure,” Journal of Computer
`Vision, Graphics, and Image Processing, Academic Press, June 1987, pp. 258-274.
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`34. H. M. Chan, P. Mazumder and K. Shahookar, “Macro-Cell and Module Placement by Genetic
`Optimization with Bit-Map Represented Crossover Operators,” Integration, the International VLSI
`Journal, Dec. 1991, pp. 49-77.
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`35. P. Mazumder, “Layout Optimization for Yield Enhancement in On-Chip VLSI/WSI Parallel
`Processing,” IEE Proceedings-E: Computers and Digital Techniques. Vol. 139, No. 1, Jan. 1992,
`pp. 21-28.
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`36. S. Mohan and P. Mazumder, “WOLVERINES: A Distributed Standard Cell Placement Tool,” IEEE
`Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 9, Sept.
`1993, pp. 1312-1326.
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`37. K. Shahookar, W. Khamisani, P. Mazumder, S.M. Reddy, “Genetic Beam Search for Gate Matrix
`Placement,” IEE Proceedings-E: Computers and Digital Techniques, Vol. 141, No. 2, Mar. 1994,
`pp. 123-128.
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`38. R. Venkateswaran and P. Mazumder, “DA Techniques for PLD and FPGA Based Systems,”
`Integration, the International VLSI Journal, Vol. 17, Dec. 1994, pp. 191-240.
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`39. R. Venkateswaran and P. Mazumder, “CHiRPS: A General-area Parallel Multi-layer Routing
`System,” IEE Proceedings-E: Computers and Digital Techniques, Vol. 142, No. 3, May 1995, pp.
`208-214.
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`40. P. Mazumder and J. Tartar, “Planar Topologies for Tree Representation,” Congressus
`Numerantium, Vol. 46, May 1985, pp. 173-186.
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`41. H. Esbensen and P. Mazumder, “Viking: Macro-cell Placement by Genetic Algorithm,” IEE
`Proceedings-E: Computers and Digital Techniques.
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`CMOS VLSI SYSTEM DESIGN ISSUES
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`42. L. Ding, D. Blaauw and P. Mazumder, ”Accurate Estimation of Crosstalk Using Effective Coupling
`Capacitance,” IEEE Transactions on Computer-Aided Design of Integrated Systems, Vol. 22,
`No.5, May 2003, pp.627-634.
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`43. Q.W. Xu, Z. Li, P. Mazumder and J. Mao, “Time-domain Modeling of High-speed Interconnects by
`Modified Method of Characteristics,” IEEE Transactions on Microwave Theory and Techniques,
`Vol. 48, No. 2, Feb. 2000, pp. 323-327.
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`44. Q.W. Xu and P. Mazumder, ”Modeling of Lossy Multiconductor Transmission Lines,” IEEE
`Transactions on Microwave Theory and Techniques, Vol. 50, No. 10, pp 2233-2246, Oct. 2002.
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`45. Q.W. Xu and P. Mazumder, “Equivalent-Circuit Interconnect Modeling Based on the Fifth-Order
`Differential Quadrature Methods,” IEEE Transactions on VLSI Systems, Vol.11, No.6, Dec. 2003,
`pp.1068-1079.
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`46. K. Chakrabaorty, M. Bhattacharya, S. Kulkarni, A. Gupta and P. Mazumder, “BISRAMGEN: A
`Built-In Self-Repairable SRAM and DRAM Compiler,” IEEE Transactions on VLSI Systems,
`Vol. 9, No. 2, Apr. 2001, pp. 352-364.
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`47. A. Gupta, K. Chakraborty and P. Mazumder, ”FTROM: A Silicon Compiler for Fault-Tolerant
`ROMs, ” Integration, the International VLSI Journal, Vol. 26, No. 1-2, Dec. 1998.
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`48. L. Ding and P. Mazumder, ”Simultaneous Switching Noise Analysis Using Application Specific
`Device Modeling,” IEEE Transactions on VLSI Systems. Vol.11, No.6, Dec.2003, pp.1146-1152.
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`49. A. F. Gonzalez and P. Mazumder, “Redundant Arithmetic: Algorithms and Implementations,”
`INTEGRATION, the International VLSI Journal, Vol. 30, Dec. 2000, pp. 13-53.
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`50. L. Ding and P. Mazumder, ”On Optimal Tapering of FET Chains in High-Speed CMOS Circuits”,
`IEEE Transactions on Circuits and Systems, Vol. 48, No. 12, Dec. 2001, pp. 1099-1109.
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`51. L. Ding and P. Mazumder, “On Circuit techniques to Improve Noise Immunity of CMOS Dynamic
`Logic,” IEEE Transactions on VLSI Systems, Vol. 12, No. 9, pp. 910-925, Sept. 2004.
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`52. Q.W. Xu and P. Mazumder, “Efficient Modeling of Transmission Lines with Electromagnetic
`Wave Coupling by Using the Finite Difference Quadrature Method”, IEEE Transactions on VLSI
`Systems, Vol. 15, No. 12, Dec. 2007, pp. 1289-1302.
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`53. P. Mazumder, “Evaluation of On-Chip Static Interconnection Networks,” IEEE Transactions on
`Computers, C-36, Mar. 1987, pp. 365-369.
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`54. B. Wang and P. Mazumder, "Accelerated Chip-level Thermal Analysis Using Multilayer Green's
`Function," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
`Vol. 26, No. 2, Feb. 2007, pp. 325-244.
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`55. R. Venkateswaran and P. Mazumder, “Design of a Coprocessor for Accelerating Maze Routing in
`VLSI and PCB Layouts,” IEEE Transactions on VLSI Systems, Mar. 1993, Vol. 1, No. 1, pp. 1-14.
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`56. P. Mazumder, “An Economical Design of Programmable Seven Segments to Decimal Decoder,”
`Electronic Design News, Apr. 1987, pp. 222-224, (Design Ideas Prize Winner).
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`57. P. Mazumder, “Satellite Communications versus Submarine Cables for Long Distance Links,” IETE
`Journal - A Special Issue on TV Communication in India, 1976 (Best Student Paper Award
`Winner).
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`REVOLUTIONARY TECHNOLOGIES
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`QUANTUM TUNNELING DEVICES & SYSTEMS
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`58. J. P. Sun, G. I. Haddad, P. Mazumder and J. Schulman, “Resonant Tunneling Diodes: Device and
`Modeling,” Proceedings of the IEEE, Apr. 1998, pp. 641-663.
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`59. P. Mazumder, S. Kulkarni, G. I. Haddad, and J. P. Sun, “Digital Applications of Quantum Tunneling
`Devices,” Proceedings of the IEEE, Apr. 1998, pp. 664-688.
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`60. L. Ding and P. Mazumder, “Noise-Tolerant Quantum MOS Circuits Using Resonant Tunneling
`Devices,” IEEE Trans. on Nanotechnology, Mar. 2004, pp. 134-146.
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`61. A. Seabaugh and P. Mazumder, ”Quantum Devices and Their Applications,” Proceedings of the
`IEEE, Vol. 7, No. 4, April 1999.
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`62. T. Ueymura and P. Mazumder, ”Design and Analysis of Resonant-Tunneling-Diode (RTD) Based
`High Performance Memory System,” IEICE Transactions on Electronics (Special Issue on
`Integrated Electronics and New System Paradigms), Vol. E82-C, No. 9, Sept. 1999.
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`63. M. Bhattacharya and P. Mazumder, ”Analysis and Simulation of RTD and HBT Based Threshold
`Gate Logic,” IEEE Trans. on Circuits and Systems II, Vol. 47, No. 10, Oct. 2000, pp. 1080-1085.
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`64. M. Bhattacharya and P. Mazumder, ”Augmentation of SPICE for simulation of RTD Based
`Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
`20, No. 1, Jan, 2001, pp. 39-50.
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`65. A. F. Gonzalez and P. Mazumder, ”Multiple-Valued Signed-Digit Adder Using Negative
`Differential-Resistance Devices,” IEEE Transactions on Computers, Vol. 47, No. 9, Sept. 1998, pp.
`947-959.
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`66. S. Mohan, P. Mazumder, G. I. Haddad, R. Mains, and J. P. Sun, Ultra-fast Pipelined Adders Using
`Resonant Tunneling Transistors, IEE Electronics Letters, Vol. 27, No. 10, May 1991, pp. 830-831.
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`67. G. I. Haddad and P. Mazumder, ”Tunneling Devices and Their Applications in High-
`Functionality/Speed Digital Circuits,” Journal of Solid State Electronics, Vol. 41, No. 10, Oct.
`1997, pp. 1515-1524.
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`NANOELECTRONIC DEVICES & CIRCUITS
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`78. M. Rajagopalan and P. Mazumder, “Tunneling through Finite Quantum Dot Super-lattices” AJSE
`(Springer), Vol. 39, No. 3, pp. 1863-1879 (Invited).
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`68. W. H. Lee and P. Mazumder, “Color Image Processing Using Multi-Peak RTD’s”, ACM Journal
`of Emerging Technologies in Computing Systems, Vol. 9 No. 3, September 2013 (20 pages).
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`69. S. Mohan, P. Mazumder and G. I. Haddad, “A Sub-nanosecond 32-bit Multiplier Using Negative
`Differential Resistance Devices,” IEE Electronics Letters, Oct. 1991, Vol. 27, No. 21, pp. 1929-
`1931.
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`70. S. Mohan, P. Mazumder, G.I. Haddad and W. L. Chen, “Pico Second Pipelined Adder Using Three-
`Terminal NDR Devices,” IEE Proceedings-E: Computers and Digital Techniques, Vol. 141, No. 2,
`Mar. 1994, pp. 104-110.
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`71. S. Mohan, P. Mazumder, G. I. Haddad, R. Mains, and S. Sung, “Logic Design Based on Negative
`Differential Resistance Characteristics of Quantum Electronic Devices,” IEE Proceedings-G:
`Electronic Devices, Vol. 140, No. 6, Dec. 1993, pp. 383-391.
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`72. E. Chan, S. Mohan, P. Mazumder and G. I. Haddad, “Compact Multiple-valued Multiplexers Using
`Negative Differential Resistance,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, Aug. 1996,
`pp. 1151-1156.
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`73. E. Chan, M. Bhattacharya and P. Mazumder, “Mask Programmable Multi-Valued Logic Gate Arrays
`Using Resonant Tunneling Devices,” IEE Proceedings-E: Computers and Digital Techniques, Vol.
`143, No. 5, Oct. 1996, pp. 289-294.
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`74. S. Mohan, J.P. Sun, P. Mazumder and G. I. Haddad, “Device and Circuit Models for Resonant
`Tunneling Devices for Circuit Simulation,” IEEE Transactions on Computer-Aided Design of
`Integrat