United States Patent [191
`Lee
`
`USO05349556A
`[11]
`Patent Number:
`[45] Date of Patent:
`
`5,349,556
`Sep. 20, 1994
`
`[54] ROW REDUNDANCY CIRCUIT SHARING A
`FUSE BOX
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.
`_
`[75] Inventor‘ Egg!“ Lee’ Ahnsan’ Rep‘ of
`
`[73] Assignee: Samsung Electronics Co., Ltd.,
`Kyungki-do, Rep, of Korea
`
`21 A l. N .: 90691
`[
`1
`pp
`0
`’
`[22] Filed.
`Jul 13 1993
`‘
`°
`’
`Foreign Application Priority Data
`
`[30]
`
`Jul. 13, 1992 [KR] Rep. of Korea ....................... .. 12436
`
`[51] Int. 01.5 .............................................. .. G11C 7/00
`[52] US. Cl. ............................... .. 365/200; 365/225.7;
`371 /1()_3
`[58] Field of Search .............. .. 365/200, 230.03, 225.7;
`371/ 10.3, 10.1
`
`4,660,179 4/ 1987 Aoyama ............................ .. 365/200
`4,727,516 2/1988 Yoshida et a1. ............... .. 365/200
`5,255,234 10/1993 Seok .............................. .. 365/200 X
`Primary Examiner-‘Joseph A- Popek
`Attorney, Agent, or Firm-Cushman, Darby & Cushman
`[57]
`ABSTRACT
`The present invention discloses a row redundancy cir
`cuit in which, when the number of word lines contain
`ing defective memory cells in a ?rst normal memory
`cell array is greater than the. number of redundant word
`lines in a ?rst redundant memory cell array, an adjacent
`redundant row address decoder and associated adjacent
`redundant word lines are used to repair such excess
`number of defects Therefore, there is no need to in
`crease the number of redundant row address decoders
`and redundancy ef?ciency is greatly increased.
`
`12 Claims, 8 Drawing Sheets
`
`20L
`I
`
`NORMAL
`MEMORY
`CELL ARRAY
`
`10L
`I
`
`2"
`E
`9%
`QB
`Q5
`*5
`
`._
`e-
`
`30L 40L 5O 40R 30R
`I
`l
`I
`x
`:U
`§- III e - R - E
`02 2
`H 2 22
`E8 9% B R {:2
`>5 3i
`3g’
`'
`>_2_|
`73;
`-D
`g g Q;
`522 5
`g 52
`I“
`
`o m
`e- e
`
`0
`- e - e
`
`20R
`l
`
`NORMAL
`MEMORY
`CELL ARRAY
`
`10R
`I
`Q
`- 2
`E
`%2
`20
`=5
`E
`
`E
`- Q
`
`60L
`I
`
`NORMAL-WORD
`QOL'“ LINE DRIVER
`I ----- -- II
`ROW ADDRESS
`-'
`70L ~ RVEODRJBIEPNNET RWLL
`DRIVER
`——
`RAL
`
`60R
`I
`Renee
`
`NORMAL WORD ~
`LINE DRIVER
`90R
`----- -
`ROW ADDRESS
`REDUNDUNT
`RWLR WORD LINE ~7OR
`DRIVER
`
`RAL REDR
`
`80L ~ FUSE BOX REDL
`
`FUSE BOX ~ 80R
`
`ROW ADDRESS _
`
`ROW ADDRESS
`
`Apple – Ex. 1015
`Apple Inc., Petitioner
` 1
`
`

`
`U.S. Patent
`
`Sep. 20, 1994
`
`Sheet 1 of 8
`
`5,349,556
`
`
`.momxommmP._xommm:.._om
`
`
`
`wasmz:omo;mz_._omo;..._oh
`
`HZDQZDQME:30w.__oEzozaomm
`E>_~E--E>_mo
`
`
`
`Etc.tgtnifi
`
`
`
`mmm~Eo<30¢mmmmoo<soy.
`
`mmzmmIII-IIIu.I.Iu.I
`
`Iu..II-.I.IlI-
`
`
`2502.m8;oo9.02._<2moz.mommm_>_momz:E>_moH._z_._._om.9.0;
`
`
`
`
`
`
`GmmmmGWORROWM%EWMYMAnMRH.NUWMAW
`
`
`
`
`
` uw><$_<duoTmPLPR><E<._.mouwmmE052NLmoMMAEozm:mmEc._<_2mozwe.%VM»wu.._<2mozEcMwemmmmWWWSSW..nBDuRB
`
`H -
`
`mo.mommommowon._o¢Jon._oN._o—
`
`
`
`L.
`
`m_m_.._:n_2<~m_:_._n_2<
`
`
`
`
`
`
`
`mmmmoo<zom._Om._.zOommmEoo<zom
`
` 2
`
`
`
`
`

`
`US. Patent
`
`Sep. 20, 1994
`
`Sheet 2 of 8
`
`5,349,556
`
`m 3% 8>
`J. A. k 2 - ,,,,, -, ‘
`
`EN? QQQR V mmmmag 26m
`5. N .QNB?
`
`:E S 3 c ..... -- Q 9 I
`
`mama ~35 15 moms @b 5 6m; a: 35 J88 _ * @ _ * r_L F k k
`I, I I ¢ N .1 l I.
`L2 L8 Er» L? _ o\_ L‘ _ I?“ I? l8 l2
`,. .. 1 “ML A? I 1 ..
`
`
`
`w .QNB?
`
`
`
`
`
`Xe 00> ‘9.1% E Emma
`
`djmslimmemg _ mg _ We “ HE " %
`
` 3
`
`

`
`U.S. Patent
`
`Sep. 20, 1994
`
`Sheet 3 of 8
`
`5,349,556
`
`BIT LINE EQUALIZING
`CIRCUIT
`
`90R
`
`DRIVER
`LINE
`
`0I
`
`r 0 3_
`
`I
`<2:
`
`20
`
`: Oz
`
`>-
`>_<(cc
`‘ICE
`°<
`E._I
`L”...I
`Eu
`0
`
`NORMAL
`
`RWLR70RIEDRFUSEBOX80R
`
`
`ROWADDRESS
`
`ROWADDRESS
`
`FIG.3
`
`ROWADDRESS
`
`ROWADDRESS
`
`):
`
`0 L
`
`_I
`<:
`
`REDUNDUNT MEMORY
`CELL ARRAY
`
`ENSE AMPLIFIER
`
`/0 UNE
`
`S S
`
`ENSE AMPLIFIER
`
`S
`REDUNDUNT MEMORY
`CELL ARRAY
`
`__I>-
`<(CK
`20
`(IE
`Om
`
`
`S 1
`S S
`
`CK
`
`20R10
`
`30L4OLSO40R30R
`
`20L
`
`
`
`Z2CELLARRAY
`
`I2:
`Lu
`
`00
`
`2I
`: o 3.
`
`u Z_
`20
`
`l
`
`: O2
`
`1OL
`
`BIT LINE EQUALIZING
`CIRCUIT
`
`ca
`
` 4
`
`

`
`US. Patent
`
`86,). 20, 1994
`
`sheet 4 of 8
`
`5,349,556
`
`RAL
`
`REDL
`
`REDR
`
`Vcc
`
`104
`
`101
`102
`
`1 O3
`
`105
`
`106
`
`107
`
`¢EQL
`
`¢ISOR
`
`108
`
`FIG. 5A
`
`Vcc
`0
`
`[104'
`
`RAL
`
`101'
`_
`102’
`103'
`REDR —-—[§<>——jr
`105’
`REDL
`I____:
`RA? RAJ
`
`105'
`
`107'
`
`¢EQR
`¢|SOL
`
`108’
`
`FIG. 5B.
`
` 5
`
`

`
`US. Patent
`
`Sep. 20, 1994
`
`Sheet 5 of 8
`
`5,349,556
`
`RAF-‘150%
`
`‘
`
`RA_|—
`
`112
`
`113
`
`114
`
`115
`
`REDR
`
`R—AL
`
`REDL
`
`REDL
`
`RAL
`
`REDR
`
`122
`
`FIG. 6B
`
`¢"5—
`
`RA] RA] 125,
`
`V“
`
`126'
`
`LAR
`
`122'
`
`FIG. 6C
`
` 6
`
`

`
`U.S. Patent
`
`Sep. 20, 1994
`
`Sheet 6 of 8
`
`5,349,556
`
`Vcc
`
`I32
`
`¢RsT——c1
`
`F1
`
`MI
`
`REDL
`
`‘°X
`
`137
`
`I38
`
`RWLL
`
`ROW ADDRESS
`
`‘R73 W
`
`FIG 7A
`
`ROW ADDRESS
`
`fii
`
`EAT;
`
`FIG. 7B
`
` 7
`
`

`
`U.S. Patent
`
`Sep. 20, 1994
`
`Sheet 7 of 8
`
`5,349,556
`
`AMEV
`
`§.m><mv
`
`3<m\HEv
`
`Aqommv
`
`Ammmmv
`
`Eomshamg
`
`Somsxmamev
`
`EV
`
`33
`
`E4:
`
` 8
`
`

`
`US. Patent
`
`Sep. 20, 1994
`
`Sheet 8 of 8
`
`5,349,556
`
`km”;
`
`[*<___/
`
`W
`$823433
`SQmEESQV
`$255
`
`EV
`
`3%
`
`$26
`
`AMEV
`
` 9
`
`

`
`5,349,556
`2
`For example, if there are defects in the word line of the
`?rst normal memory cell array 20L, an address of the
`defective word line is programmed in the ?rst fuse box
`80L’ and the redundant word line corresponding to the
`defective normal word line is enabled in the redundant
`memory cell array 30L through the redundant word
`line driver 70L’. Further, the ?rst sense ampli?er 40L is
`enabled through the ?rst sense ampli?er control signal
`60L’ by the output signal REDL’ from the ?rst redun
`dant row address decoder 80L’, and as a result, the
`redundant word line is selected.
`FIG. 2 shows a detailed circuit diagram of the ?rst
`redundant row address decoder 80L’ for programming
`the address in which the defects are generated. As
`shown, one redundant row address decoder has a plu
`rality of fuses for receiving row addresses. After redun
`dancy programming and during normal operation, a
`block selection signal ¢BLKL is applied to node N1. If
`the defective address is input, node N1 remains at a
`logic “high” level, thereby generating a redundant
`word line signal RWL.
`In the circuit constructed in the above described
`manner, the normal memory cell array 20L or 20R have
`a large number of memory cells. In order to raise the
`probability of repairing all defective normal memory
`cells, at least one more redundant row address decoder
`is needed. As the number of redundant row address
`decoders increase, so does the need increase for addi
`tional word lines and associated redundant memory
`cells in the redundant memory cell arrays. Thus, the
`number of repairable word lines is limited by the num
`ber of corresponding redundant word lines within the
`redundant memory cell array. However, if a defective
`word line does not exist in the ?rst normal memory cell
`array 20L, but the number of defective word lines gen
`erated in the second normal memory cell array 20R is
`greater than the number of redundant word lines in the
`second redundant memory cell array 30R, the resulting
`semiconductor memory device will be inoperable.
`
`5
`
`25
`
`35
`
`1
`
`ROW REDUNDANCY CIRCUIT SHARING A FUSE
`BOX
`
`BACKGROUND OF THE INVENTION
`1. The Field of the Art
`The present invention relates to a semiconductor
`memory device, and more particularly to a row redun
`dancy circuit for repairing row defects generated in a
`given memory cell by the use of a redundant memory
`cell.
`2. Background of the Related Art
`As is well known in the art, a semiconductor memory
`device has a plurality of memory cells arranged in a
`matrix of columns and rows. As the capacity of a mem
`ory is increased, the semiconductor memory device
`contains more memory cells. In semiconductor memory
`devices, if defects are generated in any one memory
`cell, the semiconductor memory device cannot be used.
`In order to improve yields even if there is a defective
`memory cell, methods for replacing the defective nor
`mal memory cell with a redundant memory cell are well
`known.
`One example of such a redundancy technique con
`nects a fuse with each bit line or word line of the semi
`conductor memory device. If defects are generated in a
`normal memory cell, the fuse connected to the bit line
`or word line to which the normal memory cell is cou
`pled is cut by a laser beam, for example.
`However, as the integration density of semiconduc
`tor memory devices increases, it is wasteful of overall
`chip area to connect a fuse with each bit line and word
`line of the chip.
`Therefore, another method for using redundant mem
`ory cells when there is defective normal memory cell
`provides a redundant row decoder programmed with
`an address corresponding to the normal row address
`containing the defective memory cell. This method is
`the generally preferred method.
`Referring to FIG. 1, a conventional row redundancy
`circuit using redundant row address decoding method is
`shown. There are provided a ?rst normal memory cell
`array 20L, a ?rst redundant memory cell array 30L and
`a second normal memory cell array 20R, a second re
`dundant memory cell array 30R disposed around an
`45
`input/output (I/O) line 50. Each memory cell group
`including the redundant and normal memory cell arrays
`has ?rst and second sense ampli?ers 40L, 40R and ?rst
`and second bit line equalizing circuits 10L, 10R. More
`over, each memory cell group contains ?rst and second
`sense ampli?er control circuits 60L’, 60R’, ?rst and
`second redundant word line drivers 70L’, 70R’, ?rst and
`second redundant row address decoders or fuse boxes
`80L’, 80R’, and ?rst and second normal word line driv
`55
`ers 90L’, 90R’.
`FIG. 1 shows a two memory arrays and a plurality of
`such memory arrays are included in one chip.
`In the decoding method of FIG. 1, the redundant
`memory cell arrays 30L and 30R are respectively se
`lected when a redundant row address is decoded by the
`60
`redundant row address decoders 80L'and 80R’. The
`outputs of the redundant memory cell arrays 30L and
`30R are enabled by the redundant word line drivers
`70L’ and 70R’. That is, if defects are generated in the
`?rst normal memory cell array 20L, the ?rst redundant
`memory cell array 30L is used, and if the defects are
`generated in the second normal memory cell array 20R,
`the second redundant memory cell array 30R is used.
`
`50
`
`SUMMARY OF THE INVENTION
`It is therefore an object of the present invention to
`provide a row redundancy circuit capable of high inte
`gration ef?ciency.
`It is another object of the present invention to pro
`vide a row redundancy circuit that performs an effec
`tive redundancy operation.
`It is a further object of the present invention to pro
`vide a row redundancy circuit wherein adjacent mem
`ory array blocks share a redundant row address de
`coder.
`It is a still further object of the present invention to
`provide a row redundancy circuit wherein one redun
`dant row address decoder controls sense ampli?ers of
`adjacent memory arrays simultaneously.
`The present invention accomplishes the above recited
`objects with a row redundancy circuit in which, when
`the number of word lines containing defective memory
`cells in a ?rst normal memory cell array is greater than
`the number of redundant word lines in a ?rst redundant
`memory cell array, an adjacent redundant row address
`decoder and associated adjacent redundant word lines
`are used to repair such excess number of defects.
`Therefore, there is no heed to increase the number of
`redundant row address decoders and redundancy ef?
`ciency is greatly increased.
`
`65
`
` 10
`
`

`
`3
`BRIEF DESCRIPTION OF DRAWINGS
`The advantages and features of the present invention
`will be more apparent from the detailed description
`hereunder, with reference to the attached drawings, in
`which:
`FIG. 1 is a block diagram of a conventional row
`redundancy circuit;
`FIG. 2 is a more detailed circuit diagram of a redun
`dant row address decoder of FIG. 1;
`FIG. 3 is a block diagram of a row redundancy cir
`cuit according to the present invention;
`FIG. 4 shows a column structure of a memory array
`of FIG. 3;
`FIGS. 5A and 5B are circuit diagrams for generating
`bit line equalizing signals of FIG. 3;
`FIGS. 6A, 6B and 6C are circuit diagrams for gener
`ating sense ampli?er control signals of FIG. 3;
`FIGS. 7A and 7B are circuit diagrams showing exam
`ples of a redundant row address decoder of FIG. 3; and
`FIGS. 8A and 8B are timing diagram according to
`the present invention.
`
`5
`
`10
`
`25
`
`30
`
`35
`
`20
`
`5,349,556
`4
`during operation when this address is decoded. Accord
`ingly, the ?rst redundant row address decoder 80L of
`FIG. 3 disables the second sense ampli?er control cir
`cuit 60R, and enables the ?rst sense ampli?er control
`circuit 60L. If the address signal corresponding to an
`other word line containing defective memory cells of
`the ?rst normal memory cell array 20L is programmed
`into the second redundant row address decoder 80R,
`the signal REDR is enabled as logic “low” level and the
`signal REDL is disabled as logic “high” level. Accord
`ingly, the second redundant row address decoder 80R
`disables the ?rst sense ampli?er control circuit 60L, and
`enables the second sense ampli?er control circuit 60L.
`Thus, the defects in the ?rst normal memory cell array
`20L are repaired using the ?rst redundant memory cell
`array 30L the second redundant memory cell array 30R
`the second redundant memory cell array 30R.
`When there are no Word lines containing defective
`memory cells in the ?rst normal memory cell array 20L,
`if the number of word lines containing defective mem
`ory cells of the second normal memory cell array 20R is
`greater than the number of redundant word lines in the
`second redundant memory cell array 30R, the second
`redundant row address decoder 80R controls the sec
`ond sense ampli?er control circuit 60R to enable the
`second sense ampli?er 40R, and disables the ?rst sense
`ampli?er control circuit 60L. The ?rst redundant row
`address decoder 80L is then programmed with the ad
`dress of the second word line containing defective
`memory cells disposed in the second normal memory
`cell array 20R. When this address is input, signal REDL
`enables ?rst sense ampli?er control circuit 60L and
`disables second sense ampli?er control circuit 60R,
`thereby repairing the defective word lines of the second
`normal memory cell array 20R with the ?rst redundant
`memory cell array 30L and the second redundant mem
`ory cell array 30R.
`For a more detailed description, FIG. 4 shows one
`column of the memory array of FIG. 3 and each control
`signal. The ?rst and second sense ampli?ers 40L and
`40R of FIG. 3, as is well known in the art, each consist
`of ?rst and second PMOS sense ampli?ers 40L1 and
`40R1 each sharing an NMOS sense ampli?er 41. In
`order to separate the ?rst and second PMOS sense am
`pli?ers 40L1 and 40R1, there are provided isolation
`gates 1 and 2; 3 and 4 controlled by separate control
`signals qbISOL and ¢ISOR, respectively. The con?gu
`ration of each block in FIG. 4 is well known in the art.
`Each control signal of FIG. 4 is generated from the
`circuits of FIGS. 5A, 5B, 6A, 6B, 6C, 7A and 7B.
`Bit line equalizing control signals ¢EQL and ¢EQR
`of ?rst and second bit line equalizing circuits 10L1 and
`10R1, and the isolation control signals ¢ISOL and
`¢ISOR are generated from the circuits of FIGS. 5A
`and 5B. A signal RAL of FIG. 5A is for selecting a ?rst
`cell array 20L1 and a ?rst redundant memory cell array
`30L1, and a signal RAL of FIG. 5B is for selecting a
`second cell array 20R1 and a second redundant memory
`cell array 30R1. Signals RAi and Raj are for selecting
`the illustrated memory arrays of FIG. 3, assuming that
`there are a greater number of such arrays on the chip. If
`the ?rst redundant memory cell array 30L1 is selected,
`the signals RAL, REDR, RAi and RAj of FIG. 5A are
`set to logic “high” level and the signal REDL is set to
`a logic “low” level, the output of the NAND gate 105
`is set to logic “low” level. Therefore, the bit line equal
`izing control signal ¢EQL and the separate control
`signal ¢ISOR are set to logic “low” level, and the out
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`The block diagram of FIG. 3 has the same overall
`con?guration as that of FIG. 1, except that redundant
`row address decoders 80L and 80R are simultaneously
`connected to sense ampli?er control circuits 60L and
`60R. However, the detailed circuits and operations
`thereof are considerably different as will be explained
`hereinafter. In the explanation of the drawings, the same
`reference numerals and symbols are used to designate
`similar elements.
`Referring to FIG. 3, ?rst and second sense ampli?er
`control circuits 60L and 60R are respectively connected
`to ?rst and second sense ampli?ers 40L and 40R. A ?rst
`redundant row address decoder 80L normally receives
`a row address and the selection signal. If the input row
`address corresponds to the address programmed into
`redundant row address decoder 80L, output signal
`REDL is generated and is connected to the ?rst and
`second sense ampli?er control circuits 60L and 60R. A
`second redundant row address decoder 80R similarly
`normally receives the row address and the selection
`signal associated with the second normal memory cell
`array 20R. If the input row address corresponds to the
`address programmed into redundant row address de
`coder 80R, output signal REDR is connected to the ?rst
`and second sense ampli?er control circuits 60L and
`60R. First and second redundant word line drivers 70L
`and 70R enable the ?rst and second redundant memory
`cell arrays 30L and 30R, respectively.
`If the number of word lines containing defective
`memory cells in the ?rst normal memory cell array 20L
`55
`is less than or equal to the number of redundant word
`lines in the ?rst redundant memory cell array 30L, the
`row redundancy circuit of FIG. 3 performs substan
`tially the same operation as that of FIG. 1.
`However, when the number of word lines containing
`defective memory cells in the ?rst normal memory cell
`array 20L is greater than the number of redundant word
`lines in the first redundant memory cell array 30L, if the
`address signal corresponding to the defective word line
`of the ?rst normal memory cell array 20L is pro
`grammed into the ?rst redundant row address decoder
`80L, the signal REDL is enabled as a logic “low” level
`and the signal REDR is disabled as logic “high” level
`
`45
`
`65
`
` 11
`
`

`
`20
`
`25
`
`5,349,556
`5
`put of the ?rst redundant memory cell array 30L1 of
`FIG. 4 is enabled.
`On the other hand, if the second redundant memory
`cell array 30R1 is selected, the signals RAL, REDL,
`RAi and RAj of FIG. 5B are set to logic “high” level
`and the signal REDR is set to a logic “low” level, the
`output of the NAND gate 105' is set to logic “low”
`level. Hence, the bit equalizing signal ¢EQR and the
`separate control signal qbISOL are set to logic “low”
`level and the output of the second redundant cell array
`30R1 of FIG. 4 is enabled.
`Sense ampli?er control signals LE, LAL and LAR
`of the sense ampli?ers 41, 40L1 and 40R1 of FIG. 4 are
`generated from the circuits of FIGS. 6A, 6B and 6C.
`FIG. 6A shows the circuit for generating the signal I]
`controlling the NMOS sense ampli?er 41 of FIG. 4. A
`timing signal ¢S is enabled to logic “high” level during
`a data sensing operation. If the ?rst or second cell array
`is selected, the signals RAi, RAj and (b5 are all set to
`logic “high” level. Hence, an NMOS transistor 115 is
`turned on and the signal E4- of logic “low” level is
`generated. The signal LA of the logic “low” level ena
`bles the NMOS sense ampli?er 41 of FIG. 4.
`FIG. 6B shows the circuit for generating the signal
`LAL controlling the ?rst PMOS sense ampli?er 40L1.
`Timing signal (#8 is delayed for a predetermined time to
`generate a signal 4>SD shown E FIG. 6A. In FIG. 4,
`when the ?rst PMOS sense ampli?er 40L1 is selected,
`the signal LAL must be set to logic “high” level. There
`fore, if the ?rst PMOS sense ampli?er 40L1 is selected,
`the signals RAi, RAj, REDR and RAL are set to logic
`“high” level and the signal ¢SD is set to logic “low”
`level during normal operation. At this time, since the
`signal RAL is set to a logic “high” level, the signal
`REDL is ignored in the NOR gate 123. As a result, the
`signal LAL of logic “high” level is generated to enable
`the PMOS sense ampli?er 40L1 of FIG. 4.
`FIG. 6C shows the circuit for generating the signal
`LAR controlling the second PMOS sense ampli?er
`40R1. When the second PMOS sense ampli?er 40Rl is
`selected, the signal LAR must be set to logic “high”
`level. Therefore, if the second PMOS sense ampli?er
`40R1 is selected, the signals RAi, RAj, REDL and
`RAL are set to logic “high” level and the signal ¢SD of
`45
`logic “low” level during normal operation. At this time,
`since the signal RAL is set to a logic “high” level, the
`signal REDL is ignored in the NOR gate 123. As a
`result, the signal LAR of logic “high” level is generated
`to enable the PMOS sense ampli?er 40R1 of FIG. 4 is
`enabled.
`The redundant enable signals REDL and REDR for
`controlling the ?rst and second sense ampli?er control
`circuits 60L and 60R of FIG. 3 during a redundancy
`operation are generated from the redundant row ad
`dress decoder circuits shown in FIGS. 7A and 7B. Re
`ferring to FIGS. 7A and 7B, NMOS transistors 137, 138
`and 137’, 138’ are the redundant word line driver circuit
`and enable redundant word lines RWLL and RWLR,
`respectively. It should be noted that if a defective ad
`60
`dress is applied, the signals REDL and REDR are set to
`logic “low” level due to the electrical pathways pro
`grammed into the fuses to correspond to the defective
`address.
`The redundancy operation of FIG. 3, in accordance
`with the circuits of FIGS. 5A, 5B, 6A, 6B, 6C, 7A and
`7B, will now be described with reference to the timing
`diagrams of FIGS. 8A and 8B.
`
`6
`Assuming that one redundant word line exists in the
`?rst and second redundant memory cell arrays 30L and
`30R, respectively and one word line containing defec
`tive memory cells exists in the ?rst normal memory cell
`array 20L, since the redundant word line included in the
`?rst redundant memory cell array 30L is suf?ciently
`capable of repairing the word line containing defective
`memory cells, substantially the same redundancy opera
`tion with that of FIG. 1 is performed. If the number of
`redundant word lines contained in the ?rst redundant
`memory cell array 30L is one (“1”) and the number of
`word lines containing defective memory cells generated
`in the ?rst normal memory cell array 20L is two (“2”),
`it is impossible to repair the word lines containing de
`fective memory cells using only the redundant word
`line in the ?rst redundant memory cell array 30L.
`However, when the defective address signal is ap
`plied to the redundant row address decoder of FIG. 7A
`to repair one word line containing defective memory
`cells of two such word lines, a node N10 maintains logic
`“high” level and the signal REDL is set to logic “low”
`level as shown in FIG. 8B. An then, the redundant
`word line RWLL is enabled as logic “high” level. Fur
`ther, in FIG. 6B, since the three input signals of the
`NOR gate 124 are set to logic “low” levels and the three
`input signals of the NAND gate 125 are set to logic
`“high” levels, the signal LAL is set to logic “low” level.
`In FIG. 6C, since the signal REDL is set to as logic
`“low” level, the NOR gate 124’ outputs the signal of
`logic “low” level. As a result, the signal LAR is set to
`a precharge state of % Vcc. Accordingly, the ?rst
`PMOS sense ampli?er 40L1 is enabled to replace the
`one word line having defective memory cells.
`On the other hand, when the defective address signal
`is applied to the redundant row address decoder of
`FIG. 7B to repair the other word line containing defec
`tive memory cells, a nod N10’ maintains logic “high”
`level and the signal REDR is set to logic “low” level as
`shown in FIG. 8A. And then, the redundant word line
`RWLR is enables as logic “high” level. Further, in
`FIG. 6C, since the three input signals of the NOR gate
`124’ are set to logic “low” levels and the three input
`signals of the NAND gate 124’ are set to logic “high”
`levels, the signal LAR is set to a logic “high” level. In
`FIG. 6B, since the signal REDR is set to as logic “low”
`level, the NOR gate 124 outputs the signal of logic
`“low” level. As a result, the signal LAL is set to a pre»
`charge state of % Vcc. Accordingly, the second PMOS
`sense ampli?er 40R1 is enabled so as to replace the
`other word line containing defective memory cells.
`When the second normal memory cell contains more
`word lines having memory cell defects than associated
`redundant word lines and associated redundant memory
`cells, operation of the ?rst and second redundant mem
`ory cell arrays is similar to that described above. FIGS.
`8A and 8B each respectively illustrate the timing associ
`ated with the ?rst redundant memory cell array 30L1
`and the second redundant memory cell array 30R1.
`Thus, according to the present invention, even if the
`number of word lines containing defective memory
`cells in the normal memory cell array is greater than the
`number of redundant word lines included in the redun
`dant memory cell array, there is no necessity for in
`creasing the number of redundant row address decoders
`connected only to that particular normal memory array.
`As described above, in the row redundancy circuit
`embodying the present invention, since one redundant
`row address decoder controls each sense ampli?er of
`
`55
`
`65
`
` 12
`
`

`
`5
`
`25
`
`7
`adjacent memory arrays, there is no need to increase the
`number of redundant row address decoder in order to
`increase redundancy ef?ciency. While preferred em
`bodiments of the present invention have been particu
`larly shown and described, it will be understood by
`those skilled in the art that foregoing and other changes
`in form and details may be made without departing
`from the spirit and scope of the present invention.
`What is claimed is:
`1. A row redundancy circuit in a semiconductor
`memory device having a plurality of ?rst normal mem
`ory cell arrays and a plurality of second normal mem
`ory cell arrays, each ?rst normal memory cell array
`having a plurality of rows and further including a ?rst
`redundant memory cell array and a ?rst sense ampli?er
`array, and each second normal memory cell array hav
`ing a plurality of rows and further including a second
`redundant memory cell array and a second sense ampli
`?er array, said second normal memory cell array being
`substantially adjacent to said ?rst normal memory cell
`array, said row redundancy circuit comprising:
`a ?rst sense ampli?er control circuit connected to
`said ?rst sense ampli?er array that generates a ?rst
`sense ampli?er array control signal that is input to
`said ?rst sense ampli?er array; and
`a second sense ampli?er control circuit connected to
`said second sense ampli?er array that generates a
`second sense ampli?er array control signal that is
`input to said second sense ampli?er array;
`a ?rst redundant row address decoder programmed
`to decode a ?rst row address and a ?rst array select
`signal associated with a ?rst one of said rows lo
`cated within one of said ?rst normal memory cell
`arrays and said substantially adjacent second nor
`mal memory cell array, said ?rst redundant row
`35
`address decoder outputting a ?rst redundant row
`address decode signal when said ?rst row address
`is decoded to both said ?rst and second sense am
`pli?er control circuits; and
`a second redundant row address decoder pro
`grammed to decode a second row address and a
`second array select signal associated with a second
`one of said rows located within said one of said ?rst
`normal memory cell arrays and said substantially
`adjacent second normal memory cell array, said
`second redundant row address decoder outputting
`a second redundant row address decode signal
`when said second row address is decoded to both
`said ?rst and second sense ampli?er control cir
`cuits.
`2. A row redundancy circuit according to claim 1,
`wherein said ?rst and second row addresses are both
`associated with said ?rst normal memory cell array.
`3. A row redundancy circuit according to claim 2,
`wherein said ?rst sense ampli?er control circuit gener
`ates said ?rst sense ampli?er array control signal in
`response to both said ?rst redundant row address de
`code signal and said second redundant row address
`decode signal.
`4. A row redundancy circuit according to claim 1,
`wherein said ?rst and second row addresses are both
`associated with said second normal memory cell array.
`5. A row redundancy circuit according to claim 4,
`wherein said second sense ampli?er control circuit gen
`erates said second sense ampli?er array control signal in
`response to both said ?rst redundant row address de
`code signal and said second redundant row address
`decode signal.
`
`5,349,556
`8
`6. A row redundancy circuit according to claim 1,
`wherein said ?rst sense ampli?er control circuit further
`inputs a ?rst array select signal and said second sense
`ampli?er control circuit further inputs a second array
`select signal so that only one of said ?rst sense ampli?er
`array control signal and said second sense ampli?er
`array control signal are generated at the same time.
`7. A row redundancy circuit in a semiconductor
`memory device having a plurality of first normal mem
`ory cell arrays and a plurality of second normal mem
`ory cell arrays, each ?rst normal memory cell array
`having a plurality of rows and further including a ?rst
`redundant memory cell array and a ?rst sense ampli?er.
`array, and each second normal memory cell array hav
`ing a plurality of rows and further including a second
`redundant memory cell array and a second sense ampli
`?er array, said second normal memory cell array being
`substantially adjacent to said ?rst normal memory cell
`array, said circuit comprising:
`a ?rst sense ampli?er control circuit connected to
`said ?rst sense ampli?er array that generates a ?rst
`sense ampli?er array control signal that is input to
`said ?rst sense ampli?er array; and
`a second sense ampli?er control circuit connected to
`said second sense ampli?er array that generates a
`second sense ampli?er array control signal that is
`input to said second sense ampli?er array;
`a ?rst redundant row address decoder programmed
`to decode a ?rst row address and a ?rst array select
`signal associated with a ?rst one of said rows lo
`cated within one of said ?rst normal memory cell
`arrays and said substantially adjacent second nor
`mal memory cell array, said ?rst redundant row
`address decoder outputting a ?rst redundant row
`address decode signal when said ?rst row address
`is decoded to both said ?rst and second sense am
`pli?er control circuits;
`a second redundant row address decoder pro
`grammed to decode a second row address and a
`second array select signal associated with a second
`one of said rows located within said one of said ?rst
`normal memory cell arrays and said substantially
`adjacent second normal memory cell array, said
`second redundant row address decoder outputting
`a second redundant row address decode signal
`when said second row address is decoded to both
`said ?rst and second sense ampli?er control cir
`cuits;
`a ?rst redundant word line driver for enabling said
`?rst redundant memory cell array in response to
`said ?rst redundant row address decode signal; and
`a second redundant word line driver for enabling said
`second redundant memory cell array in response to
`said second redundant row address decode signal.
`8. A row redundancy circuit according to claim 7,
`wherein said ?rst and second row addresses are both
`associated with said ?rst normal memory cell array.
`9. A row redundancy circuit according to claim 8,
`wherein said ?rst sense ampli?er control circuit gener
`ates said first sense ampli?er array control signal in
`response to both said ?rst redundant row address de~
`code signal and said second redundant row address
`decode signal.
`10. A row redundancy circuit according to claim 7,
`wherein said ?rst and second row addresses are both
`associated with said second normal memory cell array.
`11. A row redundancy circuit according to claim 10,
`wherein said second sense ampli?er control circuit gen
`
`45
`
`55
`
`65
`
` 13
`
`

`
`5,349,556
`erates said second sense ampli?er array control signal in
`response to both said ?rst redundant row address de
`code signal and said second redundant row address
`decode signal.
`12. A row redundancy circuit according to claim 7,
`wherein said ?rst sense ampli?er control circuit further
`
`10
`inputs a ?rst array select signal and said second sense
`ampli?er control circuit further inputs a second array
`select signal so that only one of said ?rst sense ampli?er
`array control sign