throbber
Trials@uspto.gov
`571-272-7822
`
`Paper No. 10
`
` Entered: April 7, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00033
`Patent 6,020,259
`____________
`
`
`
`Before KEVIN F. TURNER, JO-ANNE M. KOKOSKI, and
`JEFFREY W. ABRAHAM, Administrative Patent Judges.
`
`
`ABRAHAM, Administrative Patent Judge.
`
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`
`
`I. INTRODUCTION
`
`Samsung Electronics Co., Ltd. (“Petitioner”) filed a Petition seeking
`
`inter partes review of claims 1–10 of U.S. Patent No. 6,020,259 (Ex. 1001,
`
`“the ’259 patent”). Paper 1 (“Pet.”). ProMOS Technologies, Inc. (“Patent
`
`Owner”) filed a Patent Owner Preliminary Response to the Petition. Paper 7
`
`(“Prelim. Resp.”). After considering the Petition and Preliminary Response,
`
`we determine that Petitioner has not established a reasonable likelihood of
`
`prevailing with respect to any of the challenged claims of the ’259 patent.
`
`See 35 U.S.C. § 314(a). Accordingly, we deny the Petition, and do not
`
`institute inter partes review.
`
`II. BACKGROUND
`
`A. Related Proceedings
`
`The parties identify ProMOS Technologies, Inc. v. Samsung
`
`Electronics Co. Ltd., Civil Action No. 1:15-cv-00898-SLR-SRF (D. Del.),
`
`involving the ’259 patent. Pet. 1; Paper 5, 1. The parties also identify
`
`IPR2017-00035, a second petition seeking review of the ’259 patent. Pet. 1;
`
`Paper 5, 1.
`
`B. The ’259 Patent
`
`The ’259 patent, titled “Method of Forming a Tungsten-Plug Contact
`
`for a Semiconductor Device,” issued on February 1, 2000. Ex. 1001, [54],
`
`[45]. The ’259 patent discloses a method of forming “a W-plug by using
`
`selective TiSi2 [chemical vapor deposition (CVD)] process, TiN CVD
`
`process and chemical mechanical polishing (CMP).” Id. at 2:41–43. The
`
`method of the ’259 patent includes (1) depositing an isolation layer, such as
`
`BPSG or silicon oxide, on a substrate, (2) generating a contact hole in the
`
`
`
`2
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`isolation layer by an etching process, (3) selectively depositing a TiSi2 layer
`
`in the contact hole on the substrate using CVD, (4) forming a TiN layer on
`
`the isolation layer, the sidewall of the contact hole, and the TiSi2 layer, (5)
`
`forming a tungsten layer on the TiN layer and in the contact hole, and (6)
`
`polishing the tungsten layer to the surface of the isolation layer for
`
`planarization. Id. at 2:62–3:37.
`
`The ’259 patent teaches that the TiSi2 layer can be selectively
`
`deposited at the contact region using TiCl4 as the reaction material and by
`
`controlling the temperature and pressure of the reaction. Id. at 3:13–18
`
`(stating that the preferred temperature of CVD is about 600–900° C, and the
`
`preferred pressure is 5 to 100 torr). The ’259 patent also teaches that “[t]he
`
`present invention provides a thinner TiN layer process to reduce the time for
`
`CMP polish. Therefore, the cost of the process is degraded and the
`
`throughput is increased. Further, the erosion problem . . . generated by long
`
`polish time is eliminated by the present invention.” Id. at 3:38–42; see also
`
`id. at 1:48–55 (noting that the conventional CMP process “needs [a] long
`
`polish time to remove the thick TiN layer” which “may cause the erosion
`
`effect” and “raises the cost” of CMP).
`
`C. Challenged Claims
`
`Petitioner challenges claims 1–10 of the ’259 patent. Independent
`
`claim 1 is illustrative, and is reproduced below:
`
`1. A method of forming an electrical contact on a semi-
`conductor wafer, said method comprising:
`
`forming an isolation layer on said wafer;
`
`forming a contact hole in said isolation layer, said contact
`hole exposing a portion of said wafer;
`
`
`
`3
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`selectively forming a TiSi2 layer in said contact hole on said
`exposed wafer by using chemical vapor deposition and
`by controlling a deposition temperature, the reaction
`material being TiCl4, wherein said reaction material
`(TiCl4) reacts with said exposed wafer thereby forming
`said TiSi2 wherein said TiSi2 layer is selectively formed
`at said deposition temperature in the range of about 600°
`C. to 700° C.;
`
`forming a TiN layer on said isolation layer, on the surface
`of said contact hole and on the TiSi2 layer by using
`chemical vapor deposition in nitrogen ambient
`environment, the reaction material being TiCl4;
`
`forming a tungsten layer on said TiN layer and in said
`contact hole; and
`
`planarizing said tungsten layer and said TiN layer to the
`surface of said isolation layer by using chemical
`mechanical polishing.
`
`Id. at 3:56–4:13. Independent claim 4 is substantially similar to claim 1,
`
`except that it does not require that the “TiSi2 layer is selectively formed at
`
`said deposition temperature in the range of about 600° C. to 700° C,” and
`
`further requires that the “TiN layer is formed at a temperature in the range of
`
`about 600° C. to 900° C.” Id. at 4:23–45.
`
`
`
`Petitioner relies on the following references:
`
`D. References
`
`Mathews et al., US Patent No. 5,580,821, issued Dec. 3, 1996
`(“Mathews,” Ex. 1006).
`
`Suzuki et al., JP H05-67585, published March 19, 1993 (“Suzuki,”
`Ex. 1004).
`
`Nakanishi et al., Kinetics of Chemical Vapor Deposition of
`Titanium Nitride, 137 J. Electrochem. Soc. 322–328 (1990)
`(“Nakanishi,” Ex. 1005).
`
`
`
`4
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`Maury et al., Selective Titanium Silicide for Industrial
`Applications, 402 Mat. Res. Soc. Symp. Proc. 283–294 (1996)
`(“Maury,” Ex. 1007).
`
`Petitioner also relies on Applicant’s Admitted Prior Art (“AAPA”)
`
`and the Declaration of Gary Rubloff, PhD. (Ex. 1002).
`
`E. The Asserted Grounds
`
`Petitioner asserts the following grounds of unpatentability:
`
`References
`
`Suzuki, Nakanishi, and
`AAPA
`Suzuki, Nakanishi,
`AAPA, and Mathews
`Suzuki, Nakanishi,
`AAPA, and Maury
`
`
`Statutory
`Basis
`
`§103
`
`§103
`
`§103
`
`Claims Challenged
`
`1, 4–7, and 9
`
`2 and 8
`
`3 and 10
`
`III. ANALYSIS
`
`A. Claim Construction
`
`Petitioner offers a proposed construction for “forming a TiN layer . . .
`
`by using chemical vapor deposition in nitrogen ambient environment, the
`
`reaction material being TiCl4.” Pet. 19–21. Patent Owner argues that the
`
`Board does not need to construe this limitation in order to resolve the
`
`question of patentability. Prelim. Resp. 13–14.
`
`We agree with Patent Owner that no express claim construction is
`
`necessary for purposes of this decision. See Vivid Techs., Inc. v. Am. Sci. &
`
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those terms need be
`
`construed that are in controversy, and only to the extent necessary to resolve
`
`the controversy.”).
`
`
`
`5
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`B. References
`
`i.
`
`Suzuki
`
`Suzuki discloses a method for forming a semiconductor device that
`
`includes forming an insulating film with openings (i.e., contact holes) on a
`
`silicon circuit board. Ex. 1004 ¶¶ 1, 13. Suzuki teaches forming a contact
`
`metal layer comprising TiSi2 at the bottom of the contact hole using CVD
`
`with TiCl4 as the titanium source and heating the Si circuit board to a
`
`temperature between 60 and 700° C. Id. ¶ 14. Suzuki further teaches the
`
`steps of forming a barrier metal layer comprising TiN on the contact metal
`
`layer, the sidewall of the contact hole, and the insulation layer, and forming
`
`a wiring layer, which may be comprised of tungsten, on the TiN barrier
`
`layer. Id. ¶¶ 14–15. Figure 1(c) of Suzuki is reproduced below.
`
`
`
`Figure 1(c) of Suzuki shows a semiconductor device having insulating
`
`layer (4) with an opening (3) on a Si circuit board (1), a contact metal layer
`
`(5) on the Si circuit board (1) inside the opening (3), a barrier metal layer (6)
`
`covering the contact metal layer (5) and insulating layer (3), and a wiring
`
`layer (7) covering the barrier metal layer (6). Id. ¶¶ 13–15.
`
`ii. Nakanishi
`
`Nakanishi discusses the kinetics and reaction mechanism of chemical
`
`vapor deposition of titanium nitride using reactant gases H2, N2, and TiCl4.
`
`Ex. 1005, 322–323.
`
`
`
`6
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`iii. Mathews
`
`Mathews discloses a “semiconductor processing method of forming
`
`an electrically conductive contact plug relative to a wafer” that includes
`
`depositing a material on a substrate followed by “pattern masking,”
`
`preferably using a layer of photoresist, and etching the material to form a
`
`desired contact opening in the material. Ex. 1006, Abstract, 3:23–29.
`
`iv. Maury
`
`Maury discloses a “TiSi2 selective CVD technique” that includes “the
`
`deposition of TiSi2 using the H2/SiH4 (or DCS)/TiCl4 gas system in the 650–
`
`750°C temperature range,” and wherein the working pressure of the reactive
`
`gasses is between 20 and 5 Torr. Ex. 1007, 283, 286.
`
`v.
`
` AAPA
`
`The ’259 patent contains a section titled “Background of the
`
`Invention,” which includes a discussion of a “conventional method” of
`
`forming a tungsten-plug used to fill a contact hole in an isolation layer. Ex.
`
`1001, 1:26–28. According to the ’259 patent, this conventional method
`
`includes depositing an isolation layer on a silicon substrate, creating a
`
`contact hole in the isolation layer using patterning and etching, and
`
`depositing a titanium layer on the isolation layer and on the surface of the
`
`contact hole using physical vapor deposition (PVD). Id. at 1:29–35. The
`
`’259 patent states that a TiSi2 layer is formed at the interface between the
`
`silicon substrate and the titanium layer. Id. at 1:42–44. The ’259 patent
`
`further describes forming a tungsten layer in the contact hole using CVD and
`
`using CMP to polish the tungsten layer for planarization. Id. at 1:46–49,
`
`Fig. 3. Petitioner refers to these disclosures as the Applicant’s Admitted
`
`Prior Art (AAPA). Pet. 6.
`
`
`
`7
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`C. Obviousness of Claims 1–10
`
`For each asserted ground challenging the claims of the ’259 patent,
`
`Petitioner relies on Suzuki, Nakanishi, and AAPA. Pet. 2–3. Petitioner
`
`additionally relies on Mathews and Maury for the asserted grounds
`
`challenging dependent claims 2, 3, 8, and 10. Id.
`
`Independent claims 1 and 4 each recite forming a TiN layer on an
`
`isolation layer, forming a tungsten layer on the TiN layer, and “planarizing
`
`said tungsten layer and said TiN layer to the surface of said isolation layer
`
`by using chemical mechanical polishing.” Ex. 1001, 4:4–13, 4:35–45.
`
`Petitioner contends that the combined teachings of Suzuki and
`
`Nakanishi disclose a tungsten layer deposited on top of a TiN layer, but
`
`acknowledges that Suzuki and Nakanishi fail to disclose planarizing the
`
`tungsten layer and TiN layer to the insulating layer. Pet. 37–38. Petitioner,
`
`however, argues that the claimed planarization step “was well known as
`
`acknowledged by the AAPA in the ’259 patent.” Id. at 38. Specifically,
`
`Petitioner directs us to Figure 3 of the ’259 patent, arguing that it is labeled
`
`as “prior art” and shows a tungsten layer and TiN layer planarized to the
`
`surface of the isolating layer. Id. (citing Ex. 1001, 1:46–51, Figs. 2, 3; Ex.
`
`1002 ¶ 70). Petitioner also notes that the ’259 patent refers to the use of
`
`CMP to perform planarization as “conventional.” Id. at 39. Additionally,
`
`Petitioner argues that during prosecution of the application leading to the
`
`’259 patent, the Examiner stated that this claimed feature was admitted prior
`
`art, and the applicant did not rebut those statements. Id. at 39–40.
`
`Petitioner thus argues that:
`
`Given the admissions in the ’259 patent, a skilled artisan
`would have known to use CMP for planarization of the tungsten
`and TiN layers in Suzuki to the surface of the insulation film 4
`
`
`
`8
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`the Suzuki-Nakanishi combination and would have
`in
`recognized the benefit of such planarization for subsequent
`processing, handling, and/or use of the resulting device. (Ex.
`1002 at ¶ 72.) A skilled artisan would have been motivated to
`planarize the tungsten and TiN layers in Suzuki using CMP to
`provide a substantially flat surface so that the layers (e.g.,
`interconnection layers) that are typically added to the tungsten
`plug can reliably be added to achieve multiple wiring layers
`with better manufacturing yield, reliability, and performance.
`(Id.)
`
`Id. at 40.
`
`Petitioner further asserts that the use of CMP for planarizing the
`
`tungsten and TiN layers constitutes nothing more than the use of a known
`
`technique to improve a similar device to yield an expected result. Id. (citing
`
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
`
`Patent Owner argues that AAPA is not eligible prior art under 35
`
`U.S.C. § 311(b), which limits the prior art the Board can consider in inter
`
`partes reviews to “patents or printed publications.” Prelim. Resp. 7–8.
`
`Patent Owner further argues that even if the Board could and/or does
`
`consider the AAPA, the Board should still deny institution because
`
`Petitioner fails to explain adequately why a person of ordinary skill in the art
`
`would have combined the CMP process from the AAPA with the teachings
`
`of Suzuki and Nakanishi. Id. at 9. Patent Owner asserts that simply
`
`showing individual claimed elements were already known in the art is
`
`insufficient. Id. Rather, Petitioner must demonstrate that a person of
`
`ordinary skill in the art would have had a reason to combine the teachings of
`
`the prior art references to achieve the claimed invention, and would have had
`
`a reasonable expectation of success in doing so. Id. (citing KSR, 550 U.S. at
`
`418; PAR Pharm., Inc. v. TWI Pharms. Inc., 773 F.3d 1186, 1193 (Fed. Cir.
`
`
`
`9
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`2014)). Patent Owner contends that Petitioner’s only support for combining
`
`the CMP process of the AAPA with what Suzuki teaches is the conclusory
`
`statement from its declarant alleging the benefits associated with CMP. Id.
`
`at 10–11. Patent Owner thus argues that Petitioner failed to present any
`
`evidence or a reasoned explanation demonstrating that a person of ordinary
`
`skill in the art would have had a reason to combine the teachings of AAPA
`
`and Suzuki. Id. (citing In re Nuvasive, 842 F.3d 1376, 1384–85 (Fed. Cir.
`
`2016)).
`
`Patent Owner also notes that Suzuki refers to the tungsten layer as a
`
`“wiring layer” with a film thickness of roughly 5000 Å. Id. at 12 (citing Ex.
`
`1004 ¶ 15). Patent Owner argues that a person of ordinary skill in the art
`
`would have known that the tungsten and TiN layers would have to be
`
`retained, and therefore would not utilize the CMP process from the AAPA
`
`that would remove those layers down to the isolation layer. Id. Patent
`
`Owner further argues that the thickness of the TiN layer in Suzuki provides
`
`another reason why a person of ordinary skill in the art would not have had a
`
`reason to use the planarizing step from the AAPA in combination with
`
`Suzuki’s process for forming a semiconductor device. Id. at 12–13. Patent
`
`Owner points out that the ’259 patent states that removing a thick TiN layer
`
`using the conventional CMP process requires a long polish time for
`
`planarization, which may cause an erosion effect and increase the cost of the
`
`CMP. Id. (citing Ex. 1001, 1:49–54, 3:38–43). According to Patent Owner,
`
`“[t]hese problems associated with the CMP process are exactly what the
`
`’259 invention was trying to solve,” and, therefore, “[u]sing the AAPA CMP
`
`process with the thick TiN layer of Suzuki would lead to precisely the same
`
`
`
`10
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`problems of erosion and increased costs that a [person of ordinary skill in the
`
`art] would want to avoid.” Id. at 13.
`
`We agree with Patent Owner that, on this record, Petitioner failed to
`
`demonstrate sufficiently that a person of ordinary skill in the art would have
`
`had a reason to combine the teachings of the AAPA CMP process with
`
`Suzuki’s method for forming a semiconductor device.
`
`The Supreme Court has explained that an obviousness analysis should
`
`“determine whether there was an apparent reason to combine the known
`
`elements in the fashion claimed by the patent at issue.” KSR, 550 U.S. at
`
`418. Similarly, the Federal Circuit has made clear that “[t]he factual inquiry
`
`whether to combine references must be thorough and searching” (Nuvasive,
`
`842 F.3d at 1381 (quoting In re Lee, 277 F.3d 1338, 1343 (Fed. Cir. 2002)),
`
`and that an obviousness determination “cannot be sustained by mere
`
`conclusory statements; instead, there must be some articulated reasoning
`
`with some rational underpinning to support the legal conclusion of
`
`obviousness” (In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)). See KSR,
`
`550 U.S. at 418 (quoting Kahn, 441 F.3d at 988); see also Lee, 227 F.3d at
`
`1342, 1345 (“The board cannot rely on conclusory statements when dealing
`
`with particular combinations of prior art and specific claims, but must set
`
`forth the rationale on which it relies.”).
`
`Petitioner relies on testimony from Dr. Rubloff regarding better
`
`manufacturing yield, reliability, and performance resulting from CMP as
`
`evidence of a reason to combine the teachings of AAPA and Suzuki. Pet.
`
`40; Ex. 1002 ¶ 72. Dr. Rubloff, however, offers no underlying facts or data
`
`to support the conclusion that applying the AAPA CMP step to Suzuki’s
`
`semiconductor device would result in such benefits. Such conclusory
`
`
`
`11
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`statements by a declarant are entitled to little or no weight. 37 C.F.R.
`
`§ 42.65(a); see also Ashland Oil, Inc. v. Delta Resins & Refractories, Inc.,
`
`776 F.2d 281, 294 (Fed. Cir. 1985) (stating a lack of objective support for an
`
`expert opinion “may render the testimony of little probative value in [a
`
`patentability] determination”).
`
` Furthermore, when discussing CMP in the Background of the
`
`Invention section, the ’259 patent states:
`
`[A] CMP is utilized to polish the tungsten layer 14 for
`planarization. Unfortunately, the conventional process needs
`long polish time to remove the thick TiN layer 10 and the
`titanium 8. However, the long polish time for planarization
`may cause the erosion effect. Further, it also raises the cost of
`the CMP for removing the tungsten layer 14 in the conventional
`method. Additionally, the PVD titanium deposition process can
`not [sic] achieve high aspect ratio contact in half submicron
`devices.
`
`Ex. 1001, 1:48–55. As Patent Owner points out, the ’259 patent further
`
`explains that “[t]he present invention provides a thinner TiN layer process to
`
`reduce the time for CMP polish. Therefore, the cost of the process is
`
`degraded and the throughput is increased. Further, the erosion problem . . .
`
`generated by long polish time is eliminated by the present invention.” Id. at
`
`3:38–42; Prelim. Resp. 12–13.
`
`At the very least, these portions of the ’259 patent cast doubt on
`
`Petitioner’s conclusion that a person of ordinary skill in the art would have
`
`recognized that the use of CMP for planarizing tungsten and TiN down to
`
`the isolation layer would improve a device formed based on the combined
`
`teachings of Suzuki and Nakanishi and would yield an expected result. Pet.
`
`40 (citing KSR, 550 U.S. at 417). Suzuki discloses a TiN layer having a
`
`thickness up to 2000 Å. Petitioner does not explain adequately why, in view
`
`
`
`12
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`of the negative treatment afforded to conventional CMP in the context of
`
`thick TiN layers, a person of ordinary skill in the art would proceed with a
`
`conventional CMP step, as taught by AAPA, in combination with the steps
`
`for forming a semiconductor device set forth in Suzuki and Nakanishi. Nor
`
`does Petitioner explain adequately why a person of ordinary skill in the art
`
`would planarize the tungsten and TiN layers of Suzuki’s semiconductor
`
`device down to the surface of the isolation layer (as required in claims 1 and
`
`4) when Suzuki expressly states that it aims to achieve a flat tungsten wiring
`
`layer on top of a barrier layer, as shown in Figure 1(c). Ex. 1004 ¶¶ 16–17,
`
`Fig. 1.
`
`Petitioner’s reliance on Mathews or Maury does not cure this
`
`deficiency, as Petitioner does not assert that either reference discloses or
`
`suggests the claimed planarization step.
`
`In view of the foregoing, we determine that the obviousness analysis
`
`proposed in the Petition does not provide sufficiently articulated reasoning,
`
`with rational and/or factual underpinnings, to combine the teachings of
`
`Suzuki, Nakanishi, and AAPA to reach the invention recited in the
`
`challenged claims and, instead, is driven by conclusory reasons to combine
`
`the references. For this reason, we determine that Petitioner has not
`
`established a reasonable likelihood of establishing that independent claims 1
`
`and 4, and therefore claims 2, 3, and 5–10, which depend therefrom, are
`
`unpatentable over the cited prior art.1
`
`
`
`
`1 In view of this, we find that it is unnecessary to address Patent Owner’s
`argument that AAPA is not prior art “consisting of patents or printed
`publications,” and, therefore, cannot form the basis for institution of inter
`partes review. Prelim. Resp. 7.
`
`
`
`13
`
`

`

`IPR2017-00033
`Patent 6,020,259
`
`
`IV. CONCLUSION
`
`Based on the information presented, we conclude that Petitioner has
`
`not demonstrated a reasonable likelihood of prevailing with respect to its
`
`challenges to claims 1–10.
`
`V. ORDER
`
`For the reasons given, it is hereby
`
`ORDERED the Petition is denied.
`
`
`
`PETITIONER:
`
`Naveen Modi
`naveenmodi@paulhastings.com
`
`Joseph Palys
`josephpalys@paulhastings.com
`
`Chetan Bansal
`chetanbansal@paulhastings.com
`
`Arvind Jairam
`arvindjairam@paulhastings.com
`
`
`
`PATENT OWNER:
`
`Craig Kaufman
`ckaufman@tklg-llp.com
`
`Kevin Jones
`kjones@tklg-llp.com
`
`
`
`
`14
`
`

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