ca
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`CO
`
`U.S. UTILITY Patent Application
`e_sn
`PATENT DATE
`0.I.P.E.
`
`SCANNED 4 II
`
`FEB 2 7 144'
`
`APPLICATION NO.
`
`CONT/PRIOR CLASS
`
`SUBCLASS
`
`ART UNIT„ .0 3/ EXAMINER
`
`09/492726
`
`Kim Harde'e
`
`Dual slope ,ser:Ise clock qenerato
`
`PATENT NUMBER
`
`6195302
`
`6195302
`
`/
`
`
`
`PTO-2040
`12/99
`
`ORIG (cid:9) AL
`
`, (cid:9)
`
`ISS ING 9CASSIFICAT1ŠN
`CROS REFERENCE(S)
`
`SS
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`7/0-v (cid:9)
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`tinued on Issue Slip lnsid (cid:9)
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`
`r----1 TERMINAL
`I (cid:9)
`
`I DISCLAIMER
`
`DRAWINA
`
`Sheets D (cid:9) g.
`
`Figs. (cid:9)
`
`g.
`
`11"
`
`Print F' (cid:9) .
`1 ani
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`CLAI (cid:9)
`Total Claims
`
`ALLOWED
`Print Clai (cid:9)
`for 0.G.
`
`cZ
`
`• TICE OF ALLOWANC (cid:9)
`
`AILED
`
` (date)
`
`The term of this patent
`subsequent to (cid:9)
`has been disclaimed.
`fl (cid:9) The term of this patent shall
`not extend beyond the expiration date
`of U.S Patent. No.
`
`'
`
`•
`
`months of
`The terminal (cid:9)
`this patent have been disclaimed.
`
`id (cid:9)
`
`(Assistant Examiner)
`
`-
`
`.....
`HUANHOANG
`PRIMARY EXAMINER
`
`4 (Iv
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`3 (cid:9)
`ISSUE (cid:9)
`Amount Due
`
`)0? ...- (cid:9)
`
`040.
`ISSUE BATCH NUM (cid:9) R
`
`00
`
`1-02.1
`
`WARNING:
`The information disclosed herein may be restricted. (cid:9) Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`Form PTO-436A
`(Rev. 6/99)
`
`FILED WITH:
`
`DISK (CRF)
`
`FICHE El CD-ROM
`
`(Attached in pocket on right inside flap)
`
`---les*Erls6t1A415410ftwod
`
`(FACE)
`
`3113 Ni 33J anssl
`
`Page 1 of 77
`
` SAMSUNG EXHIBIT 1003
`
`(cid:9)
`(cid:9)
`

`
`PATENT APPLICATION SERIAL NO. (cid:9)
`
`
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`02/07/2000 SCARMICH 00000019 09492726
`01 FC:101 (cid:9)
`
`690.00 OP
`
`PTO-1556
`(5/87)
`
`*U.S. GPO: 1999-459-082/19144
`
`Page 2 of 77
`
`

`
`n••••0
`rown"--7:10.
`
`011•0011011.•
`
`0111MINIMINI
`011010110.
`
`0
`
`UTILITY
`PATENT APPLICATION
`TRANSMITTAL
`
`Attorney Docket No.
`
`First Inventor
`
`Express Mail Label No.
`
`UMI 216
`
`E-.
`
`
`Kim C. HARDEE (cid:9) 4
`4:1
`.m 0,--
`„,...
`Tic
`
`EL523824389US (cid:9)
`
`1. (cid:9)
`
`2. (cid:9)
`
`APPLICATION ELEMENTS
`
`1E1 (cid:9)
`
`Fee Transmittal Form
`
`Specification
`- Descriptive
`title of the Invention
`- Cross
`References to Related Applications
`- Statement
`Regarding Fed sponsored R&D
`- Reference
`to Microfiche Appendix
`of the Invention
`- Background
`- Brief Summary
`of the Invention
`- Brief Description
`of the Drawings
`- Detailed
`Description
`- Claim(s)
`- Abstract
`of the Disclosure
`
`3. (cid:9)
`
`'' Drawings
`
`Assistant Commissioner for Patents
`Box Patent Application
`Washington, DC 20231
`
`5.
`
`•
`
`Computer Program (Appendix)
`Microfiche
`Acid Sequence(if applicable)
`6. Nucelotide/Amino
`
`a. • (cid:9)
`Readable Copy
`Computer
`Paper
`b. • (cid:9)
`Copy (identical to computer copy)
`Statement
`c. • (cid:9)
`verifying identity of said copies
`ACCOMPANYING APPLICATION PARTS
`Assignment
`
`Papers (cover sheet/document(s))
`
`7.
`
`i4 (cid:9)
`
`8.
`
`•
`
`9.
`
`•
`1.T.1 (cid:9)
`10.
`
`•
`11.
`
`37 C.F.R.
`§ 3.73(h) Statemt
`
`(when
`an assignee)
`there is
`English
`Translation
`
`IDS &
`
`Form 1449
`
`
`
`Amendment Preliminary
`
`• Power of
`Attorney
`
`Copies of
`IDS Citations
`
`4. (cid:9)
`
`[signed]
`Oath or Declaration
`4 Newly executed
`(original or copy)
`a. (cid:9)
`Return
`Postcard
`(MPEP 503)
`Receipt
`.b. • Copy from
`prior appl. (37 C.F.R. § 1.63(d))
`Small
`
`0 Statement filed in prior
`Entity
`DELETION
`OF INVENTOR(S1
`i. (cid:9) • (cid:9)
`application
`--Status
`and desired
`still proper
`Signed statement attached deleting
`Certified
`of Priority
`14.1
`Document(s)
`Copy
`inventor(s) named in prior application,
`see 37 C.F.R. §§ 1.63(d)(2) and 1.33(b).
`16.0 Other:
`Preliminary
`Amendment;
`Certificate
`of Mailing
`by Express
`NOthlk)R.PrEMS''fi,ii. IN 6 fRogi3:':1,5;), BE ENTITLED idAksyskiALLE0I.
`Mail; and Check
`Fggs, A;siopatkpanysrATO*17--7s.iiRgpOE00:7t#R
`-§:1.2 (cid:9) g>mgAr '
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`for $
`j#.0NtiÉlliEDAIAPAIOiRiA.P.P.LloAteMpRELIEbttIPft(37:CAR:,§
`'Utt):
`16. If a CONTINUING
`APPLICATION,
`
`i4 (cid:9)
`12.
`13.0
`
`provisional No. 060/118,737 filed Feb. 5, 1999,
`CI with
`• CIP (cid:9)
`0 Divisional (cid:9)
`priority of
`0 Continuation
`OR DIVISIONAL APPS only:
`prior application,
`disclosure of the
`The entire
`FOR CONTINUATION
`from which an oath
`continuation or
`or declaration is supplied under Box 4b, is considered
`of the accompanying
`the disclosure
`a part of
`divisional application and is hereby incorporated by
`can only be relied
`The incorporation
`reference.
`upon when a
`portion has been inadvertently omitted form the submitted
`parts.
`application
`17. CORRESPONDENCE ADDRESS
`• Customer Number of Bar Code Label (cid:9)
`or
`(cid:9) Correspondence address below
`
`Name
`
`William J. KUBIDA, Esq. (cid:9)
`
`.
`
`Address
`
`City
`
`Country
`
`Hogan & Hartson, LLP
`
`1200 17th Street, Suite 1500
`
`Denver
`
`US
`
`State
`
`Telephone
`
`CO
`(719) 448-5909
`
`Zip
`
`Fax
`
`80202
`(719) 448-5922
`
`Name (Print/Type)
`
`Carol W. Burton
`
`Registration No.
`
`35,465
`
`(Signature)
`
`942 A
`
`1
`
`Date
`
`January Z 7 (cid:9)
`
`, 2000
`
`80450/20 -#78084 vi
`
`Page 3 of 77
`
`

`
`Attorney Docket No. UMI 216
`Client Matter No. 80450.0020.001
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Non-Provisional Application of:
`
`Kim C. HARDEE
`
`Serial No.
`
`Filed: January 27, 2000
`
`For: DUAL SLOPE SENSE CLOCK
`GENERATOR
`
`Examiner:
`
`Art Unit:
`
`CERTIFICATE OF MAILING BY EXPRESS MAIL
`
`Assistant Commissioner for Patents
`Washington, D.C. 20231
`
`Sir:
`
`The undersigned hereby certifies that the attached
`1. Utility Patent Application Transmittal;
`2. Fee Transmittal for FY 2000;
`3. Check for $730.00;
`4. Specification, Claims, Abstract and Drawings;
`5. Information Disclosure Statement, Form 1449 and
`Copies of References;
`6. Patent Assignment Recordation Cover Sheet,
`Assignment;
`7. Certificate of Mailing by Express Mail; and
`8. Return Card,
`
`relating to the above application, were deposited as "Express Mail," Mailing
`Label No. EL523824517US with the U.S. Postal Service, addressed to
`Attention: Box Patent Application, Assistant Commissioner for Patents,
`Washington, D.C. 20231, on January 27, 2000.
`
`January 27, 2000
`
`January 27, 2000
`
`Mailer
`
`Carol W. Burto , Reg. No. 35465
`Hogan & Hartson LLP •
`1200 17th Street, Suite 1500
`Denver, Colorado 80202
`(303) 454-2454 (telephone)
`(303) 899-7333 (facsimile)
`
`\\\DE - 80450/20 -#78080 vi
`
`Page 4 of 77
`
`

`
`FEE TRANSMITTAL (cid:9)
`for FY 2000
`
`TOTAL AMOUNT OF PAYMENT ($)
`
`730.00
`
`I
`Application Number
`
`Filing Date
`
`First Named Inventor
`
`Examiner Name
`Group /Art Unit
`Attorney Docket No.
`
`Complete if Known
`
`January 27, 2000
`Kim C. HARDEE
`
`UMI 216
`
`METHOD OF PAYMENT check one)
`The Commissioner is hereby authorized
`to charge indicated
`
`fees and credit any over payments to:
`50-1123
`
`FEE CALCULATION (continued)
`3. ADDITIONAL FEES
`Entity (cid:9)
`Entity
`Fee
`Fee (cid:9)
`($) (cid:9)
`($) (cid:9)
`
`Fee Description (cid:9)
`
`Fee Paid
`
`130 (cid:9)
`
`50 (cid:9)
`
`130 (cid:9)
`
`2,520 (cid:9)
`
`65 (cid:9)
`
`25 (cid:9)
`
`Surcharge — late filing fee or oath
`
`Surcharge—late provisional filing fee
`or cover sheet
`
`130 (cid:9)
`
`Non-English specification
`
`2,520 (cid:9)
`
`For filing a request for reexamination
`
`920* (cid:9)
`
`920* (cid:9)
`
`Requesting publication of SIR prior to
`Examiner action
`
`1,840* (cid:9)
`
`1,840* (cid:9)
`
`110 (cid:9)
`
`380 (cid:9)
`
`870 (cid:9)
`
`1,360 (cid:9)
`
`55 (cid:9)
`
`190 (cid:9)
`
`435 (cid:9)
`
`680 (cid:9)
`
`Requesting publication of SIR after
`Examiner action
`
`Extension for reply within first month
`
`Extension for reply within second
`month
`
`Extension for reply within third month
`
`Extension for reply within fourth
`month
`
`1,850 (cid:9)
`
`925 (cid:9)
`
`Extension for reply within fifth month
`
`300 (cid:9)
`
`300 (cid:9)
`
`260 (cid:9)
`
`150 (cid:9)
`
`Notice of Appeal
`
`150 (cid:9)
`
`Filing a brief in support of an appeal
`
`130 (cid:9)
`
`Request for oral hearing
`
`1 .III
`
`. Deposit
`Account
`Number
`
`Deposit
`Account
`Name
`
`2.12g
`
`Hogarr& Hartson L.L.P.
`
`. Charge Any Additional Fee
`§ § 1.16 and 1.17
`Payment Enclosed:
`
`Required Under 37 CFR
`
`Check (cid:9)
`
`Money
`Order
`FEE CALCULATION.
`
`El Other
`
`1. BASIC FILING FEE
`Entity Fee (cid:9)
`Entity Fee (cid:9)
`($) (cid:9)
`($)
`
`Fee Description
`
`690 (cid:9)
`
`310 (cid:9)
`
`480 (cid:9)
`
`690 (cid:9)
`
`150 (cid:9)
`
`345 (cid:9)
`
`Utility Filing Fee
`
`155 (cid:9)
`
`Design filing fee
`
`240 (cid:9)
`
`Plant filing fee
`
`345 (cid:9)
`
`Reissue filing fee
`
`75 (cid:9)
`
`Provisional filing fee
`
`Fee Paid
`
`690.00
`
`SUBTOTAL (1)
`
`($)690.00
`
`1,510 (cid:9)
`
`1,510 (cid:9)
`
`Petition to institute a public use
`proceeding
`
`2. EXTRA CLAIM FEES
`
`11
`
`Total Claims
`Independent
`Claims
`Multiple Dependent
`
`3
`
`Fee from
`below (cid:9)
`
`Extth Claims (cid:9)
`-20**=
`0
`
`X
`
`-3**=
`
`0
`
`Fee Paid
`0
`
`0
`
`0
`
`=
`
`=
`
`=
`
`Fee Description
`
`
`**or number previously paid, if greater; For Reissues, see below
`Large Entity Small Entity
`Fee (cid:9)
`Fee (cid:9)
`Fee (cid:9)
`Fee (cid:9)
`Code (cid:9)
`($) (cid:9) Code (cid:9)
`($)
`18 (cid:9)
`203 (cid:9)
`78 (cid:9)
`260 (cid:9)
`78 (cid:9)
`
`103 (cid:9)
`102 (cid:9)
`104 (cid:9)
`109 (cid:9)
`
`9 (cid:9)
`39 (cid:9)
`130 (cid:9)
`39 (cid:9)
`
`202 (cid:9)
`204 (cid:9)
`209 (cid:9)
`
`Claims in excess of 20
`
`Independent claims in excess of 3
`
`Multiple dependent claim, if not paid
`
`**Reissue independent claims over
`
`original patent
`
`110 (cid:9)
`
`1,210 (cid:9)
`
`1,210 (cid:9)
`
`430 (cid:9)
`
`580 (cid:9)
`
`130 (cid:9)
`
`50 (cid:9)
`
`240 (cid:9)
`
`40 (cid:9)
`
`760 (cid:9)
`
`760 (cid:9)
`
`55 (cid:9)
`
`Petition to revive — unavoidable
`
`605 (cid:9)
`
`Petition to revive — unintentional
`
`605 (cid:9)
`
`Utility issue fee (or reissue)
`
`215 (cid:9)
`
`Design issue fee
`
`290 (cid:9)
`
`Plant issue fee
`
`130 (cid:9)
`
`50 (cid:9)
`
`240 (cid:9)
`
`40 (cid:9)
`
`380 (cid:9)
`
`380 (cid:9)
`
`Petitions to the Commissioner
`
`Petitions related to provisional
`applications
`
`Submission of Information Disclosure
`Stmt
`
`Recording each patent assignment
`per property (x number of properties)
`
`Filing a submission after final
`rejection (37 CFR § 1.129(a))
`
`For each additional invention to be
`examined (37 CFR § 1.129(b))
`
`Other fee (specify)
`
`Other fee (specify)
`
`40.00
`
`110 (cid:9)
`
`18 (cid:9)
`
`210 (cid:9)
`
`9 (cid:9)
`
`**Reissue claims in excess of 20
`and over original patent
`
`SUBTOTAL (2)
`
`($)0.00
`
`*Reduced by Basic Fling Fee Paid (cid:9)
`
`SUBTOTAL (3)
`
`($)40.00
`
`SUBMITTED BY
`Name (PrinVType) ,- arol W.
`C,
`\s.........et (cid:9)\...
`I
`
`Signature
`
`on
`
`No.
`
`(Attorney/Agent) Agent)
`(Attorney/Agent)
`
`35,465
`
`Complete (if applicable)
`(303) 454-2454
`
`Telephone
`
`Date
`
`Jan. 27, 2000
`
`\ \DE - 80450/20 -#78098 vi
`
`Page 5 of 77
`
`

`
`DUAL SLOPE SENSE CLOCK GENERATOR
`TLS ft-t?lp (cid:9)
`P a •407/ los 751-4 .(elf, (cid:9)
`eo ?Pray; yise (cid:9)
`BACKGROUND OF THE INVENTION
`
`NV.
`
`1.
`
`Field of the Invention.
`
`The present invention relates, in general, to integrated circuits and,
`
`5 (cid:9) more particularly, to sense amplifiers in integrated circuit memory devices.
`
`2.
`
`Relevant Background.
`
`Semiconductor memory devices include sense amplifiers to sense
`
`weak signal levels from storage capacitors and amplify those weak signals to
`
`levels sufficient to drive other circuitry. Similar devices are used in other
`
`10 (cid:9)
`
`integrated circuit devices that sense, hold, and amplify signal levels. In a
`
`typical dynamic random access memory (DRAM) circuit, a data bit is stored
`
`as charge in a storage capacitor. A number of these storage capacitors are
`
`served by a single sense amplifier. During reading, writing, and refresh
`
`operations appropriate addressing signals are applied to couple one of the
`
`15 (cid:9)
`
`capacitors through a bit line to a latch node of the sense amplifier. Before
`
`accessing one of the capacitors, the bit lines are equalized to a selected
`
`precharge voltage during a precharge operation. The selected precharge
`
`voltage is usually a voltage midway between logic high level and a logic low
`
`level.
`
`20 (cid:9)
`
`When an address-selected capacitor is coupled to one of the bit lines
`
`feeding into a sense amplifier the charge stored in the capacitor alters the
`
`signal on the bit line moving it incrementally towards either a logic high or a
`
`logic low level. Because it is desirable to make the storage capacitor as small
`
`as possible, the bit line may only move a few hundred millivolts or less from
`
`25 (cid:9)
`
`the equalization level. The sense amplifier serves to amplify this small signal
`
`level to drive the bit line to either a logic high or logic low voltage level
`
`1
`
`Page 6 of 77
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`depending on the direction in which the bit line moved with respect to the
`
`equalization level.
`
`Sense amplifiers typically comprise a latch circuit formed, for example,
`
`by a pair of cross-coupled high gain inverters. A typical latch circuit has two
`
`5 (cid:9)
`
`latch nodes that each serve as a differential input coupled to sense a signal
`
`on the bit line during sensing to drive the bit line to the logic levels. It is
`
`desirable that sense amplifiers accurately sense the bit line signal and quickly
`
`set the latch outputs. During read operations, each latch output is coupled to
`
`a data input/output (I/O) line by a pass transistor as soon as the latched
`
`10 (cid:9)
`
`output is available. To reduce access time, it is desirable to activate the pass
`
`transistor as soon as possible after the latch output is stable. Also, it is
`
`desirable to make the pass transistor relatively large to couple the latched
`
`signal to the data line quickly and with little signal loss. However, to use a
`
`large pass transistor the latch must be strong in order to hold the latched
`
`15 (cid:9)
`
`signal when coupled to the parasitic load presented by the data lines.
`
`The latches within the sense amplifiers typically comprise P-channel
`
`field effect transistors (FETs) coupled to a positive power supply such as VD D
`
`by a P-channel FET driver switch, also referred to as a "high-side" driver.
`
`Similarly, N-channel FETs in the latches are coupled to a relatively negative
`
`20 (cid:9)
`
`power supply (such as V 5 or ground) using an N-channel driver switch, also
`referred to as a "low-side" driver. For convenience, the latch power supply
`
`nodes are designated herein as an LN node (i.e., a node coupling the low-
`
`side driver switch to the N-channel FET devices within the latch) and an LP
`
`node (i.e., a node coupling the P-channel FET devices within the latch to the
`
`25 (cid:9)
`
`high-side driver switch).
`
`In a standby or precharge mode the driver switches are turned. off so
`
`that the latch lacks sufficient power to drive a signal on the latch output
`
`nodes. In this standby mode, the latch input nodes follow the signal to be
`
`sensed. To read data from the memory cell, the driver transistors are turned
`
`2
`
`7--
`
`Page 7 of 77
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`on thereby enabling the latch to amplify the sensed signal on the bit lines and
`
`drive the latch output nodes to appropriate logic levels.
`
`In DRAM devices, for example, rapid driver turn-on can cause the
`
`sense amp to latch to an incorrect state due to the effects of capacitance and
`
`5 (cid:9)
`
`transistor imbalances within the sense amplifier. During overly rapid turn on,
`
`parasitic coupling through transistors in each sense amplifier may pull both
`
`differential latch nodes of the sense amplifier toward either a logic HIGH or
`
`logic LOW depending on whether lower drive transistors or upper drive
`
`transistors turned on first. Because one of the drive transistors is typically
`
`10 (cid:9)
`
`implemented using N-channel devices and the other using P-channel devices,
`
`it is common that the N-channel side will turn on first. To counter this problem
`
`the driver transistors are desirably activated slowly during initial sensing to
`
`allow the sense amplifier to accurately latch the bit line value. However, after
`
`initial sensing has begun, the sense amps are preferably turned on hard to
`
`15 (cid:9)
`
`quickly amplify the differential voltage on the latch nodes (i.e., the bit lines) to
`
`minimize access time. This type of sensing is referred to herein as "dual-
`
`speed" sensing.
`
`In many DRAM designs, the LN and LP nodes are shared among a
`
`plurality of sense amplifiers. These designs allow the driver switches to be
`
`20 (cid:9)
`
`implemented with large, low impedance switches. By low impedance it is
`
`meant that they are low impedance with respect to the transistors in the latch
`
`itself including pass transistors that couple the latch output nodes to the data
`
`line. These strong driver switches ensure that the sense amplifiers can be
`
`turned on hard when necessary. Dual-speed sensing is provided by
`
`25 (cid:9)
`
`implementing the driver switch with two or more transistors of different size.
`
`For example, a small transistor having high on-resistance is activated first to
`
`provide the initial sensing. After a preselected delay, a larger transistor
`
`having low on-resistance is activated to turn the latch devices on hard.
`
`However, shared drivers result in long LN and LP lines in large
`
`30 memory devices such as 64M, 256M, and larger memory arrays. Parasitic
`
`3
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`Page 8 of 77
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`(cid:9)
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`
`impedance in the long lines results in voltage drops or sagging when a high
`
`current flows in the LN and/or LP lines. An example case is illustrated by a
`
`group of sense amplifiers sharing LN and LP lines, in which only one sense
`
`amplifier at the end of long LN and LP line is trying to sense a "0" and all
`
`5 (cid:9)
`
`other sense amplifiers are sensing a "1". When the sense amplifiers are
`
`simultaneously activated, the large number of sense amplifiers that are
`
`sensing a logic "1" will disturb the voltage at distant locations on the LN line.
`
`A sense amplifier that is coupled to that portion of the LN line will take longer
`
`to sense a logic "0". Hence, the sense amplifier performance is sensitive to
`
`10 (cid:9)
`
`the pattern of l's and O's stored in the memory. To accommodate this pattern
`
`sensitivity, the DRAM must be operated using access timing that will allow the
`
`slowest sense amplifier to accurately sense and drive the stored value
`
`regardless of the pattern. It is desirable to minimize pattern sensitivity to
`
`improve, cell access speed.
`
`15 (cid:9)
`
`To minimize pattern sensitivity, each sense amplifier may be provided
`
`with its own local driver transistors. In a typical memory device the power
`
`supply busses are distributed throughout the chip area. Each sense amplifier
`
`can be coupled to a nearby power supply bus using short, low impedance
`
`interconnect through a local drive transistor. However, the local drive
`
`20 (cid:9)
`
`transistors must be significantly smaller than the shared drive transistors.
`
`These smaller drive transistors limit the sense amplifier's ability to drive the
`
`data I/O line. High switching current in the latch can destabilize the sense
`
`amplifier by allowing the LN and LP nodes to drift impermissibly far from the
`
`power supply bus voltages.
`
`25 (cid:9)
`
`It is not practical to implement dual slop sensing using the dual
`
`transistor technique described above in a local drive transistor design.
`
`because of the chip area consumed by two transistors required for each
`
`sense amplifier. Instead, dual speed sensing is provided with local drive
`
`switches by generating control signals to the driver transistors that settle
`
`30 (cid:9)
`
`temporarily at a level between a logic low (i.e., Vss) and a logic high (i.e., VDD).
`
`4
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`Page 9 of 77
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`

`
`After a predetermined delay time, the control signals continue to the full logic
`
`levels to turn the driver transistors, and so the latch devices, on hard. This
`
`type of design is described in U.S. Patent No. 5,334,890 titled "SENSE
`
`AMPLIFIER CLOCK DRIVER" issued August 2, 1994 and incorporated herein
`
`by reference. This design distributes the driver transistors reducing pattern
`
`sensitivity. However, to provide sufficiently stable LN and LP nodes the
`
`control signals to the local drive transistors must have carefully controlled
`
`signal levels, timing, and slew. Hence, local driver designs require relatively
`
`complex control circuitry that increases the overall size overhead of the
`
`10 (cid:9)
`
`design to levels that may be inappropriate for some applications.
`
`A need remains for a sense amplifier design and method for operating
`
`a sense amplifier that provides dual slope sensing and is compatible with
`
`large shared driver designs as well as local driver designs that offer pattern
`
`insensitivity. Moreover, a need exits for a high speed sense amplifier that can
`
`15 (cid:9)
`
`be implemented with simple, compact circuitry for high capacity memory
`
`designs.
`
`SUMMARY OF THE INVENTION
`
`The present invention involves a memory circuit having a plurality of
`
`sense amplifiers where each amplifier includes a power node for receiving
`
`20 (cid:9)
`
`current from a power supply. One or more driver switches couple each power
`
`node to 'a power supply bus node. The power nodes of a plurality of the
`
`plurality of sense amplifiers are coupled together to provide a shared power
`
`node. Pass transistors are used to couple output nodes of each of the
`
`plurality of sense amplifiers to data lines. A sense clock circuit provides a
`
`25 (cid:9)
`
`control signal to the one or more driver switches such that the control, signal
`
`comprises an initial phase with a preselected initial rate of voltage change
`
`and a final phase with a rate of voltage change that is faster than the initial
`
`rate of change.
`
`5
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`Page 10 of 77
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`

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`In another aspect the present invention involves a method for
`
`operating a memory device by generating a dual slope control signal for
`
`controlling the operation of sense amplifier driver transistors in an integrated
`
`circuit memory device. A sense amplifier drive transistor is provided having a
`
`control terminal coupled to receive the control signal and having a power
`
`node for supplying current to a preselected number of sense amplifiers. The
`
`control signal is placed at a level selected to turn off the driver transistors. A
`
`signal to be sensed is coupled to a latch node of the sense amplifier and
`
`charge is supplied from an external power supply to the sense amplifier driver
`
`10 (cid:9)
`
`transistor through a first impedance. After a delay, additional charge is
`
`supplied to the sense amplifier driver transistor through a second impedance
`
`at a second rate.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shows a group of sense amplifiers in a memory circuit in
`
`15 (cid:9)
`
`accordance with the present invention;
`
`FIG. 2 illustrates in schematic diagram form a portion of a memory
`
`device including an embodiment in accordance with the present invention;
`
`FIG. 3 shows a timer circuit generating clock signals in accordance
`
`with the present invention; and
`
`20 (cid:9)
`
`FIG. 4 illustrates waveforms resulting for an embodiment of the present
`
`invention.
`
`DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
`
`The present invention involves a memory device having a sense
`
`amplifier with LN and LP nodes shared among a number of sense amplifiers.
`
`25 (cid:9)
`
`In one embodiment, local drive transistors (i.e., drive transistors associated
`
`with each sense amplifier) supply current to the shared LN and LP nodes. In
`
`an alternative embodiment, a single drive transistor is associated with each
`
`6
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`Page 11 of 77
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`

`
`shared LN and LP node and drives current to the associated node. A timer
`
`circuit generates control or clock signals to the control electrodes of the local
`
`drive switches such that the control signal has a first phase with slow rate of
`
`change (e.g., dv/dt) and a final phase with higher rate of change. It is
`
`5 (cid:9)
`
`contemplated that more than two phases may be used, but it is significant that
`
`the initial phase allow for slow, gentle turn on while the sense amplifiers are
`
`sensing the stored signal and the final phase allows for rapid turn on to
`
`increase access speed.
`
`Inaccordance with the local drive transistor implementation of the
`
`10 (cid:9)
`
`present invention, the drive transistors are distributed so that they are
`
`physically and electrically close to each sense amplifier providing improved
`
`pattern sensitivity in large memory devices. Also, shared LN and LP nodes
`
`enable the local drive transistors to operate cooperatively in parallel to
`
`provide 'a strong (i.e., low impedance) coupling between the sense amplifiers
`
`15 (cid:9)
`
`and the power supply nodes thereby enhancing sense amplifier stability and
`
`sensing speed.
`
`FIG. 1 illustrates a portion of a memory device, shown generally at
`
`100, in accordance with the present invention. A group of sense amplifiers
`
`101a-101c are shown, but more or fewer sense amplifiers may be included in
`
`20 (cid:9)
`
`a group of sense amplifiers. Sense amplifiers 101a-101c include a pair of p-
`
`channel transistors and a pair of n-channel transistors. The gate electrode of
`
`one p-channel transistor is coupled to the gate electrode of one of the n-
`
`channel transistors to form a first latch node 102. The gate electrode of the
`
`other p-channel transistor is coupled to the gate electrode of the other n-
`
`25 (cid:9)
`
`channel transistor to form a second latch node 103. Additional circuitry that
`
`couples latch nodes 102 and 103 to bit lines and data I/O lines is described in
`
`greater detail with reference to FIG. 3. FIG. 1 illustrates the present invention
`
`embodied in a dynamic random access memory (DRAM). Other types of
`
`memory devices and integrated circuitry can, however, make use of the
`
`30 (cid:9)
`
`teachings of the present invention.
`
`7
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`Page 12 of 77
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`
`A significant feature in accordance with the present invention as shown
`
`in FIG. 1 is that local driver transistors 104 and 106 are provided for each
`
`sense amplifier 101a-101c, but the LN and LP nodes are also shared among
`
`a plurality of sense amplifiers 101a-101c. As described in greater detail
`
`5 (cid:9)
`
`hereinafter, a control signal (LPB) driving transistors 104 comprises a dual-
`
`slope signal. Similarly, a control signal (LNB) driving transistors 106
`
`comprises a dual-slope signal. The configuration in accordance with the
`
`present invention allows the local driver transistors 104 and 106 to be small to
`
`reduce overall chip area. Yet, because local drive transistors 104 and 106
`
`10 (cid:9)
`
`are coupled in parallel via the shared LN and LP nodes, they operate
`
`cooperatively to provide sufficient drive capacity to stabilize the LN and LP
`
`nodes during switching. This feature simplifies the requirements placed on
`
`the LNB and LNP signals resulting in simplified control circuitry (shown in FIG.
`
`3).
`
`15 (cid:9)
`
`FIG. 2 shows a single sense amplifier 101 with associated circuitry
`
`typical in a DRAM application. Storage capacitors 201 are selectively
`
`coupled to bit lines 202 through access switches 203 in response to address
`
`signals supplied to word lines 204. In FIG. 2, signal lines are labeled with
`
`mnemonic labels to ease understanding. In general, an "R" suffix indicates a
`
`20 (cid:9)
`
`right-side signal line and an "L" suffix indicates a left-side signal line.
`
`Complementary signals are identified with a "B" (i.e., bar) suffix indicating that
`
`the signal is inverted. Word lines are identified as "WL", bit lines as "BIT",
`
`and latch nodes as "LAT". Operations described in terms of either a left side
`
`or right side components are readily implemented on the other side in a
`
`25 (cid:9)
`
`similar manner.
`
`Just prior to a read operation, a pair of bit lines 202 such as left-side
`
`non-inverted bit line labeled BITL and inverting bit line BITLB are equalized at
`
`some voltage between a logic high and a logic low signal. In operation, when
`
`one word line 204 (labeled WL) is activated, a selected storage capacitor 201
`
`30 (cid:9)
`
`is coupled to a bit line and incrementally moves the bit line to a relatively
`
`8
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`Page 13 of 77
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`(cid:9)
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`(cid:9)
`

`
`positive or relatively negative voltage depending on the stored charge. The
`
`terms "relatively positive" and "relatively negative" mean relative voltage
`
`levels with respect to the equalized voltage.
`
`To access a storage capacitor 201 on the left side, left side bit lines
`
`5 BITBL and BITL are coupled to the latch nodes LATB and LAT through
`
`transistor 206 by activation of the isolation left (ISOL) signal line. Similarly,
`
`right side bit lines BITBR and BITR are coupled to latch nodes LATB and LAT
`
`through transistors 207 by activation of the isolation right (ISOR) signal line.
`
`In typical operation, once the ISOL or ISOR signal is set, the appropriate WL
`
`10 (cid:9)
`
`is activated to couple the storage capacitor 201 to the LAT or LATB node of
`
`sense amp 101.
`
`Shortly after the WL signal is activated, the LPB signal is driven to a
`
`logic low coupling VCCI to sense amp 101 through drive transistor 104.
`
`Similarly, the LNB signal is driven high to couple sense amp 101 to ground or
`
`15 VSS through drive transistor 106. As described hereinbefore, LPB and LNB
`
`signals drive a number of transistors 104 and 106, respectively. Preferably,
`
`LNB and LPB are generated by a circuit such as that shown in FIG. 3 that
`
`generates LNB and LBP both as dual slope signals. Once sense amp 101 is
`
`powered the signals on LAT and LATB begin to separate under the influence
`
`20 (cid:9)
`
`of sense amp 101. As this separation occurs, the rate of change in the LNB
`
`and LPB signals (e.g., dv/dt) can increase to drive LAT and LATB quickly to
`
`the appropriate logic levels. The column select signal, labeled YSE in FIG. 2,
`
`is activated to couple the LAT and LATB signals to the data line (D) and
`
`inverted data line (DB) respectively.
`
`25 (cid:9)
`
`FIG. 3 shows in block diagram form a circuit useful in generating the
`
`dual slope LPB and LNB control signals described hereinbefore. As shown in
`
`FIG. 3, a sense right (SENR) or sense left (SENL) signal is applied to logic
`
`gate 301. Logic gate 301 is implemented as a NOR gate in the preferred
`
`embodiment, although other logic gates or a combination of logic gates may
`
`30 (cid:9)
`
`be convenient in other applications. Logic gate 301 logically combines the
`
`9
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`Page 14 of 77
`
`

`
`SENR and SENL signals to form an intermediate sense amplifier control
`
`signal on node 302.
`
`In operation, one of the input signals SENR or SENL will go to a logic
`
`high when sensing is to begin and then goes to a logic low during precharge
`
`5 or standby mode. The SENR and SENL signals are derived from, for
`
`example, the row address strobe (RAS). During standby, when both SENR
`
`and SENL are low, the control signal on node 302 is a logic high. Soon after
`
`either SENR or SENL goes high, the signal on node 302 will transition to a
`
`logic low.-
`
`10
`
`The signal on node 302 is inverted by inverter 304 and applied to the
`
`control node of transistor 303. Hence, shortly after either SENR or SENL
`
`goes high, transistor 303 is turned on pulling the LPB signal low through
`
`resister 306. Similarly, when the signal on node 302 goes low, transistor 313
`res.is.+vr
`is turned on pulling the LNB signal high through Ar4,24ester 316. Resistor 316
`res st?) r
`controls the rate of change or dv/dt of LNB while paeicater 306 controls the
`
`0 15
`
`dv/dt of LPB.
`
`After a delay determined by delay element 307, transistor 308 will be
`
`turned on pulling LPB to ground with a much lower resistance. When
`
`transistor 308 is turned on, LPB will fall to the ground voltage with a high
`
`20 (cid:9)
`
`dv/dt. Similarly, after a delay determined by delay unit 317, transistor 318 will
`
`be turned on to pull the LNB signal to VCCI rapidly without the dv/dt limiting
`
`effect of resistor 316 described hereinbefore.
`
`In a typical application, transistor 308 will be sized much larger than
`
`transistor 303 and transistor 318 will be sized to be much larger than
`
`25 (cid:9)
`
`transistor 313. In the particular example, th