United States Patent
`Tobita
`
`[19]
`
`[11] Patent Number:
`
`4,980,799
`
`[45] Date of Patent:
`
`Dec. 25, 1990
`
`[54] ELECTROSTATIC CAPACITY DEVICE IN
`SEMICONDUCTOR MEMORY DEVICE,
`AND APPARATUS FOR AND METHOD OF
`DRIVING SENSE AMPLIFIER USING
`ELECTROSTATIC CAPACITY DEVICE
`
`Inventor: Youichi Tobita, Hyogo, Japan
`[75]
`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo, Japan
`
`[21] Appl. No.: 459,998
`
`Jan. 4, 1990
`[22] Filed:
`[30]
`Foreign Application Priority Data
`Jan. 18,1989 [JP]
`Japan ...................................... 1-9039
`Apr. 10,1939 [JP]
`Japan .................................. .. 1-91021
`
`[51]
`
`Int. Cl.5 ....................... H01G 4/06; GllC 11/40;
`HOIL 27/04
`[52] U.S.. Cl. .................................... 361/311; 307/530;
`.
`29/25.03; 365/182
`[58] Field of Search ................................ 361/311-313;
`29/571; 357/51, 65, 22, 23.6, 45, 71; 365/144,
`149, 189, 158, 174, 182, 189.05, 193, 203, 205,
`207, 210, 226; 307/362, 530
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,348,746 9/1982 Okabayashi et al.
`4,658,158 4/1987 Chan et al.
`......
`4,777,625 10/1988 Sakui et al.
`.
`
`............... 365/182
`. 307/530
`365/207
`
`OTHER PUBLICATIONS
`
`thorough countermeasures against noise” Nikkei Elec-
`tronics, No. 455, 1988, Sep. 5., pp. 133-136.
`
`Primary Examiner-Donald A. Griffin
`Attorney, Agent, orFirm—Lowe, Price, Leblanc, Becker
`& Shur
`
`ABSTRACT
`[57]
`An apparatus (50) activates and drives sense amplifiers
`in a dynamic random access memory (DRAM) at a high
`speed. The sense amplifier includes a P-MOS sense
`amplifier (15, 16) and an n-MOS sense amplifier (18, 19).
`The P-MOS sense amplifier is connected to a power line
`(31) through a first switching element (22) to be acti-
`vated while the n-MOS sense amplifier is connected to
`a ground line (30) through a second switching element
`(20) to be activated. The sense amplifier driving appara-
`tus includes a capacitor (34) conneced between the
`power line and the ground line. This enables compensa-
`tion for the charge and discharge currents which flow
`in the bit line charging and discharging operations,
`reduction in the bit line charging and discharging times,
`and suppression of the fluctuation in supply potential,
`improving the operating speed of the DRAM. This
`capacitor (34) has an electrode and a dielectric which
`are made of the same materials with those of a memory
`cell capacitor (6) comprised in a memory cell, and the
`dielectric is formed to be of the same film thickness also
`as that of the memory cell capacitor. The memory cell
`has a stack-type structure, where the capacitor com-
`prises at least two capacitance elements connected in
`series.
`
`“32KX8 bits fast SRAM; 10 ns accomplished with
`
`9 Claims, 13 Drawing Sheets
`
`POTENTIAL
`ON SIGNAL
`LINE l7
`
`POTENTIAL ON
`CONNECTION
`NODE 35
`
`Page 1 of 26
`
` SAMSUNG EXHIBIT 1009
`
`

`
`US. Patent
`
`Dec. 25, 1990
`
`Sheet 1 of 13
`
`4,980,799
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`Page 2 of 26
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`

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`US. Patent
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`Dec. 25, 1990
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` Sheet 2 of 13
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`4,980,799
`
`8300330 A
`
`ISENSEI‘AMPLIFIERI
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`Page 3 of 26
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`

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`US. Patent}
`
`Dec. 25, 1990
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`Sheet 3 of 13
`
`4,980,799
`
`FIG. 3
`
`PRIOR ART
`
`Page 4 of 26
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`

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`US. Patent
`
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`
`Sheet 4 of 13
`
`PRIOR ART
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`Page 5 of 26
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`

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`US. Patent
`
`Dec.25, 1990
`
`Sheet 5 of 13
`
`4,980,799
`
`FIG.5 PRIOR ART
`
`Page 6 of 26
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`

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`US. Patent
`
`Dec.25, 1990
`
`Sheet 6 of 13
`
`FIGS
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`Page 7 of 26
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`

`
`U.S. Patent
`
`Dec.25, 1990
`
`POTENTIAL
`ON SIGNAL
`LINE 17
`FIG. 7(b)
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`POTENTIAL ON
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`NODE 36
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`FIG. 7(c)
`
`Page 8 of 26
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`

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`US. Patent
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`Dec. 25, 1990
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`Sheet 8 of 13
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`4,980,799
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`Page 9 of 26
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`

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`U.S. Patent
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`Dec. 25, 1990
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`Sheet 9 of 13
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`4,980,799
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`FIGJOA
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`Page 10 of 26
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`

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`US. Patent
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`Dec. 25, 1990
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`Sheet 10 of 13
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`4,980,799
`
`8
`1 10 a
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`106a
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`Page 11 of 26
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`

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`US. Patent
`
`Dec. 25, 1990
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`Sheet 11 of 13
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`4,980,799
`
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`Page 12 of 26
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`

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`US. Patent
`
`Dec. 25, 1990
`
`Sheet 12 of 13
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`4,980,799
`
`F-'1G.17
`
`STEP-DOWN
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`108h
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`
`Page 13 of 26
`
`

`
`U.S. Patent
`
`Dec. 25, 1990
`
`Sheet 13 of 13
`
`4,980,799
`
`I TO SEMICONDUCTOR
`02 I SUBSTRATE
`I
`
`Page 14 of 26
`
`

`
`1
`
`4,980,799
`
`2
`vating signal 435 and the like, as will be described later in
`detail.
`
`ELECTROSTATIC CAPACITY DEVICE IN
`SEMICONDUCTOR MEMORY DEVICE, AND
`APPARATUS FOR AND METHOD OF DRIVING
`SENSE AMPLIFIER USING ELECTROSTATIC
`CAPACITY DEVICE
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention generally relates to semicon-
`ductor memory devices, and more particularly, to im-
`provements of an electrostatic capacity device in a
`semiconductor memory device. More specifically, the
`present invention relates to a structure for providing a
`fast sensing operation in which a read-out potential
`appearing on a bit line in selecting a word line is de-
`tected and amplified, with the use of the improved elec-
`trostatic capacity device.
`‘
`2. Description of the Background Art
`FIG. 1 is a diagram exemplifying a schematic struc-
`ture of an entire read-out portion in a conventional
`dynamic random access memory. Referring to FIG. 1,
`the dynamic random access memory comprises a mem-
`ory cell array MA constituted of memory cells arranged
`in a matrix of rows and columns and each storing infor-
`mation, an address buffer AB responsive to an exter-
`nally applied external address for generating an internal
`address, an X decoder ADX for decoding an internal
`row address received from the address buffer AB for
`selecting a corresponding row in the memory cell array
`MA, and a Y decoder ADY for decoding an internal
`column address received from the address buffer AB for
`selecting a column corresponding thereto in the mem-
`ory cell array MA.
`The address buffer AB receives a row address speci-
`fying a row in the memory, cell array MA and a column
`address specifying a column in the memory cell array
`MA in a time division multiplexing manner and gener-
`ates the internal row address and the internal column
`address at predetermined timings to apply them to the X
`decoder ADX and to the Y decoder ADY, respec-
`tively.
`To read out data in a memory cell specified by the
`external address, the dynamicrandom access memory
`further comprises a sense amplifier for detecting and
`amplifying data in the memory cells connected to a row
`selected by a decoded row address signal from the X
`decoder ADX, an input/output interface (I/O) respon-
`sive to a decoded column address signal from the Y
`decoder ADY for transmitting data of a selected mem-
`ory cell among the memory cells connected to these-
`lected single row, and connected to the corresponding
`column, to an output buffer OB, and the output buffer
`OB for transmitting the memory cell data received
`through the input/output interface (I/0), to a device
`external to the dynamic random access memory. In
`FIG. 1, there are shown the sense amplifier and the
`input/output interface (I/O) as constituting a single
`block S1. The output buffer OB receives the read-out
`data transmitted from the block SI and converts the
`same into corresponding output data Dout for output.
`Peripheral circuitry CG for generation of control
`signals is provided to generate the control signals for
`controlling various operating timings of the dynamic
`random access memory. The peripheral circuitry CG
`for generation of control signals generates a precharge
`potential V3, a word line drive signal Rn, an equalize
`signal 495‘, a precharge signal ¢P, a sense amplifier acti-
`
`5
`
`‘10
`
`15
`
`25
`
`30
`
`A schematic structure of the memory cell array
`shown in FIG. 1 and other circuit associated therewith
`is shown in FIG. 2. Referring to FIG. 2, the memory
`cell array MA comprises word lines WL1, WL2, .
`.
`.
`and WLn each defining a single row of the memory cell
`array MA, and bit line pairs BLO and BLO, BL1 and
`BL1,
`.
`.
`. and BLm and BE each having connected
`memory cells for a single column of the memory cell
`array MA.
`. BLm and fill? each
`.
`The bit line BLO and BLO, .
`constitute a folded bit line, every two bit lines of which
`constitute a single bit line pair. More specifically, the bit
`lines BLO and BLO constitute one bit line pair, the bit
`lines BL1 and BL1 constitute another bit line pair and so
`forth, until the bit lines BLm and BE constitute a bit
`line pair.
`Memory cells 1 for storing information are provided
`at intersections of each of the bit lines BLO, .
`.
`. BLm
`and FIE, and alternate word lines. Therefore, for re-
`spective bit line pairs, the memory cell 1 is provided at
`an intersection of a single word line and either bit line of
`a single bit line pair. The respective bit line pairs BLO
`and BLO, .
`.
`. BLm and WE are provided with a pre-
`charge/equalize circuit 150 for equalizing and pre-
`charging potentials on the respective bit lines to a pre-
`determined potential Vg while the dynamic random
`access memory is in its stand-by state.
`. , BLm
`.
`The respective bit line pairs BLO and BLO, .
`and IBTE are further provided with a sense amplifier 50
`for sensing and amplifying data of the selected memory
`cell. The sense amplifier 50 is responsive to a first sense
`amplifier drive signal 4>,4 and a second sense amplifier
`drive signal dug transmitted through a first signal line 14
`and a second signal line 17, respectively, for being acti-
`vated to detect and differentially amplify potential dif-
`ference on the corresponding bit line pair.
`In order to transmit the data of the selected memory
`cell to the output buffer OB as shown in FIG. 1, the bit
`line pairs BLO and BLO, . . .
`, BLm and BT35 are further
`provided with transfer gates T0 and T0’, T1 and T1’, .
`.
`. and Tm and Tm’, respectively, which are responsive
`to the decoded column address signal from the Y de-
`coder ADY for turning on to connect the correspond-
`ing bit line pair with data input/output buses I/O and I/
`. The transfer gates T0 and T0, are provided for the bit
`lines BLO and BT5, the transfer gates T1 and T1’ for the
`bit lines BL1 and FLT, and the transfer gates Tm and
`Trn’ for the bit line pairs BLm and BEE. A single trans-
`fer gate pair turns on in response to the decoded column
`address signal from the Y decoder ADY thereby con-
`necting the corresponding bit line pair to the input/out-
`put buses I/O and I/ .
`FIG. 3 is a diagram showing a circuit structure asso-
`ciated with a single bit line pair out of the structure
`shown in FIG. 2. In particular,.the diagram shows a
`specific structure of an apparatus for driving the sense
`amplifier 50.
`Referring to FIG. 3, the memory cell 1 comprises a
`memory capacitor 6 for storing information in the form
`of charge, and a selection transistor 5 which is respon-
`sive to the word line drive signal Rn transmitted onto a
`word line 3 for turning on to connect the memory ca-
`pacitor 6 to a bit line 2. The selection transistor 5 com-
`prises an n-channel insulating gate field effect transistor
`(referred to simply as n-FET hereinafter) having the
`
`Page 15 of 26
`
`

`
`3
`gate connected to the word line 3 and the source con-
`nected to the bit line 2. One electrode of the memory
`capacitor 6 is connected to the drain of &he selection
`transistor 5 through a storage node 4 while the other
`electrode is connected to ground potential GND (prac-
`tically to a supply potential Vcc).
`The precharge/equalize circuit 150 comprises n-
`FETS 9, 10 and 12. The n-FET 9 is responsive to the
`precharge "signal 4:,» transmitted through a precharge
`signal transmitting line 11, for turning on to transmit the
`precharge voltage V3 transmitted through a precharge
`potential transmitting signal line 8 onto the bit line 2.
`The n-FET 10 is responsive to the precharge signal dip
`transmitted through the signal line 11, for turning on to
`transmit the precharge voltage V3 transmitted through
`the signal line 8 to another bit line 7. The n-FET 12 is
`responsive to the equalize signal 4);; transmitted through
`an equalize signal transmitting signal line 13, for turning‘
`on to electrically short-circuit the bit lines 2 and 7
`thereby equalizing the potentials on the bit lines 2 and 7.
`The sense amplifier 50 comprises p—channel insulating
`gate field effect transistors (referred to simply -as p-
`FETs hereinafter) 15 and 16, and n-FETs 18 and 19.
`The sense amplifier 50 comprises a flip-flop of a CMOS
`(Complimentary Metal Oxide Semiconductor) structure
`where one electrode of each of the p-FETs 15 and 16 is
`cross-coupled with the gate electrode of the other, and
`also one electrode of each of the n-FETs 18 and 10 is
`cross-coupled with the gate electrode of the other. A
`connection node between one electrode of the p-FET
`15 and one electrode of the n-FET 18 is connected to
`the bit line 2 while another connection node between
`one electrode of the p-FET16 and one electrode of the
`n-FET 19 is connected to the bit line 7. The other elec-
`trodes of the p-FETs 15 and 16 are connected together
`to a signal line 14 which transmits the first sense ampli-
`tier drive signal 49,1. The other electrodes of the n-FETs
`18 and 19 are connected together to a signal line 17
`which transmits the second sense amplifier drive signal
`‘#3-
`Between the signal lines 14 and 17 there are provided
`n-FETs 26, 27 and 28 for precharging and equalizing
`potentials on the signal lines 14 and 17 to the predeter-
`mined potential V3. The n-FET26 is responsive to the
`precharge signal qbp transmitted through the signal line
`11 for turning on to transmit the predetermined con-
`stant precharge voltage V3 transmitted through the
`signal line 8 onto the signal line 14. The n-FET 27 is
`responsive to the precharge signal
`«pp transmitted
`through the signal line 11 for turning on to transmit the
`precharge potential V5 transmitted through the signal
`line 8 onto the signal line 17. The n-FET 28 is respon-
`sive to the precharge signal dip transmitted through the
`signal line 11 for turning on to electrically short-circuit
`the signal lines 14 and 17 thereby equalizing the poten-
`tials on the signal lines 14 and 17.
`In order to drive the sense amplifier 50, between the
`signal line 14 and a first source potential supply terminal
`24 there is provided a p-FET 22 which is responsive to
`the first sense amplifier activating signal 415 for turning
`on to connect the signal line 14 to a first power line 31.
`Similarly, between the signal line 17 and a second
`source potential supply terminal 29 there is provided an
`n-FET 25 which is responsive to the second sense am-
`plifier activating signal d>s for turning on to connect the
`signal line 17 to a second power line 30. The sense am-
`plifier activating signals xbs and tbs are applied to the
`gates of the p-FET 22 and the n-FET 25 through signal
`
`_
`
`4,980,799
`
`V 4
`input terminals 23 and 26, respectively. The supply
`terminals 24 and 29 are made of bonding pads which
`have been formed in a peripheral area of a semiconduc-
`tor chip having the dynamic random access memory
`formed therein, so as to receive a predetermined poten-
`tial from an external to the dynamic random access
`memory.
`The bit line 2 has a parasitic capacitance 20 and the
`bit line 7 has a parasitic capacitance 21.‘In addition, the
`second power line 30 has a parasitic resistance 32.
`Meanwhile, for simplicity of the drawing, in FIG. 3
`there are typically shown only one word line 3 and the
`memory cell 1 disposed at the intersection between the
`word line 3 and the bit line 2. In practice, however, a
`plurality of memory cells are connected to each of the
`bit lines 2 and 7.
`Furthermore, the precharge voltage V3 for precharg-
`ing the bit lines 2 and 7 and the signal lines 14 and 17 to
`a predetermined potential is generally set to about a half
`of the operational supply potential Vcc.
`FIG. 4 is a signal waveform diagram showing opera-
`tion of the circuit structure shown in FIG. 3. In FIG. 4,
`an operation is shown where information of logic “1”
`which has bee stored in the memory cell 1 shown in
`FIG. 3 is read out. In the following, the reading-out
`operation for the memory cell data will be described
`with reference to FIGS. 3 and 4.
`In a stand-by state between the time to and the time
`t1, the precharge signal dip and the equalize signal 4);;
`are both at the “H” level. Therefore, all of the n-FETs
`9, 10 and 12, and the n-FETs 26, 27 and 28 are in their
`on-state to hold the bit lines 2 and 7 and the signal lines
`14 and 17 at the predetermined precharge potential V5
`(=Vcc/2).
`At the beginning of a memory cycle or at the time t1
`whereat the stand-by state terminates, the precharge
`signal «lap and the equalize signal dag begin to fall to the
`“L” level. This causes the n-FETs 9, 10, 12, 26, 27 and
`28 to be turned off.
`At the time t2, the precharge signal 4:; and the equal-
`ize signal «by reach the “L” level, turning off all of the
`n-FETs 9, 10, 12, 26, 27 and 28, and then the internal
`row address is applied from the address buffer AB to
`the X decoder ADX as shown in FIG. 1, to select a row
`in the memory cell array MA.
`At the time t3, the word line drive signal Rn is trans-
`mitted onto a selected word line 3 (assuming that the
`word line 3 shown in FIG. 3 is selected) to raise poten-
`tial on the word line 3. This causes the selection transis-
`tor 5 in the memory cell 1 to be turned on so that the
`capacitor 6 in the memory cell 1 is connected to the bit
`line 2. As a result, charges having been stored at the
`storage node 4 move to the bit line 2, increasing poten-
`tial on the bit line 2 by only AV. The value V of this
`potential increase on the bit line 2 is determined depend-
`ing on capacitance value C6 of the memory capacitor 6,
`capacitance value C20 of the parasitic capacitance 20 of
`the bit line 2 and the stored voltage V4 at the storage
`node 4, which generally amounts to 100 to 200 mV.
`At the time t4, the sense amplifier activating signal
`(1)5 begins to rise while the sense amplifier activating
`signal qbs begins to fall, so that the n-FET 25 and the
`p-FET 22 are turned on. As a result, the first and second
`signal lines 14 and 17 are connected to the first and
`second power lines 31 and 30, respectively, causing the
`potential on the first signal line 14 to rise and the poten-
`tial on the second signal line 17 to fall.
`
`Page 16 of 26
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`

`
`4,980,799
`
`5
`The rise and fall of potential on these first and second
`signal lines 14 and 17 activates the flip-flop circuit
`(sense amplifier 50) comprising the p-FETs 15 and 16
`and the n-FETs 18 and 19, allowing the sensing opera-
`tion for memory cell data to begin, followed by differ-
`ential amplification of the minute potential difference
`AV between the bit lines 2 and 7. Meanwhile, since to
`the bit line 7 is connected no selected memory cell,
`potential on the bit line 7 remains held at the precharge
`level of Vcc/2 until the time t4.
`'
`In this sensing operation, when the n-FET 19 is
`turned on as a result of the potential increase on the bit
`line 2 only by AV, with the potential on the second
`signal line 17 decreased, the charges having been stored
`in the parasitic capacitance 21 are discharged through
`the n-FET 19 to the signal line 17, so that potential on
`the bit line 7 substantially reaches 0 V at the time t5.
`On the other hand, the potential decrease on the bit
`line 7 causes the p-FET 15 to be turned on, through
`which potential on the first signal line 14 is transmitted
`to the bit line 2 so that potential on the bit line 2 in-
`creases to the Vcc level. The potential on the bit line 2
`is transmitted to the storage node 4 through the selec-
`tion transistor 5 so that potential level at the storage
`node 4 becomes Vcc-V1-H, allowing restoring of data in
`the memory cell 1. V7-H represents here threshold volt-
`age of the selection transistor.
`When the amplifying operation of the signal poten-
`tials on the bit lines 2 and '7 is accomplished by establish-
`ing the respective potentials at the supply potential Vec
`level and at the ground potential GND level, one col-
`umn of the memory cell array is selected according to
`the decoded address signal from the column decoder
`ADY (see FIG. 1) and the bit lines 2 and 7 are con-
`nected to the data input/output buses I/O and I/ (see
`FIG. 2) until the time t8, whereby the information of
`the memory cell 1 is read out.
`The aforementioned is a description for the opera-
`tions of reading-out, amplifying and restoring data in a
`memory cell. When a series of these operations is ac-
`complished, the circuit enters in its stand-by state for
`the subsequent memory cycle. More specifically, the
`word line drive signal Rn begins to fall at the time t8
`and reaches the ground potential level of “L" at the
`time t9, and then the selection transistor 5 is turned off,
`electrically disconnecting the memory cell 1 from the
`bit line 2 to put the circuit in the stand-by state.
`At the time t10, the sense amplifier activating signals
`4:5 and 4:5 begin to fall and rise, and at the time tll reach
`the low level of ground potential GND and the high
`level of supply voltage Vcc, respectively, turning off
`the p-FET 22 and the n-FET 25 so that the sense ampli-
`fier 50 is inactivated.
`At the time t12, the equalize signal 4); begins to rise,
`turning on the n-FET 12 so that the bit lines 2 and 7 are
`electrically connected to each other. As a result,
`charges move from the bit line 2 at a higher potential
`level to the bit line 7 at a lower potential level and the
`potentials on the bit lines 2 and 7 together reach the
`precharge potential V}; (=Vcc/2) approximately at the
`time t13. At the same time, transfer of charges occurs
`between the first and second signal lines 14 and 17
`which have been put in the high-impedance state due to
`the p-FET 22 and n-FET 25 in the off-state, and the bit
`lines 2 and 7, resulting in potential levels of the signal
`lines 14 and 17 at Vcc/2+ |VTp| and Vcc/2—V7~1v,
`respectively. Vrp represents here threshold voltage of
`
`'
`
`6
`the p-FETs 22 and 16 while Vnv represents threshold
`voltage of the n-FETs 18 and 19.
`When the precharge signal dip begins to rise at the
`time t14, the n-FETs 9, 10, 26, 27 and 28 begin to be-
`come conductive. When the precharge signal <i>p attains
`the supply voltage Vcc of “H” level at the time US, all
`of the n-FETs 9, 10, 22, 26, 27 and 28 are turned on so
`that the precharge voltage V3 is transmitted to the bit
`lines 2 and 7 and the signal lines 14 and 17 are electri-
`cally connected through the n-FET 28, whereby the
`two sets of potentials are equalized, respectively. Fur-
`thermore, the predetermined precharge voltage V3 is
`transmitted to the signal lines 14 and 17 through the
`n-FETs 26 and 27 so that the potentials on the first and
`second signal lines 14 and 17 become Vcc/2. This tran-
`sit of the precharge signal 4);» to the “H” level stabilizes
`potentials on the bit lines 2 and 7 and the signal lines 14
`and 17 in preparation for the subsequent reading-out
`operation.
`As described above, in the reading-out operation of
`memory cell data in the dynamic random access mem-
`ory, one bit line of one bit line pair is charged from the
`Vcc/2+AV level to the Vcc level while the other bit
`line is discharged from the Vcc/2 level to the ground
`potential of O V level (only where logic “I” has been
`stored in the memory cell). In a case wherein logic “O”
`has been stored in the selected memory cell, potential of .
`one bit line is discharged from the Vcc/2—AV level to
`the ground potential of 0 V level while the other bit line
`is charged from the Vcc/2 level to the supply potential
`of Vcc level.
`In other words, in the operation of the sense ampli-
`fier, one bit line at a higher potential is charged to the
`supply voltage Vcc level while the other bit line at a
`lower potential is discharged to the ground potential
`level with respect to one bit line pair. This charge and
`discharge is attained by charging and discharging the
`capacitors of the bit lines, which is performed between
`the supply potential terminal 24 and the ground termi-
`nal (second supply potential terminal) 29 through the
`sense amplifier, the first and second signal lines 14 and
`17 and the first and second power lines 30 and 31. How-
`ever, the first and second power lines 31 and 30 are
`provided with the parasitic resistances 33 and 32 as
`described above (in the following description, the first
`power line 31 is referred to simply as power line and the
`second power line 30 as ground line for convenience of
`description). The parasitic resistances of the power line
`31 and the ground line 30 will be described with refer-
`ence to FIG. 5.
`In FIG. 5, there is shown a schematic layout of a
`memory cell array, a sense amplifier, a power line 31
`and a ground line 30 of a 4 M (mega) bit dynamic ran-
`dom access memory formed on a semiconductor chip
`100.
`In FIG. 5, the memory cell array MA is divided into
`8 sub array blocks MAI to MA8. Each of the sub arrays
`MAI to MA8 has 512K bits, or memory cells arranged
`in 512 rows and 1024 columns (lK columns). The divi-
`sion of the memory cell array into the sub arrays allows
`bit lines in the respective sub array blocks to be reduced
`in length, and the read-out voltage AV for the memory
`cell to be increased. The sub array blocks MA] to MA8
`are provided with the sense amplifier blocks SA1 to
`SA8, respectively. In the respective sense amplifier
`blocks SA1 to SA8, since a single sense amplifier is
`" provided for each of the columns in the corresponding
`
`35
`
`50
`
`Page 17 of 26
`
`

`
`7
`sub array block, 1024 sense amplifiers are provided in
`total.
`‘
`The ground line 31 extends from a bonding pad 24 to
`be disposed along and commonly for all of the sub array
`blocks MAI to MA8 on the semiconductor chip 100.
`Likewise, the ground line 30 extends from a pad 29 for
`the ground potential to be disposed along and com-
`monly for the memory cell array blocks MA1 to MA8
`on the semiconductor chip 100. The power line 31 and
`the ground line 30 are disposed not only for the memory
`cell array blocks MA1 to MAB, but of course for Sup-
`plying other peripheral circuits with a predetermined
`potential. For example, in the vicinity of the bonding
`pads 24 and 29, each of the power line 31 and the
`ground line 30 branches to be used for other peripheral
`circuits such as an address decoder, an address buffer or
`the like. To avoid complexity of description, here is
`shown only a structure where supply/ground potential
`is supplied to those circuit blocks which are associated
`with the memory cell array blocks MAI to MA8.
`A p-FET 221 and an n—FET 251 are provided to
`drive the sense amplifiers of the sense amplifier block
`SA1. Likewise, a p-FET 222 and an n-FET 252 are
`provided to drive the sense amplifier of the sense ampli-
`fier block SA2. For the sense amplifier block SA3, a
`p-FET 223 and an n-FET 253 are provided, for the
`sense amplifier block SA7 a p-FET 227 and an n-FET
`257, and for the sense amplifier block SA8, a p-FET 228
`and an n-FET 258 are provided.
`The p-FETs 221 to 228 are responsive to the sense
`amplifier activating signal 455 applied from a signal input
`node 23, for turning on to connect the sense amplifier
`activating signal lines in the respective blocks to the
`ground line 31. The respective n-FETs 251 to 258 are
`responsive to the sense amplifier activating signal 4:5
`transmitted through a signal input node 26, for turning
`on to connect a signal line in the corresponding sense
`amplifier block to the ground line 30. The power line 31
`and the ground line 30 have parasitic resistance as indi-
`cated by broken lines in FIG. 5.
`As exemplified in FIG. 5, the power line 31 and the
`ground lines 30 are disposed substantially from one end
`of the semiconductor chip 100 to the other. Therefore,
`the parasitic resistance will be relatively great even if
`aluminum of low resistivity is employed as the intercon-
`nection material. In the structure shown in FIG. 5, for
`example, the largest possible parasitic resistance of the
`ground line 30 can be seen with respect to the sense
`amplifier block SA1 which has been provided furthest
`away from .the pad 29. It is here attempted to calculate
`the parasitic resistance value of the ground line 30 with _
`respect to this sense amplifier block SA1 in a general 4
`M dynamic random access memory as an example.
`Now, assume that:
`aluminum resistance value: 50 mfl/El,
`* aluminum interconnection width: 25 um,
`aluminum interconnection length: 15 mm.
`With the values above, the parasitic ground line 30 with
`respect to the sense amplifier block SAI is given by the
`following expression.
`
`50 x 10-3 x 15 x 1o-3/25 x 10-6
`2
`_ 30 (0)
`
`(1)
`
`Meanwhile, there are provided memory cells of 1024
`columns in the memory cell array MAI, where a single
`column corresponds to a single bit line pair. This means
`that there are 1024 discharging bit lines in the sensing
`
`4,980,799
`
`8
`operation. Now, assuming that the capacitance per sin-
`gle bit line is about 0.3 pF, the total capacitance of the
`bit lines participating in the discharging is given by the
`following expression.
`
`C
`
`0.3 X 1024
`- 300 (pF)
`
`(2)
`
`The charges stored in this capacitance C are to be dis-
`charged to the ground terminal pad 29 through the
`n-FET 251 and the parasitic resistance of the ground
`line 30 in the sensing operation. Then, the time required
`for this discharging will be calculated. In order to sim-
`plify this calculation, it is assumed that size of the
`n-FET 250 is enlarged enough to have an equivalent
`resistance which is well smaller than the parasitic resis-
`tance of the ground line 30, and the discharge time t is
`regarded as time constant 7' of this CR discharge circuit.
`The discharge time t is given by the following expres-
`sion.
`
`45
`
`50
`
`The total delay time acceptable in a single memory
`cycle of the dynamic random access memory is 60 to 80
`ns and more than 10% thereof is taken by the discharge
`time, which amounts to a relatively high proportion.
`Furthermore,
`the above dynamic random access
`memory is constituted in such a manner that in one
`memory operation (one memory cycle), not only a sin-
`gle sub array block but also other sub array, blocks
`operate (in the 4 M bit dynamic random access memory
`shown in FIG. 5, two sub array blocks operate simulta-
`neously). Therefore, in the sensing operation these plu-
`rality of sub array blocks are simultaneously activated
`so that the discharge in the sensing operation will cause
`the potential level on the ground line 30 and thus the
`discharge level of the bit line to increase, resulting in a
`longer discharge time than the above-mentioned value.
`Furthermore, while in the above, description has
`been made merely on the delay in the discharge opera-
`tion of the bit line at a lower potential in thesensing
`operation, the same argument is true of the charge oper-
`ation for charging the bit line at a higher potential so
`that also the charge time becomes longer.
`The increased time for charging and discharging the
`bit lines in the sensing operation also leads to an unnec-
`essarily increased time which will be taken for establish-
`ing the potentials of the bit lines to the supply potential
`V“ level and the ground potential level, so that a prob-
`lem arises that the memory cell data cannot be read out
`at a high speed.
`Additionally, in a case where numerous bit lines are
`charged and discharged in the sensing operation as
`described above, the charging and the discharging cur-
`rents in a large-capacity dynamic random access mem-
`ory amount to, for example, as much as 150 mA to 250
`mA, causing fluctuation in the supply potential and the
`ground potential, which may even result in a malfunc-
`tion of the circuit operation.
`The stabilization of supply voltage by providing a
`bypass condenser formed of a PN junction between the
`power line and, the ground line is described in “32K>< 8
`
`Page 18 of 26
`
`

`
`9
`bits fast SRAM; 10 ns accomplished with thorough
`countermeasures against noise” Nikkei Electronics, No.
`455, 1988, September 5, pp. 133 to 136.
`SUMMARY OF THE INVENTION
`
`An object of the present invention is to provide a
`sense amplifier driving apparatus which can eliminate
`the problems of a conventional dynamic random access
`memory as described above and perform charging and
`discharging of the bit lines at a high speed in the sensing
`operation.
`'
`Another object of the present invention is to provide
`a sense amplifier driving apparatus which is provided
`with ‘an electrostatic capacitor superior in the high-fre-
`quency characteristic and capable of fully suppressing
`t