Paper No. ____
`Filed: October 7, 2016
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`PROMOS TECHNOLOGIES, INC
`Patent Owner
`
`____________________
`
`U.S. Patent No. 6,195,302
`____________________
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,195,302
`
`
`
`
`
`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`TABLE OF CONTENTS
`
`
`INTRODUCTION ........................................................................................... 1 
`I. 
`II.  MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ................................... 1 
`III.  PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 2 
`IV.  GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.104(a) ..................... 2 
`PRECISE RELIEF REQUESTED AND GROUNDS RAISED
`V. 
`UNDER 37 C.F.R. § 42.104(b) ....................................................................... 2 
`A. 
`Claims for Which Review Is Requested ............................................... 2 
`B. 
`Statutory Grounds of Challenge ............................................................ 2 
`C. 
`Statement of Non-Redundancy ............................................................. 4 
`VI.  LEVEL OF ORDINARY SKILL IN THE ART ............................................. 5 
`VII.  OVERVIEW OF THE TECHNOLOGY, ’302 PATENT, AND
`PRIOR ART ..................................................................................................... 6 
`A. 
`Technology Background ....................................................................... 6 
`B. 
`The ’302 Patent ..................................................................................... 6 
`Seo ....................................................................................................... 11 
`C. 
`D.  Min ....................................................................................................... 14 
`VIII.  CLAIM CONSTRUCTION .......................................................................... 17 
`A. 
`“timer unit . . . generating a control signal” ........................................ 19 
`B. 
`“first component . . . causing the control signal to change from
`a first logic level towards a second logic level at a first rate” ............ 21 
`“second component . . . causing the control signal to change to
`the second logic level at a second rate” .............................................. 23 
`“delay unit . . . generating a delayed sense control signal” ................. 24 
`
`D. 
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`C. 
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`IX.  DETAILED EXPLANATION OF GROUNDS ............................................ 25 
`A.  Ground 1: Seo in view of Min Renders Obvious Claims 10-12
`and 1-5 ................................................................................................. 25 
`1. 
`Claim 10 .................................................................................... 25 
`2. 
`Claim 11 .................................................................................... 55 
`3. 
`Claim 12 .................................................................................... 56 
`4. 
`Claim 1 ...................................................................................... 57 
`5. 
`Claim 2 ...................................................................................... 73 
`6. 
`Claim 3 ...................................................................................... 74 
`7. 
`Claim 4 ...................................................................................... 75 
`8. 
`Claim 5 ...................................................................................... 76 
`B.  Ground 2: Seo Anticipates Claims 10-12 ............................................ 77 
`1. 
`Claim 10 .................................................................................... 77 
`2. 
`Claim 11 .................................................................................... 79 
`3. 
`Claim 12 .................................................................................... 79 
`C.  Ground 3: Seo, Min, and Schuster Render Obvious Claim 6 .............. 79 
`1. 
`Claim 6 ...................................................................................... 79 
`CONCLUSION .............................................................................................. 83 
`
`X. 
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`Petition for Inter Partes Review
`Patent No. 6,195,302
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`LIST OF EXHIBITS
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`
`
`Ex. 1001
`
`U.S. Patent No. 6,195,302 to Hardee (“the ’302 patent”)
`
`Ex. 1002
`
`Declaration of R. Jacob Baker, Ph.D, P.E.
`
`Ex. 1003
`
`Prosecution History of U.S. Patent No. 6,195,302
`
`Ex. 1004
`
`U.S. Patent No. 5,140,199 to Seo (“Seo”)
`
`Ex. 1005
`
`UK Patent GB2246005B to Min et al. (“Min”)
`
`Ex. 1006
`
`European Patent EP 0597231 A2 to Hardee (“Hardee EP”)
`
`Ex. 1007
`
`Schuster et al., “A 15-ns CMOS 64K RAM,” IEEE J. of Solid-State
`Circuits, Vol. SC-21, No. 5, Oct. 1986, pp.704-12 (“Schuster”)
`
`Ex. 1008
`
`Taur et al., Fundamentals of Modern VLSI Devices, 1998 (“Taur”)
`
`Ex. 1009
`
`U.S. Patent No. 4,980,799 to Tobita (“Tobita”)
`
`Ex. 1010
`
`Curriculum Vitae of Dr. R. Jacob Baker
`
`Ex. 1011 Meng et al., “A Clock-Free Chip Set for High-Sampling Rate
`Adaptive Filters,” Journal of VLSI Signal Processing, 1, pp. 345-65
`(1990) (“Meng”)
`
`Ex. 1012
`
`Amrutur et al., “A Replica Technique for Wordline and Sense
`Control in Low-Power SRAM’s,” IEEE Journal of Solid-State
`Circuits, Vol. 33, No. 8, Aug. 1998, pp.1208-19
`
`
`
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`iii
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`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`I.
`
`INTRODUCTION
`
`Samsung Electronics Co., Ltd. (“Petitioner”) requests inter partes review
`
`(“IPR”) of claims 1-6 and 10-12 (“the challenged claims”) of U.S. Patent No.
`
`6,195,302 (“the ’302 patent”) (Ex. 1001), which is currently assigned to ProMOS
`
`Technologies, Inc. (“Patent Owner”) according to USPTO records. For the reasons
`
`set forth below, the challenged claims should be found unpatentable and canceled.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Parties-in-Interest: Petitioner identifies the following as the real
`
`parties-in-interest: Samsung Electronics Co., Ltd.; Samsung Electronics America,
`
`Inc.; Samsung Semiconductor, Inc.; and Samsung Austin Semiconductor, LLC.
`
`Related Matters: Patent Owner has asserted the ’302 patent against
`
`Petitioner in ProMOS Technologies, Inc. v. Samsung Electronics Co., Ltd., et al.,
`
`No. 1:15-cv-00898-SLR-SRF (D. Del.). Petitioner is concurrently filing a petition
`
`challenging claims 1-6, 10-12 and 14-18 of the ’302 patent. Petitioner respectfully
`
`requests that the Board institute each petition, as each presents distinct and non-
`
`redundant grounds. Patent Owner has also asserted U.S. Patent Nos. 6,849,897
`
`(“the ’897 patent”), 6,020,259 (“the ’259 patent”), 6,699,789 (“the ’789 patent”),
`
`6,088,270 (“the ’270 patent”), and 5,761,112 (“the ’112 patent”) in this action.
`
`Petitioner is also concurrently filing IPR petitions on the ’897, ’259, ’789, ’270,
`
`and ’112 patents.
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`1
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`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
`Counsel and Service Information: Lead counsel is Naveen Modi (Reg. No.
`
`46,224), and backup counsel are (1) Joseph E. Palys (Reg. No. 46,508) and (2)
`
`Chetan R. Bansal (Limited Recognition No. L0667), and (3) Arvind Jairam (Reg.
`
`No. 62,759). Service information is Paul Hastings LLP, 875 15th St. N.W.,
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`Washington, D.C., 20005, Tel.: 202.551.1700, Fax: 202.551.1705, email: PH-
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`Samsung-Promos1-IPR@paulhastings.com.
`
` Petitioner consents to electronic
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`service.
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`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The PTO is authorized to charge all fees due at any time during this
`
`proceeding, including filing fees, to Deposit Account No. 50-2613.
`
`IV. GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.104(a)
`Petitioner certifies that the ’302 patent is available for IPR and Petitioner is
`
`not barred or estopped from requesting IPR on the grounds identified herein.
`
`V.
`PRECISE RELIEF REQUESTED AND GROUNDS RAISED UNDER
`37 C.F.R. § 42.104(b)
`A. Claims for Which Review Is Requested
`Petitioner respectfully requests review of claims 1-6 and 10-12 (“challenged
`
`claims”) of the ’302 patent, and cancellation of these claims as unpatentable. (Ex.
`
`1002, ¶173.)
`
`Statutory Grounds of Challenge
`
`B.
`The challenged claims should be canceled as unpatentable on the following
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`2
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`

`
`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`grounds:
`
`Ground 1: Claims 1-5 and 10-12 are unpatentable under pre-AIA 35 U.S.C.
`
`§103(a) in view of U.S. Patent No. 5,140,199 (“Seo”) (Ex. 1004) and UK Patent
`
`GB2246005B (“Min”) (Ex. 1005);
`
`Ground 2: Claims 10-12 are unpatentable under pre-AIA 35 U.S.C. §102(b)
`
`based on Seo; and
`
`Ground 3: Claim 6 is unpatentable under pre-AIA 35 U.S.C. § 103(a) in
`
`view of Seo, Min, and Schuster et al., “A 15-ns CMOS 64K RAM,” IEEE J. of
`
`Solid-State Circuits, Vol. SC-21, No. 5, Oct. 1986, pp.704-12 (“Schuster”) (Ex.
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`1007).
`
`The challenged claims are not entitled to a filing date earlier than February
`
`5, 1999.1 Seo was issued on August 18, 1992. Min was published on August 31,
`
`1994. Schuster was published in October 1986. Therefore, Seo, Min, and Schuster
`
`are prior art to the ’302 patent at least under pre-AIA 35 U.S.C. § 102(b).
`
`Schuster was published in October 1986 in the IEEE Journal of Solid-State
`
`1 Petitioner takes no position on whether that the claims of the ’302 patent are
`
`supported by the provisional application (U.S. 60/118,737 filed on February 5,
`
`1999). Each of the prior art references that form the basis of the grounds asserted
`
`in this petition are prior art to the ’302 patent regardless of whether the claims of
`
`the ’302 patent are entitled to the February 5, 1999 provisional filing date.
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`Circuits, Volume SC-21, Issue No. 5. This can be seen, for example, at the top of
`
`each page of Schuster. (Ex. 1007, 704-712.) Given that it was published in a well-
`
`known journal in October 1986, over a decade before the filing date of the ’302
`
`patent (id.), Schuster qualifies as prior art under pre-AIA 35 U.S.C. § 102(b). In
`
`fact, Schuster was cited by other articles well-before the ’302 patent was filed.
`
`(See, e.g., Ex. 1011, 363 (reference 7); Ex. 1012, 1219 (reference 21).)
`
`Among the references relied upon in this Petition, Min, and Schuster were
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`never considered by the Patent Office during prosecution of the ’302 patent. (See
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`Ex. 1001, References Cited.) Seo is, however, listed on the face of the ’302 patent
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`and was submitted in an information disclosure statement during prosecution. But
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`Petitioner presents Seo in a new light never considered by the Office. (See infra
`
`Section IX.) Moreover, Petitioner presents testimony from R. Jacob Baker, Ph.D.,
`
`P.E., an expert in the field of the ’302 patent, who confirms that the relevant
`
`teachings of Seo alone or in combination with the other cited references discloses
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`or suggests what is recited by the challenged claims. (See Ex. 1002.) As such,
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`consideration of Seo by the Patent Office during prosecution of the ’302 patent
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`should not preclude the Office from considering and adopting the grounds in this
`
`petition that involve this reference.
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`Statement of Non-Redundancy
`
`C.
`Petitioner is filing a second IPR petition against the ’302 patent concurrent
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`with the filing of this petition. However, Petitioner’s proposed grounds for
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`institution in the two petitions are not redundant and the Board should institute
`
`review in both proceedings. The primary references applied in the two petitions
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`disclose features of the challenged claims in different ways, and are based on
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`different combinations of references. For example, the primary reference in this
`
`petition (Seo) does not explicitly disclose a circuit component that delays a signal,
`
`as required by claim elements 10(e) and 1(f). Instead, a secondary reference is
`
`relied upon to disclose that feature. In contrast, the primary reference at issue in
`
`the other petition discloses these claimed features. As such, Petitioner respectfully
`
`requests that the Board adopt all proposed Grounds in both of the petitions.
`
`VI. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art at the time of the alleged invention of
`
`the ’302 patent would have had at least a Bachelor’s degree in electrical
`
`engineering, or equivalent thereof, and at least two to three years of experience in
`
`design of semiconductor memory circuits. (Ex. 1002, ¶19.)2 More education can
`
`supplement practical experience and vice versa. (Id.)
`
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`2 Petitioner submits the declaration of Dr. R. Jacob Baker (Ex. 1002), an expert in
`
`the field of the ’302 patent. (Ex. 1002, ¶19.)
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`VII. OVERVIEW OF THE TECHNOLOGY, ’302 PATENT, AND PRIOR
`ART
`A. Technology Background
`At the time of the alleged invention of the ’302 patent, it was well known
`
`that integrated circuit memories could include memory cell arrays consisting of
`
`thousands of memory cells arranged in a matrix of rows (word lines) and columns
`
`(bit lines), with each memory cell located at or near the crossing of a bit line and
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`word line. (Ex. 1002, ¶37-39, citing Ex. 1009.) To read and write to the memory
`
`cells of a DRAM, other circuitry was known to be provided. (Id.) For instance,
`
`the bit lines were often coupled into complementary bit line pairs, with each pair
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`associated with a sense amplifier that amplifies the signal on the bit lines during a
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`read operation and drives/controls the bit lines when data is being written into the
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`memory cells. (Id.) Several different techniques had been disclosed in the prior
`
`art at the time of the alleged invention of the ’302 patent for driving the sense
`
`amplifiers. (Id.) As discussed below, the ’302 patent claims a known prior art
`
`technique that drives transistors (referred to in the ’302 patent as sense amplifier
`
`driver transistors), which control activation of the sense amplifiers. (Id.; see also
`
`id. at ¶¶21-29.)
`
`The ’302 Patent
`
`B.
`The ’302 patent issued from U.S. application no. 09/492,276 filed on
`
`January 27, 2000 (Ex. 1003 at 4-26) and is directed to a memory device with sense
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`amplifiers 101a-101c that are coupled to a high voltage line Vcc and ground via
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`driver transistors 104 and 106, respectively. (See id. at ¶¶40-48.) Driver
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`transistors 104, which are PMOS pull-up transistors, and driver transistors 106,
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`which are NMOS pull-down transistors, are controlled by control signals LPB and
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`LNB, respectively and are shown in FIG. 1 of the ’302 patent:
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`(Ex. 1001, FIG. 1; see also id. at 4:40-5:4; Ex. 1002, ¶40.)
`
`
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`The ’302 patent discloses functionality of sense amplifiers 101 with respect
`
`to FIG. 2 (shown below):
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`Petition for Inter Partes Review
`Patent No. 6,195,302
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`(Id. at FIG. 2; see also id. at 5:5-55.)
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`
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`The ’302 patent discloses that for a “sense amplifier 101 with associated
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`circuitry typical in a DRAM application,” “[s]torage capacitors 201 are selectively
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`coupled to bit lines 202 through access switches 203 in response to address signals
`
`supplied to word lines 204.” (Ex. 1001, 5:5-9.) Prior to a read operation, a pair of
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`bit lines 202 are “equalized at some voltage between a logic high and a logic low
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`signal,” and a word line (WL) signal is activated. (Id. at 5:18-21, 5:35-37.) After
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`the WL signal is activated, “the LPB signal is driven to a logic low coupling VCCI
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`to sense amp 101 through drive transistor 104 [and] [s]imilarly, the LNB signal is
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`driven high to couple sense amp 101 to ground or VSS through drive transistor 106.”
`
`(Id. at 5:38-42.) The ’302 patent discloses that ““[p]referably, LNB and LPB are
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`generated by a circuit such as that shown in FIG. 3 that generates LNB and LBP
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`both as dual slope signals.” (Id. at 5:45-47.) The circuit for generating LNB and
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`LBP is shown below:
`
`
`
`(Id. at FIG. 3; Ex. 1002, ¶43.)
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`
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`The ’302 patent discloses that when sensing is to begin, “one of the input
`
`signals SENR or SENL will go to a logic high,” which causes signal 302 to
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`transition to a logic low because of NOR gate 301 and inverter 304. (Id. at FIG. 3,
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`5:66-6:6; Ex. 1002, ¶¶44-45.) Signal LPB is disclosed as being generated as
`
`follows:
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`[S]hortly after either SENR or SENL goes high, transistor 303
`is turned on pulling the LPB signal low through resist[o]r
`306. . . . Resistor 316 controls the rate of change or dv/dt of
`LNB while resistor 306 controls the dv/dt of LPB. After a
`delay determined by delay element 307, transistor 308 will be
`turned on pulling LPB to ground with a much lower resistance.
`When transistor 308 is turned on, LPB will fall to the ground
`voltage with a high dv/dt.
`
`(Id. at 6:8-18; see also id. at FIG. 3.)
`
`
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`Signal LNB is generated in a similar manner, using circuit components
`
`shown in the lower part of FIG. 3. (Id. at 6:11-13, 6:18-21.) Signals LNB and
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`LPB are generated as “dual slope signals.” (Id. at 5:45-47.)
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`Thus, the ’302 patent discloses that signal LPB, which controls drive
`
`transistor 104, is generated by turning on transistor 308 to pull down LPB, then
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`after a delay, turning on transistor 303 so that LPB is pulled down two separate
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`paths corresponding to transistors 308 and 303. (Id. at 6:33-36, FIG. 3; Ex. 1002,
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`¶48.) Signal LNB is generated in an analogous manner using staggered pull-up
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`paths (i.e., a first pull-up path corresponding to transistor 313 is enabled, and then
`
`after a delay, a second pull-up path corresponding to transistor 318 is enabled,
`
`while the first pull-up path is still enabled). (Ex. 1001, 6:33-36, FIG. 3; Ex. 1002,
`
`¶48.)
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`10
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`Petition for Inter Partes Review
`Patent No. 6,195,302
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`Seo
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`C.
`Seo discloses “sense amplifier circuitry for sensing data from memory cells.”
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`(Ex. 1004, 1:7-8; see also Ex. 1002, ¶¶53-58.) Seo shows a sense amplifier driver
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`in FIG. 5:
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`
`
`(Id. at FIG. 5; Ex. 1002, ¶53; see also id. at ¶¶54-58.)
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`
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`The circuit of FIG. 5 includes a sensing clock driver 10 that generates a
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`signal at node LAG that drives the gate of NMOS transistor Ts to a high value,
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`which turns on transistor Ts and thereby connects sense amplifier 40 to Vss. (Ex.
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`1004, FIG. 5, 5:55-58, 7:4-10; Ex. 1002, ¶¶54-58.)
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`As discussed below, the LAG signal in Seo has a “multi-slope” characteristic
`
`
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`like the LNB signal in the ’302 patent. (Ex. 1002, ¶55; see supra Section VII.B
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`(explaining the dual-slope nature of LNB).) Seo discloses that “[i]f a sensing
`
`enable state is established by the equalization control clock Qeq being at the Vss
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`level and the sensing clock signal Qs being at the Vcc level, then node ‘d’ of
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`sensing clock driver 10 [falls]3 to Vss level immediately owing to the function of
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`n-channel MOS transistor Th of inverter IV10.” (Ex. 1004, 6:56-61.) “Therefore,
`
`the p-channel MOS transistor Te of the inverter IV30 immediately turns on.” (Id.
`
`at 6:61-63.) However, transistor Ts is not turned on completely “since transistor
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`Te has small current driving capability” and is therefore unable to pull up signal
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`LAG immediately to “high level, i.e., to the Vcc level” to completely turn on
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`transistor Ts. (Id. at 6:63-66.)
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`
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`“[T]he potential of node ‘e’ is lowered to Vss level after having been
`
`delayed for a certain period of time due to the function of resistance R3 of inverter
`
`IV10,” and the PMOS transistor Td having a “large current driving capability turns
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`on.” (Id. at 6:67-7:4.) “Therefore, the potential of node LAG raises to Vcc level
`
`with a multi-slope characteristics, so that it can completely turn on the n-channel
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`MOS sense transistor Ts.” (Id. at 7:4-7.) “The resultant sensing signal LAB of the
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`3 The omission of the word “falls” in this sentence of Seo is a drafting error but it is
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`clear from FIG. 6 that node d “falls” to Vss. (Ex. 1002, ¶55, fn.4.)
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`Vss level . . . carries out the sensing operation for the data stored in the memory
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`cell.” (Id. at 7:7-10.)
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`
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`In other words, Seo discloses that transistor Te turns on first to pull up the
`
`voltage at node LAG, and then, after a delay associated with “delaying resistance
`
`R3” (id. at 5:59-60), transistor Td turns on to provide a second pull-up path for
`
`pulling up node LAG. (Ex. 1002, ¶57.) FIG. 6 of Seo discloses that nodes d and e
`
`are both at low voltage after the falling transition at node e; hence, transistors Te
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`and Td are both on, and provide separate pull-up paths for signal LAG, after
`
`transistor Td is turned on. (Id.; Ex. 1004, FIG. 6.)
`
`(Ex. 1002, ¶56, citing Ex. 1004, FIG. 6 (annotated).)
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`In summary, Seo’s technique of sequentially activating pull-up paths (i.e., a
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`
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`first pull-up path through transistor Te and a second pull-up path through transistor
`
`Td) for generating a dual-slope control signal (LAG) is very similar to the
`
`sequential activation of pull-up paths disclosed in the ’302 patent, as further
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`explained below in section IX. (Ex. 1002, ¶58; infra section IX.)
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`D. Min
`Min describes a “sense amplifier driving circuit which is suitable for use in a
`
`high density semiconductor memory device.” (Ex. 1005, 1:6-8; see also Ex. 1002,
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`¶¶59-70.) Min discloses at FIG. 1A a sense amplifier driving circuit that was
`
`conventional at the time of Min: 
`
`(Ex. 1005, FIG. 1A (annotated); Ex. 1002, ¶59.)
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`The sense amplifiers SA1-SAn in Min are connected to one another at node
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`
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`LAP and at LAN and are connected to Vcc and Vss by driving transistors Q1 and
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`Q2, respectively. (Ex. 1005, FIG. 1A.)
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`
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`Min discloses a variation of the FIG. 1A sense amplifier driving circuit
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`arrangement in FIG. 1B where now each sense amplifier is provided with its own
`
`respective driving transistor Q1i connected to VCC and Q2i connected to VSS:
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`
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`(Ex. 1005, FIG. 1B; Ex. 1002, ¶63.)
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`Min discloses, in an embodiment corresponding to FIG. 9, an improved
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`driver circuit for driving the conventional sense amplifiers shown in FIGS. 1A and
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`1B. The improved driving circuit and a corresponding timing diagram are shown
`
`in FIG. 9:
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`Petition for Inter Partes Review
`Patent No. 6,195,302
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`
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`(Ex. 1005, FIG. 9.)
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`
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`Min explains that a dual slope characteristic for signal ϕLAP (voltage at node
`
`LAP) is achieved by a sequential pull-down approach by which a first pull-down
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`path is activated to pull down the voltage at the gate of PMOS transistor Q110, and
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`then after a delay a second pull-down path is activated. (Ex. 1005, 29:18-30:3; Ex.
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`1002, ¶66.) Min discloses that “signal ϕSP1 is set to have a high level,” which turns
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`on NMOS transistor Q112. (Ex. 1005, 29:21-25.) “After a certain period of time,
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`the second active restore enable signal ϕSP2 goes to a high level, and the transistor
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`Q115 . . . is turned on so that the current Icca flowing through the driving transistor
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`Q110 is increased.” (Ex. 1005, 29:29-34.)
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`
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`Turning on transistor Q112 activates a first pull-down path for pulling down
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`the voltage at the gate of transistor Q110, and subsequently turning on transistor
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`Q115 activates a second pull-down path for pulling down that same gate voltage.
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`(Ex. 1005, FIG. 9; Ex. 1002, ¶67.)
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`Thus, Min discloses a technique of sequentially activating pull-down paths
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`and sequentially activating pull-up paths that is similar to the sequential activation
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`of pull-up paths and sequential activation of pull-down paths disclosed in the ’302
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`patent, as further explained below in section IX. (Ex. 1002, ¶¶68-70; infra section
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`IX.)
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`VIII. CLAIM CONSTRUCTION
`A claim in an unexpired patent that will not expire before a final written
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`decision is issued in an IPR receives the “broadest reasonable construction in light
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`of the specification of the patent in which it appears.” 37 C.F.R. § 42.100(b). The
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`’302 patent has not expired and will not expire before a final written decision will
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`be issued. Thus, for purposes of this proceeding, the claims of the ’302 patent
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`should be given their broadest reasonable construction.
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`Furthermore, to determine whether a claim should be interpreted under §
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`112, ¶6, “[t]he standard is whether the words of the claim are understood by
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`persons of ordinary skill in the art to have a sufficiently definite meaning as the
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`name for structure. (Williamson v. Citrix Online LLC, 792 F.3d 1339, 1349 (Fed.
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`Cir. 2015).) “[T]he failure to use the word ‘means’ [in a claim] creates a rebuttable
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`presumption . . . that § 112, para. 6 does not apply.” (Id. at 1348.) “[T]he
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`presumption can be overcome and § 112, para. 6 will apply if the challenger
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`demonstrates that the claim term fails to recite sufficiently definite structure or else
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`recites function without reciting sufficient structure for performing that function.”
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`(Id. (internal quotes omitted).)
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`As set forth herein, Petitioner provides the broadest reasonable construction
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`for certain claim terms below. Any term not interpreted below should be
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`interpreted in accordance with its plain and ordinary meaning under the broadest
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`reasonable interpretation standard.4
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`4 Because of the different claim interpretation standards used in this proceeding
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`and in district courts, any claim interpretations submitted or implied herein for the
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`purpose of this proceeding are not binding upon Petitioners in any litigation related
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`to the ’302 patent. Specifically, any interpretation or construction of the claims
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`presented herein, either implicitly or explicitly, should not be viewed as
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`constituting, in whole or in part, Petitioner’s interpretation of such claims in any
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`A.
`“timer unit . . . generating a control signal”
`Claim 1 recites the term “timer unit . . . . . . generating a control signal.”5
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`The term “timer unit” is a means-plus function term under 35 U.S.C. § 112, ¶6.
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`Claim 1 recites that “a timer unit having an output coupled to the control
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`electrode and generating a control signal.” This claim recites function (“generating
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`a control signal”) without reciting sufficient structure for performing that function.
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`A timer unit as recited in claim 1 does not connote any structure. Indeed, the
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`identified function for this term, “having an output coupled to the control
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`electrode” only specifies where the output of the timer unit is coupled and does not
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`specify structure for the timer unit itself. Like the term “module” in Williamson,
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`the recitation of a timer “unit” in claim 1 does not provide a sufficiently definite
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`underlying litigations involving the ’302 patent. Moreover, Petitioner does not
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`concede that the challenged claims are not indefinite, which is something that
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`cannot be pursued in this proceeding under the Rules.
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`5 The term “the timer unit output” in claim 12 does not have any antecedent basis,
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`and thus claim 12 is indefinite. However, for purposes of this proceeding,
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`Petitioner assumes that the term “timer unit output” in claim 12 means an output
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`from a clock or timer, such as a “clock signal.” Under that assumption, however,
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`“the timer unit output” in claim 12 should not be construed in a manner similar to
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`the recited “timer unit . . . generating a control signal” in claim 1 discussed above.
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`structure for performing the function of “generating a control signal.” Williamson,
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`792 F.3d at 1350 (“the word ‘module’ does not provide any indication of structure
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`because it sets forth the same black box recitation of structure for providing the
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`same specified function as if the term ‘means’ had been used.”).
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`Although claim 1 recites “a first component” and “a second component” that
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`are both “within the timer unit,” those “component[s]” are specified in the claim
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`using purely functional language, i.e., describing what they do. Therefore, those
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`“component[s]” do not impart sufficient structure for performing the recited
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`function of the “timer unit.” Therefore, although “means” is not recited in this
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`claim, the presumption that § 112, ¶6 does not apply is overcome in this instance,
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`and “timer unit” is a means-plus-function term.
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`Construing a means-plus-function claim term requires that the function
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`recited in the claim term be first identified; then, the written description of the
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`specification must be consulted to identify the corresponding structure that
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`performs the identified function and equivalents thereof. See Williamson, 792 F.3d
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`1339 at 1351; see also Gracenote, Inc. v. Iceberg Indus., LLC, IPR2013-00551,
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`Paper No. 6 at 15 (Feb. 28, 2014).
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`The written description of the ’302 patent discloses that the function of
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`“generating a control signal” is performed by at least a pair of transistors and one
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`or more circuit components that delay a signal. For example, the ’302 patent
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`discloses that the pair of transistors 303, 308 and delay element 307 generate
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`control signal LPB, and that the pair of transistors 313, 308 and delay unit 317
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`generate control signal LNB. (Ex. 1001, 5:57 (describing LPB and LNB as
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`“control signals”), 6:7-21 (disclosing that transistor 303 is first turned on to pull
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`signal LPB low, then after delay element 307 delays the signal at its input,
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`transistor 308 is turned to pull down signal LPB; and providing similar disclosure
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`regarding transistors 313, 308 and delay unit 317, but regarding pull up paths),
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`FIG. 3.)
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`For purposes of this proceeding, resistors 306 and 316 should not be
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`considered as part of the corresponding structure, because the specification of
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`the ’304 patent discloses that that “resistors 306 and 316 can be eliminated and rise
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`time of the first and second stage controlled by relative transistor sizes.” (Id. at
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`6:31-33.)
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`Therefore, for purposes of this proceeding, the corresponding structure for
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`the identified function for this term is “at least a pair of transistors and one or more
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`circuit components that delay a signal” and its equivalents.
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`B.
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`“first component . . . causing the control signal to change from a
`first logic level towards a second logic level at a first rate”
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`This term, which appears in claim 1, is a means-plus-function term under §
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`112, ¶6. The term “component” is a nonce word and does not connote any
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`structure. Moreover, the identified function for this term “causing the control
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`signal to change from a first logic level towards a second logic level at a first rate”
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`does not provide any description structure for the “component.” Indeed, as
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`discussed above regarding “timer unit,” although the “first component” is recited
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`as being “within the timer unit,” the “first component” in claim 1 is specified using
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`purely functional language. (See supra section VIII.A.) Therefore, claim 1 does
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`not recite sufficiently definite structure for performing the above function.
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`Accordingly, the claimed “first component” is a means-plus-function term.
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`Looking to the specification, the ’302 patent discloses that transistor 303
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`causes control signal LPB to change from VCCI (“first logic level”) towards
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`ground (“second logic level”) at an initial rate where the rate is the change in
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`voltage (dv/dt) over time for LPB. (Ex. 1001, 6:8-13, 6: