R. JACOB (JAKE) BAKER, PH.D., P.E.
`
`Professor of Electrical and Computer Engineering
`Department of Electrical and Computer Engineering
`
`6775 Agave Azul Court
`Las Vegas, NV 89120
`
`(725) 777-3755
`
`Email: rjacobbaker@gmail.com
`Website: http://CMOSedu.com/jbaker/jbaker.htm
`
`
`
`
`EDUCATION
`Ph.D. in Electrical Engineering; December 1993; University of Nevada, Reno, GPA 4.0/4.0. Dissertation
`Title: Applying power MOSFETs to the design of electronic and electro-optic instrumentation.
`M.S. and B.S. in Electrical Engineering: May 1986 and 1988; University of Nevada, Las Vegas. Thesis
`Title: Three-dimensional simulation of a MOSFET including the effects of gate oxide charge.
`ACADEMIC EXPERIENCE
`January 1991 - Present: Professor of Electrical and Computer Engineering at the University of Nevada,
`Las Vegas from August 2012 to present. From January 2000 to July 2012 held various positions at
`Boise State University including: Professor (2003 – 2012), Department Chair (2004 - 2007), and
`tenured Associate Professor (2000 - 2003). From August 1993 to January 2000 was a
`tenured/tenure track faculty member at the University of Idaho: Assistant Professor (1993 - 1998)
`and then tenured Associate Professor (1998 - 2000). Lastly, from January 1991 to May 1993 held
`adjunct faculty positions in the departments of Electrical Engineering at the University of Nevada,
`Las Vegas and Reno. Additional details:
`• Research is focused on analog and mixed-signal integrated circuit design. Worked with multi-
`disciplinary teams (civil engineering, biology, materials science, etc.) on projects that have been
`funded by EPA, DARPA, NASA, Army, DMEA, and the AFRL.
`• Current research and development interests are:
`o Circuit design for the control, use, and storage of renewable energy using thermoelectric
`generators
`o Design of electrical/biological circuits and systems using electrowetting on dielectric for
`automating and controlling biological experiments
`o Design of readout integrated circuits (ROICs) for use with focal plane arrays (FPAs)
`o Heterogeneous integration of III-V photonic devices (e.g. FPAs and VCSELs) with CMOS
`o Methods (e.g., 3D packaging and capacitive interconnects) to reduce power consumption in
`semiconductor memories and digital systems
`o Analog and mixed-signal circuit design for communication systems, synchronization, energy
`storage, data conversion, and interfaces
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`•
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`o The design of writing and sensing circuitry for emerging nonvolatile memory technologies,
`focal planes, and displays
`(arrays)
`in nascent nanotechnologies
`(e.g. magnetic,
`chalcogenide)
`o Reconfigurable electronics design using nascent memory technologies
`o Finding an electronic, that is, no mechanical component, replacement for the hard disk
`drive using nascent fabrication technologies
`o Power electronics circuit design for consumers and consumer electronics
`Led, as chair, the department in graduate curriculum (MS and PhD), program development, and
`ABET accreditation visits.
`• Worked with established and start-up companies to provide technical expertise and identify
`employment opportunities for students.
`• Held various leadership and service positions including: ECE chair, graduate coordinator, college
`curriculum committee (chair), promotion and tenure committee, scholarly activities committee,
`faculty search committee, university level search committees, etc. Collaborate with College of
`Engineering faculty on joint research projects.
`• Taught courses in circuits, analog IC design, digital VLSI, and mixed-signal integrated circuit
`design to both on- and, via the Internet, off-campus students. Research emphasis in integrated
`circuit design using nascent technologies.
`INDUSTRIAL EXPERIENCE
`2013 - present: Working with Freedom Photonics and Attollo Engineering in the Santa Barbara area on
`the integration of optoelectronics with CMOS integrated circuits.
`2013 - present: Working with National Security Technologies, LLC,) on the Design of Integrated
`electrical/photonic application specific integrated circuit (ASIC) design.
`2013 - 2015: Consultant for OmniVision. Working on integrating CMOS image sensors with memory for
`very high-speed consumer imager products.
`2010 - 2013: Worked with Arete’ Associates on the design of high-speed compressive transimpedance
`amplifiers for LADAR projects and the design of ROIC unit cells. Work funded by the U. S. Air Force.
`2013: Cirque, Inc. Consulting on the design of analog-to-digital interfaces for capacitive touch displays
`and pads.
`2012: Consultant at Lockheed-Martin Santa Barbara Focal Plane Array. CMOS circuit design for the
`development and manufacture of infrared components and imaging systems with an emphasis on
`highest sensitivity Indium Antimonide (InSb) focal plane arrays (FPAs) in linear through large staring
`formats. Product groups include FPAs, integrated dewar assemblies (IDCAs), camera heads, high-
`speed interfaces between image processors and imaging systems, and infrared imaging systems.
`2010 - 2012: Working with Aerius Photonics (and then FLIR Inc. when Aerius was purchase by FLIR) on
`the design of Focal Plane Arrays funded (SBIRs and STTRs) by the U.S. Air Force, Navy, and Army.
`Experience with readout integrated circuits (ROICs) and the design/layout of photodetectors in
`standard CMOS.
`2009 - 2010: Sun Microsystems, Inc. (now Oracle) VLSI research group. Provided consulting on memory
`circuit design and proximity connection (PxC) interfaces to DRAMs and SRAMs for lower power and
`3D packaging.
`2009 - 2010: Contour Semiconductor, Inc. Design of NMOS voltage and current references as well as
`the design of a charge pump for an NMOS memory chip.
`1994 - 2008: Affiliate faculty (Senior Designer), Micron Technology. Designed CMOS circuits for DRAMs
`including DLLs (design is currently used in Micron’s DDR memory), PLLs for embedded graphics
`chips, voltage references and regulators, data converters, field-emitting display drivers, sensing for
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`MRAM (using delta-sigma data conversion topologies), CMOS active pixel imagers and sensors,
`power supply design (linear and switching), input buffers, etc. Worked on a joint research project
`between Micron and HP labs in magnetic memory using the MTJ memory cell. Worked on
`numerous projects (too many to list) resulting in numerous US patents (see following list).
`Considerable experience working with product engineering to ensure high-yield from the
`production line. Co-authored a book on DRAM circuit design through the support of Micron. Gained
`knowledge in the entire memory design process from fabrication to packaging. Developed,
`designed, and tested circuit design techniques for multi-level cell (MLC) Flash memory using signal
`processing (35 nm technology node).
`January 2008: Consultant for Nascentric located in Austin, TX. Provide directions on circuit operation
`(DRAM, memory, and mixed-signal) for fast SPICE circuit simulations.
`May 1997 - May 1998: Consultant for Tower Semiconductor, Haifa, Israel. Designed CMOS integrated
`circuit cells for various modem chips, interfaces, and serial buses.
`Summer 1998: Consultant for Amkor Wafer Fabrication Services, Micron Technology, and Rendition,
`Inc., Design PLLs and DLLs for custom ASICs and a graphics controller chip.
`Summers 1994 - 1995: Micron Display Inc. Designing phase locked loop for generating a pixel clock for
`field emitting displays and a NTSC to RGB circuit on chip in NMOS. These displays are miniature
`color displays for camcorder and wrist watch size color television.
`September - October 1993: Lawrence Berkeley Laboratory. Designed and constructed a 40 A, 2 kV
`power MOSFET pulse generator with a 3 ns rise-time and 8 ns fall-time for driving Helmholtz coils.
`Summer 1993: Lawrence Livermore National Laboratory, Nova Laser Program. Researched picosecond
`instrumentation, including time-domain design for impulse radar and imaging.
`December 1985 - June 1993: (from July 1992 to June 1993 employed as a consultant), E.G.&G. Energy
`Measurements Inc., Nevada, Senior Electronics Design Engineer. Responsible for the design and
`manufacturing of instrumentation used in support of Lawrence Livermore National Laboratory's
`Nuclear Test Program. Responsible for designing over 30 electronic and electro-optic instruments.
`This position provided considerable fundamental grounding in EE with a broad exposure to PC
`board design to the design of cable equalizers. Also gained experience in circuit design technologies
`including: bipolar, vacuum tubes (planar triodes for high voltages), hybrid integrated circuits, GaAs
`(high speed logic and HBTs), microwave techniques, fiber optic transmitters/receivers, etc.
`Summer 1985: Reynolds Electrical Engineering Company, Las Vegas, Nevada. Gained hands on
`experience in primary and secondary power system design, installation and trouble-shooting
`electric motors on mining equipment.
`MEMBERSHIPS IN PROFESSIONAL AND SCHOLARLY ORGANIZATIONS
`IEEE (student, 1983; member, 1988; senior member, 1997; Fellow, 2013)
`Member of the honor societies Eta Kappa Nu and Tau Beta Pi
`Licensed Professional Engineer
`HONORS AND AWARDS
`Tau Beta Pi UNLV Outstanding Professor of the Year in 2013 - 2016
`•
`• UNLV ECE Department Distinguished Professor of the Year in 2015
`IEEE Fellow for contributions to the design of memory circuits - 2013
`•
`• Distinguished Lecturer for the IEEE Solid-State Circuits Society, 2012 - 2015
`IEEE Circuits and Systems (CAS) Education Award - 2011
`•
`Twice elected to the Administrative Committee of the Solid-State Circuits Society, 2011 - 2016
`•
`Frederick Emmons Terman Award from the American Society of Engineering Education - 2007
`•
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`President’s Research and Scholarship Award, Boise State University - 2005
`•
`• Honored Faculty Member - Boise State University Top Ten Scholar/Alumni Association 2003
`• Outstanding Department of Electrical Engineering faculty, Boise State 2001
`Recipient of the IEEE Power Electronics Society’s Best Paper Award in 2000
`•
`• University of Idaho, Department of Electrical Engineering outstanding researcher award, 1998-99
`• University of Idaho, College of Engineering Outstanding Young Faculty award, 1996-97
`
`SERVICE
`Reviewer for IEEE transactions on solid-state circuits, circuits and devices magazine, education,
`instrumentation, nanotechnology, VLSI, etc. Reviewer for several American Institute of Physics
`journals as well (Review of Scientific Instruments, Applied Physics letters, etc.) Board member of
`the IEEE press (reviewed dozens of books and book proposals). Reviewer for the National Institutes
`of Health. Technology editor and then Editor-in-Chief for the Solid-State Circuits Magazine.
`Led the Department on ABET visits, curriculum and policy development, and new program
`development including the PhD in electrical and computer engineering. Provided significant
`University and College service in infrastructure development, Dean searches, VP searches, and
`growth of academic programs. Provided university/industry interactions including starting the ECE
`department’s advisory board. Held positions as the ECE department Masters graduate coordinator
`and coordinator for the Sophomore Outcomes Assessment Test (SOAT).
`Also currently serves, or has served, on the IEEE Press Editorial Board (1999-2004), as a member of the
`first Academic Committee of the State Key Laboratory of Analog and Mixed-Signal VLSI at the
`University of Macau, as editor for the Wiley-IEEE Press Book Series on Microelectronic
`Systems (2010-present), on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
`(2011-2016), as an Advisory Professor to the School of Electronic and Information Engineering at
`Beijing Jiaotong University, as the Technology Editor (2012-2014) and Editor-in-Chief (2015-2017)
`for the IEEE Solid-State Circuits Magazine, as a Distinguished Lecturer for the SSCS (2012-2015), and
`as the Technical Program Chair for the IEEE 58th 2015 International Midwest Symposium on Circuits
`and Systems, MWSCAS 2015.
`ARMED FORCES
`6 years United States Marine Corps reserves (Fox Company, 2nd Battalion, 23rd Marines, 4th Marine
`Division), Honorable Discharge, October 23, 1987
`TEXTBOOKS AUTHORED
`Baker, R. J., "CMOS Circuit Design, Layout and Simulation, Third Edition" Wiley-IEEE, 1174 pages. ISBN
`978-0470881323 (2010) Over 50,000 copies of this book’s three editions in print.
`Baker, R. J., “CMOS Mixed-Signal Circuit Design,” Wiley-IEEE, 329 pages. ISBN 978-0470290262 (second
`edition, 2009) and ISBN 978-0471227540 (first edition, 2002)
`Keeth, B., Baker, R. J., Johnson, B., and Lin, F., “DRAM Circuit Design: Fundamental and High-Speed
`Topics”, Wiley-IEEE, 2008, 201 pages. ISBN: 978-0-470-18475-2
`Keeth, B. and Baker, R. J., “DRAM Circuit Design: A Tutorial”, Wiley-IEEE, 2001, 201 pages. ISBN 0-7803-
`6014-1
`Baker, R. J., Li, H.W., and Boyce, D.E. "CMOS Circuit Design, Layout and Simulation," Wiley-IEEE, 1998,
`904 pages. ISBN 978-0780334168
`BOOKS, OTHER (edited, chapters, etc.)
`Saxena, V. and Baker, R. J., “Analog and Digital VLSI,” chapter in the CRC Handbook on Industrial
`Electronics, edited by J. D. Irwin and B. D. Wilamowski, CRC Press, 2009 second edition.
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`Baker, R. J., “CMOS Analog Circuit Design,” (A self-study course with study guide, videos, and tests.)
`IEEE Education Activity Department, 2000. ISBN 0-7803-4822-2 (with textbook) and ISBN 0-7803-
`4823-0 (without textbook)
`Baker, R. J., “CMOS Digital Circuit Design,” (A self-study course with study guide, videos, and tests.) IEEE
`Education Activity Department, 2000. ISBN 0-7803-4812-5 (with textbook) and ISBN 0-7803-4813-3
`(without textbook)
`Li, H.W., Baker, R. J., and Thelen, D., “CMOS Amplifier Design,” chapter 19 in the CRC VLSI Handbook,
`edited by Wai-kai Chen, CRC Press, 1999 (ISBN 0-8493-8593-8) and the second edition in 2007 (ISBN
`978-0-8493-4199-1)
`INVITED TALKS AND SEMINARS
`Have given over 50 invited talks and seminars at the following locations: AMD (Fort Collins), AMI
`semiconductor, Arizona State University, Beijing Jiaotong University, Boise State University,
`Carleton University, Carnegie Mellon, Columbia University, Dublin City University (Ireland), E.G.&G.
`Energy Measurements, Foveon, the Franklin Institute, Georgia Tech, Gonzaga University, Hong
`Kong University of Science and Technology, ICySSS keynote, IEEE Electron Devices Conference
`(NVMTS), IEEE Workshop on Microelectronics and Electron Devices (WMED), Indian Institute of
`Science (Bangalore, India), Instituto de Informatica (Brazil), Instituto Tecnológico y de Estudios
`Superiores de Monterrey (ITESM, Mexico), Iowa State University, Lawrence Livermore National
`Laboratory, Lehigh University, Lockheed-Martin, Micron Technology, Nascentric, National
`Semiconductor, Princeton University, Rendition, Saintgits College (Kerala, India), Southern
`Methodist University, Sun Microsystems, Stanford University, ST Microelectronics (Delhi, India),
`Temple University, Texas A&M University, Tower Semiconductor (Israel), University of Alabama
`(Tuscaloosa), University of Arkansas, University of Buenos Aires (Argentina), University of Houston,
`University of Idaho, University of Illinois (Urbana-Champaign), Université Laval (Québec City,
`Québec), University of Macau, University of Maryland, Université de Montréal (École Polytechnique
`de Montréal), Xilinx (Ireland), University of Nevada (Las Vegas), University of Nevada (Reno),
`University of Toronto, University of Utah, Utah State University, and Yonsei University (Seoul, South
`Korea).
`RESEARCH FUNDING (last 5 years only)
`Recent funding listed below. In-kind, equipment, and other non-contract/grant funding [e.g., MOSIS
`support, money for travel for invited talks, etc.] not listed.
`• Baker, R. Jacob, (2016-2017) "Testing and development of BiCMOS photodetectors and diagnostic
`instrumentation," Department of Energy, National Security Technologies, LLC, $181,605
`• Baker, R. Jacob, (2016-2017) "Dual-Mode, Extended Near Infrared, Focal Plane Arrays fabricated
`with a Commercial SiGe BiCMOS Process," DARPA, $41,892
`• Baker, R. Jacob, (2016-2018) “Advanced Printed Circuit Board Design Methods for Compact Optical
`Transceiver,” U.S. Army/DOD, $299,605
`• Baker, R. Jacob, (2016-2018) "High-Sensitivity Monolithic Silicon APD and ROIC," U.S. Air
`Force/DOD, $299,665
`• Baker, R. Jacob, (2015-2016) "Photodetectors and high-speed electronics using Silicon Germanium
`(SiGe) Bipolar/CMOS (BiCMOS) integrated circuits," Department of Energy, National Security
`Technologies, LLC, $100,000
`• Baker, R. Jacob, (2015-2016) “Advanced Printed Circuit Board Design Methods for Compact Optical
`Transceiver,” U.S. Army/DOD, $45,000
`• Baker, R. Jacob, (2015) "Quantum Cryptography Detector Chip," Defense MicroElectronics Activity
`(DMEA), $45,000
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`• Baker, R. Jacob, (2014-2015) "NSTec ASIC Integrated Circuit Collaboration," Department of
`Energy, National Security Technologies, LLC, $90,000
`• Baker, R. Jacob, (2014-2015) "Silicon Photonic-Electronic System Level Integration," U.S. Air
`Force/DOD, $54,607
`• Baker, R. Jacob, (2013-2014) "NSTec ASIC Integrated Circuit Collaboration," Department of
`Energy, National Security Technologies, LLC, $162,074
`• Baker, R. Jacob, (2013) "Design Software Setup," Department of Energy, National Security
`Technologies, LLC, $10,999
`• Campbell, K. A. and Baker, R. J., (2009-2012) "Reconfigurable Electronics and Non-Volatile Memory
`Research" funded by the Air Force Research Laboratory, $2,790,081
`• Baker, R. Jacob, (2010-2012) “Dual Well Focal Plane Array (FPA) Sensor,” U.S. Navy, $31,500
`• Baker, R. Jacob, (2011) “Readout-Integrated Circuit (ROIC) Development in Support of Corrugated
`Quantum Well Infrared Photo-detector (C-QWIP) Focal Plane Arrays (FPA) for Tactical Applications,”
`U.S. Army, $27,000
`• Baker, R. Jacob, (2011) “Monolithic CMOS LADAR Focal Plane Array (FPA) with a Photonic High-
`Speed Output Interface,” U.S. Air Force/DOD, $50,002
`GRANTED US PATENTS
`144. Baker, R. J., “Quantizing circuits having improved sensing,” 9,449,664, September 20, 2016.
`143. Baker, R. J., “Error detection for multi-bit memory,” 9,336,084, May 10, 2016.
`142. Baker, R. J. and Keeth, B., “Optical interconnect in high-speed memory systems,” 9,299,423,
`March 29, 2016.
`141. Baker, R. J., “Methods for sensing memory elements in semiconductor devices,” 9,299,405, March
`29, 2016.
`140. Baker, R. J., “Comparators for delta-sigma modulators,” 9,135,962, September 15, 2015.
`139. Baker, R. J., “Resistive memory element sensing using averaging,” 9,081,042, July 14, 2015.
`138. Baker, R. J., “Digital Filters with Memory,” 9,070,469, June 30, 2015.
`137. Baker, R. J., "Reference current sources,” 8,879,327, November 4, 2014.
`136. Baker, R. J. and Beigel, K. D., “Multi-resistive integrated circuit memory,” 8,878,274, November 4,
`2014.
`135. Baker, R. J., “Methods for sensing memory elements in semiconductor devices,” 8,854,899,
`October 7, 2014.
`134. Baker, R. J., “Quantizing circuits with variable parameters,” 8,830,105, September 9, 2014.
`133. Baker, R. J., “Integrators for delta-sigma modulators,” 8,754,795, June 17, 2014.
`132. Baker, R. J., “Methods of quantizing signals using variable reference signals,” 8,717,220, May 6,
`2014.
`131. Baker, R. J. and Keeth, B., “Optical interconnect in high-speed memory systems,” 8,712,249, April
`29, 2014.
`130. Baker, R. J., “Resistive memory element sensing using averaging,” 8,711,605, April 29, 2014.
`129. Baker, R. J., “Memory with correlated resistance,” 8,681,557, March 25, 2014.
`128. Baker, R. J., “Reference current sources,” 8,675,413, March 18, 2014.
`127. Baker, R. J., “Methods for sensing memory elements in semiconductor devices,” 8,582,375,
`November 12, 2013.
`126. Linder, L. F., Renner, D., MacDougal, M., Geske, J., and Baker, R. J., “Dual well read-out integrated
`circuit (ROIC),” 8,581,168, November 12, 2013.
`125. Li, W., Schoenfeld, A., and Baker, R. J., “Method and apparatus for providing symmetrical output
`data for a double data rate DRAM,” 8,516,292, August 20, 2013.
`124. Baker, R. Jacob, “Resistive memory element sensing using averaging,” 8,441,834, May 14, 2013.
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`storage
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`123. Qawi, Q. I., Drost, R. J., and Baker, R. Jacob, "Increased DRAM-array throughput using
`inactive bitlines," 8,395,947, March 12, 2013.
`122. Baker, R. Jacob, “Memory with correlated resistance,” 8,289,772, October 16, 2012.
`121. Lin, F. and Baker, R. Jacob, “Phase splitter using digital delay locked loops,” 8,218,708, July 10,
`2012.
`120. Baker, R. Jacob, “Subtraction circuits and digital-to-analog converters for semiconductor
`devices,” 8,194,477, June 5, 2012.
`119. Baker, R. J., “Digital Filters for Semiconductor Devices,” 8,149,646, April 3, 2012.
`118. Baker, R. J., “Error detection for multi-bit memory,” 8,117,520, February 14, 2012.
`117. Baker, R. J., “Integrators for delta-sigma modulators,” 8,102,295, January 24, 2012.
`116. Baker, R.
`J.,
`“Devices
`including analog-to-digital
`converters
`for
`internal
`locations,” 8,098,180, January 17, 2012.
`115. Baker, R. J. and Beigel, K. D., “Multi-resistive integrated circuit memory,” 8,093,643, January 10,
`2012.
`114. Baker, R. J., “Quantizing circuits with variable parameters,” 8,089,387, January 3, 2012.
`113. Baker, R. J., “Reference current sources,” 8,068,367, November 29, 2011.
`112. Baker, R. J., “Methods of quantizing signals using variable reference signals,” 8,068,046,
`November 29, 2011.
`111. Baker, R. J., “Systems and devices including memory with built-in self-test and methods of making
`using the same,” 8,042,012, October 18, 2011.
`110. Baker, R. J., “Memory with correlated resistance,” 7,969,783, June 28, 2011.
`109. Baker, R. J. and Keeth, B., “Optical interconnect in high-speed memory systems,” 7,941,056, May
`10, 2011.
`108. Baker, R. J., “K-delta-1-sigma modulator,” 7,916,054, March 29, 2011.
`107. Li, W., Schoenfeld, A., and Baker, R. J., “Method and apparatus for providing symmetrical output
`data for a double data rate DRAM,” 7,877,623, January 25, 2011.
`106. Lin, F. and Baker, R. J., “Phase splitter using digital delay locked loops,” 7,873,131, January 18,
`2011.
`105. Hush, G. and Baker, R. J., “Complementary bit PCRAM sense amplifier and method of
`operation,” 7,869,249, January 11, 2011.
`104. Baker, R. J., “Subtraction circuits and digital-to-analog converters for semiconductor devices,”
`7,839,703, November 23, 2010.
`103. Baker, R. J., “Digital Filters with Memory” 7,830,729, November 9, 2010.
`102. Baker, R. J., “Systems and devices including memory with built-in self test and methods of making
`using the same,” 7,818,638, October 19, 2010.
`101. Baker, R. J., “Integrators for delta-sigma modulators,” 7,817,073, October 19, 2010.
`100. Baker, R. J., “Digital filters for semiconductor devices,” 7,768,868, August 3, 2010.
`99. Baker, R. J., “Quantizing circuits with variable reference signals,” 7,733,262, June 8, 2010.
`98. Baker, R. J., “Quantizing circuits for semiconductor devices,” 7,667,632, February 23, 2010.
`97. Baker, R. J., and Beigel, K. D., “Multi-resistive integrated circuit memory,” 7,642,591, January 5,
`2010.
`96. Baker, R. J., “Offset compensated sensing for a magnetic random access memory,” 7,616,474,
`November 10, 2009.
`95. Baker, R. J., “Resistive memory element sensing using averaging,” 7,577,044, Aug. 18, 2009.
`94. Baker, R. J., “Quantizing circuits with variable parameters,” 7,538,702, May 26, 2009.
`93. Baker, R. J., “Method and system for reducing mismatch between reference and intensity paths in
`analog to digital converters in CMOS active pixel sensors,” 7,528,877, May 5, 2009.
`92. Baker, R. J., “Method and system for reducing mismatch between reference and intensity paths in
`analog to digital converters in CMOS active pixel sensors,” 7,515,188, April 7, 2009.
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`91. Taylor, J. and Baker, R. J., “Method and apparatus for sensing flash memory using delta-sigma
`modulation,” 7,495,964, February 24, 2009.
`90. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 7,489,575, February
`10, 2009.
`89. Baker, R. J., “Per column one-bit ADC for image sensors,” 7,456,885, November 25, 2008.
`88. Staples, T. and Baker, R. J., “Input buffer design using common-mode feedback,” 7,449,953,
`November 11, 2008.
`87. Li, W., Schoenfeld, A., and Baker, R. J., “Method and apparatus for providing symmetrical output
`data for a double data rate DRAM,” 7,421,607, September 2, 2008.
`86. Baker, R. J., “Methods for resistive memory element sensing using averaging,” 7,372,717, May 13,
`2008.
`85. Taylor, J. and Baker, R. J., “Method and apparatus for sensing flash memory using delta-sigma
`modulation,” 7,366,021, April 29, 2008.
`84. Hush, G. and Baker, R. J., “Method of operating a complementary bit resistance memory sensor
`and method of operation,” 7,366,003, April 29, 2008.
`83. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 7,330,390, February
`12, 2008.
`82. Baker, R. J., “Input and output buffers having symmetrical operating characteristics and immunity
`from voltage variations,” 7,319,620, January 15, 2008.
`81. Staples, T. and Baker, R. J., “Method and apparatus providing input buffer design using common-
`mode feedback,” 7,310,018, December 18, 2007.
`80. Baker, R. J., “Offset compensated sensing for a magnetic random access memory,” 7,286,428,
`October 23, 2007.
`79. Baker, R. J., and Cowles, T. B., “Method and apparatus for reducing duty cycle distortion of an
`output signal,” 7,271,635, September 18, 2007.
`78. Baker, R. J., and Cowles, T. B., “Method and apparatus for reducing duty cycle distortion of an
`output signal,” 7,268,603, September 11, 2007.
`77. Hush, G., Baker, R. J., and Moore, J., “Skewed sense AMP for variable resistance memory sensing,”
`7,251,177, July 31, 2007.
`76. Hush, G. and Baker, R. J., “Method of operating a complementary bit resistance memory sensor,”
`7,242,603, July 10, 2007.
`75. Li, W., Schoenfeld, A., and Baker, R. J., “Method and apparatus for providing symmetrical output
`data for a double data rate DRAM,” 7,237,136, June 26, 2007.
`74. Moore, J. and Baker, R. J., “Rewrite prevention in a variable resistance memory,” 7,224,632, May
`29, 2007.
`73. Baker, R. J., “Integrated charge sensing scheme for resistive memories,” 7,151,698, December 19,
`2006.
`72. Baker, R. J., “Adjusting the frequency of an oscillator for use in a resistive sense amp,” 7,151,689,
`December 19, 2006.
`71. Baker, R. J., “Resistive memory element sensing using averaging,” 7,133,307, Nov. 7, 2006.
`70. Lin, F. and Baker, R. J., “Phase detector for all-digital phase locked and delay locked loops,”
`7,123,525, October 17, 2006.
`69. Baker, R. J., and Beigel, K. D., “Integrated circuit memory with offset capacitor,” 7,109,545,
`September 19, 2006.
`68. Baker, R. J., “Input and output buffers having symmetrical operating characteristics and immunity
`from voltage variations,” 7,102,932, September 5, 2006.
`67. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 7,095,667, August
`22, 2006.
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`R. JACOB BAKER
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`66. Baker, R. J., “Offset compensated sensing for a magnetic random access memory,” 7,082,045, July
`25, 2006.
`65. Baker, R. J., “System and method for sensing data stored in a resistive memory element using one
`bit of a digital count,” 7,009,901, March 7, 2006.
`64. Hush, G. and Baker, R. J., “Complementary bit resistance memory sensor and method of
`operation,” 7,002,833, February 21, 2006.
`63. Lin, F. and Baker, R. J., “Phase detector for all-digital phase locked and delay locked loops,”
`6,987,701, January 17, 2006.
`62. Baker, R. J., “Adjusting the frequency of an oscillator for use in a resistive sense amp,” 6,985,375,
`January 10, 2006.
`61. Baker, R. J., “Method for reducing power consumption when sensing a resistive memory,”
`6,954,392, October 11, 2005.
`60. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 6,954,391, October
`11, 2005.
`59. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 6,954,390, October
`11, 2005.
`58. Lin, F. and Baker, R. J., “Phase splitter using digital delay locked loops,” 6,950,487, September 27,
`2005.
`57. Baker, R. J., “Method and apparatus for measuring current as in sensing a memory cell,”
`6,930,942, August 16, 2005.
`56. Baker, R. J., “Offset compensated sensing for a magnetic random access memory,” 6,917,534, July
`12, 2005.
`55. Baker, R. J., “Dual loop sensing scheme for resistive memory elements,” 6,914,838, July 5, 2005.
`54. Baker, R. J., “High speed low power input buffer,” 6,914,454, July 5, 2005.
`53. Baker, R. J., and Beigel, K. D., “Method for stabilizing or offsetting voltage in an integrated circuit,”
`6,913,966, July 5, 2005.
`52. Moore, J. and Baker, R. J., “PCRAM rewrite prevention,” 6,909,656, June 21, 2005.
`51. Baker, R. J., “Integrated charge sensing scheme for resistive memories,” 6,901,020, May 31, 2005.
`50. Hush, G., Baker, R. J., and Moore, J., “Skewed sense AMP for variable resistance memory sensing,”
`6,888,771, May 3, 2005.
`49. Baker, R. J., “Method for reducing power consumption when sensing a resistive memory,”
`6,885,580, April 26, 2005.
`48. Moore, J. and Baker, R. J., “PCRAM rewrite prevention,” 6,882,578, April 19, 2005.
`47. Baker, R. J., “Integrated charge sensing scheme for resistive memories,” 6,870,784, March 22,
`2005.
`46. Baker, R. J., “Sensing method and apparatus for a resistive memory device,” 6,859,383, February
`22, 2005.
`45. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 6,856,564, February
`15, 2005.
`44. Baker, R. J., “Offset compensated sensing for a magnetic random access memory,” 6,856,532,
`February 15, 2005.
`43. Baker, R. J., “Dual loop sensing scheme for resistive memory elements,” 6,829,188, Dec. 7, 2004.
`42. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 6,826,102, Nov. 30,
`2004.
`41. Baker, R. J., “Resistive memory element sensing using averaging,” 6,822,892, Nov. 23, 2004.
`40. Baker, R. J., “System and method for sensing data stored in a resistive memory element using one
`bit of a digital count,” 6,813,208, Nov. 2, 2004.
`39. Baker, R. J., “Wordline driven method for sensing data in a resistive memory array,” 6,809,981,
`Oct. 26, 2004.
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`Page 9
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`R. JACOB BAKER
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`Page 9 of 24
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`38. Baker, R. J., “Noise resistant small signal sensing circuit for a memory device,” 6,798,705, Sept. 28,
`2004.
`37. Baker, R. J., “Methods and apparatus for measuring current as in sensing a memory cell,”
`6,795,359, Sept. 21, 2004.
`36. Hush, G. and Baker, R. J., “Complementary bit PCRAM sense amplifier and method of operation,”
`6,791,859, Sept. 14, 2004.
`35. Baker, R. J., “Method and apparatus for sensing resistance values of memory cells,” 6,785,156,
`August 31, 2004.
`34. Lin, F. and Baker, R. J., “Phase detector for all-digital phase locked and delay locked loops,”
`6,779,126, August 17, 2004.
`33. Baker, R. J., and Lin, F. "Digital dual-loop DLL design using coarse and fine loops," 6,774,690,
`August 10, 2004.
`32. Hush, G., Baker, R. J., and Voshell, T., “Producing walking one pattern in shift register,” 6,771,249,
`August 3, 2004.
`31. Baker, R. J., “Sensing method and apparatus for resistance memory device,” 6,741,490, May 25,
`2004.
`30. Li, W., Schoenfeld, A., and Baker, R. J., “Method and apparatus for providing symmetrical output
`data for a double data rate DRAM,” 6,704,881, March 9, 2004.
`29. Baker, R. J., “Method and system for writing data in an MRAM memory device,” 6,687,179,
`February 3, 2004.
`28. Baker, R. J., “High speed digital signal buffer and method,” 6,683,475, January 27, 2004.
`27. Baker, R. J., “High speed low power input buffer,” 6,600,343, July 29, 2003.
`26. Baker, R. J., “Offset compensated sensing for magnetic random access memory,” 6,597,600, July
`22, 2003.
`25. Baker, R. J., “Sensing method and apparatus for resistive memory device,” 6,577,525, June 10,
`2003.
`24. Baker, R. J., “Method and apparatus for sensing resistance values of memory cells,” 6,567,297,
`May 20,