Paper No. ____
`Filed: October 7, 2016
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`PROMOS TECHNOLOGIES, INC.
`Patent Owner
`
`____________________
`
`U.S. Patent No. 6,195,302
`____________________
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,195,302
`
`
`
`
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`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`TABLE OF CONTENTS
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`
`INTRODUCTION ........................................................................................... 1 
`I. 
`II.  MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ................................... 1 
`III.  PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 2 
`IV.  GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.104(a) ..................... 2 
`PRECISE RELIEF REQUESTED AND GROUNDS RAISED
`V. 
`UNDER 37 C.F.R. § 42.104(b) ....................................................................... 2 
`A. 
`Claims for Which Review Is Requested ............................................... 2 
`B. 
`Statutory Grounds of Challenge ............................................................ 2 
`C. 
`Statement of Non-Redundancy ............................................................. 5 
`VI.  LEVEL OF ORDINARY SKILL IN THE ART ............................................. 5 
`VII.  OVERVIEW OF THE TECHNOLOGY, ’302 PATENT, AND
`PRIOR ART ..................................................................................................... 6 
`A. 
`Technology Background ....................................................................... 6 
`B. 
`The ’302 Patent ..................................................................................... 6 
`C.  Min ......................................................................................................... 7 
`VIII.  CLAIM CONSTRUCTION ............................................................................ 8 
`A. 
`“timer unit . . . generating a control signal” ........................................ 10 
`B. 
`“first component . . . causing the control signal to change from
`a first logic level towards a second logic level at a first rate” ............ 12 
`“second component . . . causing the control signal to change to
`the second logic level at a second rate” .............................................. 13 
`“delay unit . . . generating a delayed sense control signal” ................. 14 
`D. 
`IX.  DETAILED EXPLANATION OF GROUNDS ............................................ 16 
`
`C. 
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`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
`A.  Ground 1: Min Renders Obvious Claims 14 and 15 ........................... 16 
`1. 
`Claim 14 .................................................................................... 16 
`2. 
`Claim 15 .................................................................................... 34 
`B.  Ground 2: Min and Seo Render Obvious Claims 1-5, and 10-12 ....... 35 
`1. 
`Claim 10 .................................................................................... 35 
`2. 
`Claim 11 .................................................................................... 53 
`3. 
`Claim 12 .................................................................................... 55 
`4. 
`Claim 1 ...................................................................................... 56 
`5. 
`Claim 2 ...................................................................................... 72 
`6. 
`Claim 3 ...................................................................................... 72 
`7. 
`Claim 4 ...................................................................................... 72 
`8. 
`Claim 5 ...................................................................................... 73 
`C.  Ground 3: Min, Seo, and Schuster Render Obvious claim 6............... 74 
`D.  Ground 4: Min and Tobita Render Obvious Claims 16 and 17 .......... 76 
`1. 
`Claim 16 .................................................................................... 76 
`2. 
`Claim 17 .................................................................................... 77 
`Ground 5: Min and Schuster Render Obvious Claim 18 .................... 78 
`3. 
`Claim 18 .................................................................................... 78 
`CONCLUSION .............................................................................................. 80 
`
`E. 
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`ii
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`X. 
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`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
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`LIST OF EXHIBITS
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`
`
`
`
`Ex. 1001
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`U.S. Patent No. 6,195,302
`
`Ex. 1002
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`Declaration of R. Jacob Baker, Ph.D., P.E.
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`Ex. 1003
`
`Prosecution History of U.S. Patent No. 6,195,302
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`Ex. 1004
`
`U.S. Patent No. 5,140,199 to Seo (“Seo”)
`
`Ex. 1005
`
`UK Patent GB2246005B to Min et al. (“Min”)
`
`Ex. 1006
`
`European Patent EP 0597231 to Hardee (“Hardee EP”)
`
`Ex. 1007
`
`Schuster et al., “A 15-ns CMOS 64K RAM,” IEEE J. of Solid-State
`Circuits, Vol. SC-21, No. 5, Oct. 1986, pp.704-12 (“Schuster”)
`
`Ex. 1008
`
`Taur et al., Fundamentals of Modern VLSI Devices, 1998 (“Taur”)
`
`Ex. 1009
`
`U.S. Patent No. 4,980,799 to Tobita (“Tobita”)
`
`Ex. 1010
`
`Curriculum Vitae of R. Jacob Baker, Ph.D., P.E.
`
`Ex. 1011 Meng et al., “A Clock-Free Chip Set for High-Sampling Rate
`Adaptive Filters,” Journal of VLSI Signal Processing, Vol. 1, No. 4,
`1990, pp. 345-65 (“Meng”)
`
`Ex. 1012 Amrutur et al., “A Replica Technique for Wordline and Sense
`Control in Low-Power SRAM’s,” IEEE Journal of Solid-State
`Circuits, Vol. 33, No. 8, Aug. 1998, pp. 1208-19 (“Amrutur”)
`
`
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`iii
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`

`
`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`I.
`
`INTRODUCTION
`
`Samsung Electronics Co., Ltd. (“Petitioner”) requests inter partes review
`
`(“IPR”) of claims 1-6, 10-12, and 14-18 (“the challenged claims”) of U.S. Patent
`
`No. 6,195,302 (“the ’302 patent”) (Ex. 1001), which is currently assigned to
`
`ProMOS Technologies, Inc. (“Patent Owner”) according to USPTO records. For
`
`the reasons set forth below, the challenged claims should be found unpatentable
`
`and canceled.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Parties-in-Interest: Petitioner identifies the following as the real
`
`parties-in-interest: Samsung Electronics Co., Ltd.; Samsung Electronics America,
`
`Inc.; Samsung Semiconductor, Inc.; and Samsung Austin Semiconductor, LLC.
`
`Related Matters: Patent Owner has asserted the ’302 patent against
`
`Petitioner in ProMOS Technologies, Inc. v. Samsung Electronics Co., Ltd., et al.,
`
`No. 1:15-cv-00898-SLR-SRF (D. Del.). Petitioner is concurrently filing a petition
`
`challenging claims 1-6 and 10-12 of the ’302 patent. Petitioner respectfully
`
`requests that the Board institute each petition, as each presents distinct and non-
`
`redundant grounds. Patent Owner has also asserted U.S. Patent Nos. 6,849,897
`
`(“the ’897 patent”), 6,020,259 (“the ’259 patent”), 6,699,789 (“the ’789 patent”),
`
`6,088,270 (“the ’270 patent”), and 5,761,112 (“the ’112 patent”) in this action.
`
`Petitioner is also concurrently filing IPR petitions on the ’897, ’259, ’789, ’270,
`
`1
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`

`
`Petition for Inter Partes Review
`Patent No. 6,195,302
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`and ’112 patents.
`
`Counsel and Service Information: Lead counsel is Naveen Modi (Reg. No.
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`46,224), and backup counsel are (1) Joseph E. Palys (Reg. No. 46,508), (2) Chetan
`
`R. Bansal (Limited Recognition No. L0667), and (3) Arvind Jairam (Reg. No.
`
`62,759). Service information is Paul Hastings LLP, 875 15th St. N.W.,
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`Washington, D.C., 20005, Tel.: 202.551.1700, Fax: 202.551.1705, email: PH-
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`Samsung-Promos1-IPR@paulhastings.com.
`
` Petitioner consents to electronic
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`service.
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`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The PTO is authorized to charge all fees due at any time during this
`
`proceeding, including filing fees, to Deposit Account No. 50-2613.
`
`IV. GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.104(a)
`Petitioner certifies that the ’302 patent is available for IPR and Petitioner is
`
`not barred or estopped from requesting IPR on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED AND GROUNDS RAISED UNDER
`37 C.F.R. § 42.104(b)
`A. Claims for Which Review Is Requested
`Petitioner respectfully requests review of claims 1-6, 10-12, and 14-18 of
`
`the ’302 patent, and cancellation of these claims as unpatentable.
`
`Statutory Grounds of Challenge
`
`B.
`The challenged claims should be canceled as unpatentable on the following
`
`2
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`

`
`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`grounds:
`
`Ground 1: Claims 14-15 are unpatentable under pre-AIA 35 U.S.C. §103(a)
`
`based on UK Patent GB2246005B (“Min”) (Ex. 1005);
`
`Ground 2: Claims 1-5 and 10-12 are unpatentable under pre-AIA 35 U.S.C.
`
`§103(a) in view of Min and U.S. Patent No. 5,140,199 to Seo (“Seo”) (Ex. 1004);
`
`Ground 3: Claim 6 is unpatentable under 35 U.S.C. § 103(a) in view of Min,
`
`Seo, and Schuster et al., “A 15-ns CMOS 64K RAM,” IEEE J. of Solid-State
`
`Circuits, Vol. SC-21, No. 5, Oct. 1986, pp.704-12 (“Schuster”) (Ex. 1007);
`
`Ground 4: Claims 16 and 17 are unpatentable under 35 U.S.C. § 103(a) in
`
`view of Min and U.S. Patent No. 4,980,799 to Tobita (“Tobita”); and
`
`Ground 5: Claim 18 is unpatentable under 35 U.S.C. § 103(a) in view of
`
`Min and Schuster.
`
`The challenged claims are not entitled to a filing date earlier than February
`
`5, 1999.1 Min was published on August 31, 1994. Seo was issued on August 18,
`
`1992. Schuster was published in October 1986. Tobita was published on
`
`1 Petitioner takes no position on whether that the claims of the ’302 patent are
`
`supported by the provisional application (U.S. 60/118,737 filed on February 5,
`
`1999). Each of the prior art references that form the basis of the grounds asserted
`
`in this petition are prior art to the ’302 patent regardless of whether the claims of
`
`the ’302 patent are entitled to the February 5, 1999 provisional filing date.
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`3
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`December 25, 1990. Therefore, Min, Seo, Schuster, and Tobita are prior art to the
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`’302 patent at least under pre-AIA 35 U.S.C. § 102(b).
`
`Schuster was published in October 1986 in the IEEE Journal of Solid-State
`
`Circuits, Volume SC-21, Issue No. 5. This can be seen, for example, at the top of
`
`each page of Schuster. (Ex. 1007, 704-712.) Given that it was published in a well-
`
`known journal in October 1986, over a decade before the filing date of the ’302
`
`patent (id.), Schuster qualifies as prior art under pre-AIA 35 U.S.C. § 102(b). In
`
`fact, Schuster was cited by other articles well-before the ’302 patent was filed.
`
`(Ex. 1011, 363 (reference 7); Ex. 1012, 1219 (reference 21).)
`
`Among the references relied upon in this Petition, Min and Schuster were
`
`never considered by the Patent Office during prosecution of the ’302 patent. (Ex.
`
`1001, References Cited.) Seo is, however, listed on the face of the ’302 patent and
`
`was submitted in an information disclosure statement during prosecution. But
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`Petitioner presents Seo in a new light never considered by the Office. (Infra
`
`Section IX.) Moreover, Petitioner presents testimony from R. Jacob Baker, Ph.D.,
`
`P.E., (Ex. 1002), an expert in the field of the ’302 patent, who confirms that the
`
`relevant teachings of Seo alone or in combination with the other cited references
`
`discloses or suggests what is recited by the challenged claims. (Ex. 1002.) As
`
`such, consideration of Seo by the Patent Office during prosecution of the ’302
`
`patent should not preclude the Office from considering and adopting the grounds in
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`4
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`Petition for Inter Partes Review
`Patent No. 6,195,302
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`this petition that involve this reference.
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`Statement of Non-Redundancy
`
`C.
`Petitioner is filing a second IPR petition against the ’302 patent concurrent
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`with the filing of this petition. However, Petitioner’s proposed grounds for
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`institution in the two petitions are not redundant and the Board should institute
`
`review in both proceedings. The primary references applied in the two petitions
`
`disclose features of the challenged claims in different ways, and are based on
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`different combinations of references. For example, the primary reference in this
`
`petition (Min) does not explicitly disclose a circuit component that delays a signal,
`
`as required by claim elements 10(e) and 1(f). Instead, a secondary reference is
`
`relied upon to disclose that feature. In contrast, the primary reference at issue in
`
`the other petition discloses these claimed features. As such, Petitioner respectfully
`
`requests that the Board adopt all proposed Grounds in both of the petitions.
`
`VI. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art at the time of the alleged invention
`
`(“POSITA”) of the ’302 patent would have had at least a Bachelor’s degree in
`
`electrical engineering or equivalent thereof, and at least two to three years of
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`5
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`experience in design of semiconductor memory circuits. (Ex. 1002, ¶19)2 More
`
`education can supplement practical experience and vice versa. (Id.)
`
`VII. OVERVIEW OF THE TECHNOLOGY, ’302 PATENT, AND PRIOR
`ART
`A. Technology Background
`At the time of the alleged invention of the ’302 patent, it was well known
`
`that integrated circuit memories could include memory cell arrays consisting of
`
`thousands of memory cells arranged in a matrix of rows (word lines) and columns
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`(bit lines), with each memory cell located at or near the crossing of a bit line and
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`word line. (Ex. 1002, ¶37-38, citing Ex. 1009.) To read and write to the memory
`
`cells of a DRAM, other circuitry was known to be provided. (Id., ¶39.) For
`
`instance, the bit lines were often coupled into complementary bit line pairs, with
`
`each pair associated with a sense amplifier that amplifies the signal on the bit lines
`
`during a read operation and drives/controls the bit lines when data is being written
`
`into the memory cells. (Id.)
`
`The ’302 Patent
`
`B.
`The ’302 patent issued from U.S. application no. 09/492,276 filed on
`
`January 27, 2000 (Ex. 1003 at 4-26) and is directed to a memory device with sense
`
`
`2 Petitioner submits the declaration of R. Jacob Baker, Ph.D., P.E., (Ex. 1002), an
`
`expert in the field of the ’302 patent. (Ex. 1002, ¶5-15.)
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`6
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`amplifiers 101a-101c that are coupled to a high voltage line Vcc and ground via
`
`driver transistors 104 and 106, respectively, as shown in FIG. 1. (Ex. 1002, ¶40.):
`
`
`
`(Ex. 1001, FIG. 1; see also id., 4:40-5:4; Ex. 1002, ¶¶40-48.)
`
`
`
`The ’302 patent discloses circuitry for generating the LPB and LNB signals
`
`(FIG. 1 above). (Ex. 1002, ¶¶43-48.)
`
`C. Min
`Min discloses in FIG. 1A a conventional sense amplifier driving circuit
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`(including driving transistors Q1 and Q2, and INV1 and INV2) that drives a
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`plurality of sense amplifiers SA1-SAn. (Ex. 1005, 1:6-8, FIG. 1, 2:5-29.)
`
`
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`The sense amplifiers SA1-SAn in Min are connected to one another at node
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`LAP and at LAN and are connected to Vcc and Vss by driving transistors Q1 and
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`Q2, respectively. (Ex. 1005, FIG. 1A, 2:17-19; Ex. 1002, ¶54.) In this
`
`configuration, “the sense amplifiers are controlled by turn on and off operations of
`
`the driving transistors Q1, Q2.” (Ex. 1005, 3:17-20.)
`
`Min discloses a variation of the FIG. 1A sense amplifier driving circuit
`
`arrangement in FIG. 1B where the sense amplifier driving circuitry now includes a
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`driving transistor Q11-Q1n and Q21-Q2n for each sense amplifier SA1-SAn. (Ex.
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`1005, FIG. 1B, 4:13-23; Ex. 1002, ¶55.)
`
`The sense amplifier driving circuits in both FIG. 1A and FIG. 1B, however,
`
`had some disadvantages. (Ex. 1005, 5:11-34; Ex. 1002, ¶56.) To overcome these
`
`disadvantages, Min discloses several exemplary sense amplifier driving circuits.
`
`(Ex. 1005, 12:5-13:15; Ex. 1002, ¶¶56-64.) One such sense amplifier driving
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`circuit is disclosed in FIG. 9 and another sense amplifier driving circuit is shown in
`
`FIG. 10. (Ex. 1005, 13:5-15, 27:22-30, 30:5-8.)
`
`VIII. CLAIM CONSTRUCTION
`The claims of the ’302 patent should be given their broadest reasonable
`
`construction because it has not and will not expire before a final written decision is
`
`issued in this proceeding. 37 C.F.R. § 42.100(b).
`
`Furthermore, to determine whether a claim should be interpreted under §
`
`112, ¶6, “[t]he standard is whether the words of the claim are understood by
`
`persons of ordinary skill in the art to have a sufficiently definite meaning as the
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`8
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`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
`name for structure. Williamson v. Citrix Online LLC, 792 F.3d 1339, 1349 (Fed.
`
`Cir. 2015). “[T]he failure to use the word ‘means’ [in a claim] creates a rebuttable
`
`presumption . . . that § 112, para. 6 does not apply.” Id. at 1348. “[T]he
`
`presumption can be overcome and § 112, para. 6 will apply if the challenger
`
`demonstrates that the claim term fails to recite sufficiently definite structure or else
`
`recites function without reciting sufficient structure for performing that function.”
`
`Id. (internal quotes omitted).
`
`As set forth herein, Petitioner provides the broadest reasonable construction
`
`for certain claim terms below. Any term not interpreted below should be
`
`interpreted in accordance with its plain and ordinary meaning under the broadest
`
`reasonable interpretation standard.3
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`3 Because of the different claim interpretation standards used in this proceeding
`
`and in district courts, any claim interpretations submitted or implied herein for the
`
`purpose of this proceeding are not binding upon Petitioners in any litigation related
`
`to the ’302 patent. Specifically, any interpretation or construction of the claims
`
`presented herein, either implicitly or explicitly, should not be viewed as
`
`constituting, in whole or in part, Petitioner’s interpretation of such claims in any
`
`underlying litigations involving the ’302 patent. Moreover, Petitioner does not
`
`concede that the challenged claims are not indefinite, which is something that
`
`cannot be pursued in this proceeding under the Rules.
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`9
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`

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`Petition for Inter Partes Review
`Patent No. 6,195,302
`
`A.
`“timer unit . . . generating a control signal”
`Claim 1 recites the term “timer unit . . . generating a control signal.”4 The
`
`term “timer unit” is a means-plus function term under 35 U.S.C. § 112, ¶6.
`
`Claim 1 recites that “a timer unit having an output coupled to the control
`
`electrode and generating a control signal.” This claim recites function (“generating
`
`a control signal”) without reciting sufficient structure for performing that function.
`
`A timer unit as recited in claim 1 does not connote any structure. Indeed, the
`
`identified function for this term, “having an output coupled to the control
`
`electrode” only specifies where the output of the timer unit is coupled and does not
`
`specify structure for the timer unit itself. Like the term “module” in Williamson,
`
`the recitation of a timer “unit” in claim 1 does not provide a sufficiently definite
`
`structure for performing the function of “generating a control signal.” Williamson,
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`792 F.3d at 1350 (“the word ‘module’ does not provide any indication of structure
`
`
`4 The term “the timer unit output” in claim 12 does not have any antecedent basis,
`
`and thus claim 12 is indefinite. However, for purposes of this proceeding,
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`Petitioner assumes that the term “timer unit output” in claim 12 means an output
`
`from a clock or timer, such as a “clock signal.” Under that assumption, however,
`
`“the timer unit output” in claim 12 should not be construed in a manner similar to
`
`the recited “timer unit . . . generating a control signal” in claim 1 discussed above.
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`10
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`because it sets forth the same black box recitation of structure for providing the
`
`same specified function as if the term ‘means’ had been used.”).
`
`Although claim 1 recites “a first component” and “a second component” that
`
`are both “within the timer unit,” those “component[s]” are specified in the claim
`
`using purely functional language, i.e., describing what they do. Therefore, those
`
`“component[s]” do not impart sufficient structure for performing the recited
`
`function of the “timer unit.” Therefore, although “means” is not recited in this
`
`claim, the presumption that § 112, ¶6 does not apply is overcome in this instance,
`
`and “timer unit” is a means-plus-function term.
`
`Construing a means-plus-function claim term requires that the function
`
`recited in the claim term be first identified; then, the written description of the
`
`specification must be consulted to identify the corresponding structure that
`
`performs the identified function and equivalents thereof. Williamson, 792 F.3d
`
`1339 at 1351; see also Gracenote, Inc. v. Iceberg Indus., LLC, IPR2013-00551,
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`Paper No. 6 at 15 (Feb. 28, 2014).
`
`The written description of the ’302 patent discloses that the function of
`
`“generating a control signal” is performed by at least a pair of transistors and one
`
`or more circuit components that delay a signal. For example, the ’302 patent
`
`discloses that the pair of transistors 303, 308 and delay element 307 generate
`
`control signal LPB, and that the pair of transistors 313, 308 and delay unit 317
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`generate control signal LNB. (Ex. 1001, 5:57, 6:7-21, FIG. 3.)
`
`For purposes of this proceeding, resistors 306 and 316 should not be
`
`considered as part of the corresponding structure, because the specification of
`
`the ’304 patent discloses that that “resistors 306 and 316 can be eliminated and rise
`
`time of the first and second stage controlled by relative transistor sizes.” (Id., 6:31-
`
`33.)
`
`Therefore, for purposes of this proceeding, the corresponding structure for
`
`the identified function for this term is “at least a pair of transistors and one or more
`
`circuit components that delay a signal” and its equivalents.
`
`B.
`
`“first component . . . causing the control signal to change from a
`first logic level towards a second logic level at a first rate”
`
`This term, which appears in claim 1, is a means-plus-function term under §
`
`112, ¶6. The term “component” is a nonce word and does not connote any
`
`structure. Moreover, the identified function for this term “causing the control
`
`signal to change from a first logic level towards a second logic level at a first rate”
`
`does not provide any description structure for the “component.” Indeed, as
`
`discussed above regarding “timer unit,” although the “first component” is recited
`
`as being “within the timer unit,” the “first component” in claim 1 is specified using
`
`purely functional language. (Supra section VIII.A.) Therefore, claim 1 does not
`
`recite sufficiently definite structure for performing
`
`the above function.
`
`Accordingly, the claimed “first component” is a means-plus-function term.
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`12
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`Looking to the specification, the ’302 patent discloses that transistor 303
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`causes control signal LPB to change from VCCI (“first logic level”) towards
`
`ground (“second logic level”) at an initial rate where the rate is the change in
`
`voltage (dv/dt) over time for LPB. (Ex. 1001, 6:8-13, 6:31-33, FIG. 3.) The ’302
`
`patent also discloses that transistor 313 causes control signal LNB to change from
`
`ground (“first logic level”) towards VCCI (“second logic level”) at an initial rate
`
`where the rate is the change in voltage (dv/dt) over time for LNB. (Id., 6:11-13,
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`6:31-33, FIG. 3.) Accordingly, for both the LPB and LNB control signals, the
`
`corresponding structure is transistor 303 and transistor 313, respectively.
`
`Therefore, for purposes of this proceeding, the corresponding structure for
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`the identified function the claimed “first component” is “a first transistor” and its
`
`equivalents.
`
`C.
`
`“second component . . . causing the control signal to change to the
`second logic level at a second rate”
`
`This term, which appears in claim 1, is a means-plus-function term under §
`
`112, ¶6. As noted above, “component” does not connote any structure. Also, the
`
`identified function for this term, “causing the control signal to change to the
`
`second logic level at a second rate,” does not provide any indication of the
`
`structure for the “second component.” As discussed above regarding “timer unit,”
`
`although the “second component” is recited as being “within the timer unit,” the
`
`“second component” in claim 1 is specified using purely functional language.
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`13
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`Petition for Inter Partes Review
`Patent No. 6,195,302
`(Supra section VIII.A.) Therefore, the claimed “second component” is a means-
`
`plus-function term.
`
`The ’302 patent discloses that transistor 308, when turned on, causes control
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`signal LPB to be pulled down toward ground (“change to the second logic level”),
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`which causes LPB to “fall to the ground voltage with a high dv/dt.” (Ex. 1001,
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`6:17-18; see also id., FIG. 3.) The ’302 patent also discloses that transistor 318,
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`when turned on, causes control signal LNB to be pulled up to VCCI rapidly
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`without the dv/dt limiting effect of resistor 316. (Id., 6:18-21; see also id., FIG. 3.)
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`Accordingly, for both the LPB and LNB control signals, the corresponding
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`structure is transistor 308 and transistor 318, respectively.
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`Therefore, for purposes of this proceeding, the corresponding structure for
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`the identified function the claimed “second component” is “a second transistor”
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`and its equivalents.
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`“delay unit . . . generating a delayed sense control signal”
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`D.
`This term, which appears in claim 10, is a means-plus-function term under §
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`112, ¶6. The term “delay unit” does not connote any structure and the identified
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`function for this term, “generating a delayed sense control signal,” provides no
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`guidance as to the structure. The “delay unit” is specified as being “coupled to the
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`sense control signal node,” but that does not specify structure for the “delay unit”
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`itself, and the “delay unit” is specified using purely functional language.
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`Therefore, claim 10 does not recite sufficient structure for performing the above
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`function. Accordingly, the term “delay unit” is a means-plus-function term.
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`The ’302 patent discloses that delay element 307 performs the above
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`function regarding generating a signal at the gate of transistor 308 (“delayed sense
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`control signal”) that controls signal LPB, and that delay unit 317 performs the
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`above function regarding generating a signal at the gate of transistor 318 (“delayed
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`sense control signal”) that controls signal LNB. (Ex. 1001, 6:15-21, FIG. 3.)
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`The ’302 patent does not specify the circuit components that constitute delay
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`element 307. That is, the ’302 patent does not specify delay 307 and delay 317 as
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`anything more than a black box. To the extent the Board finds such disclosure in
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`the ’302 patent as describing sufficient structure for the claimed “delay unit,” and
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`that claim 10 is somehow capable of being construed, Petitioner proposes that
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`“delay unit” be construed as one or more circuit components that delay a signal.
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`(Ex. 1001, 6:15-21, FIG. 3.) Therefore, for purposes of this proceeding, the
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`corresponding structure for the identified function for this term is “one or more
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`circuit components that delay a signal” and its equivalents.
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`Patent No. 6,195,302
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`IX. DETAILED EXPLANATION OF GROUNDS
`A. Ground 1: Min Renders Obvious Claims 14 and 15
`1.
`Claim 14
`a)
`A method for generating a control signal for
`controlling the operation of sense amplifier driver transistors in
`an integrated circuit memory device comprising:
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`To the extent that the preamble is determined to be limiting, Min discloses
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`this feature. (Ex. 1002, ¶¶75-78.)
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`With respect to FIG. 9, Min discloses a “sense amplifier driving circuit[]”
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`where transistor Q110 drives “a plurality of sense amplifiers.” (Ex. 1005, 27:22-30,
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`FIG. 9.) Min discloses a method for operating the driving circuit. (Ex. 1005,
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`29:15-30:3.) For example, Min explains that the driving circuit controls “the
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`current Icca flowing through the driver transistor Q110,” which controls the
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`voltage at node LAP. (Id., 29:15-30:3, FIG. 9.) A POSITA would have understood
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`that the current Icca depends on the gate voltage (“control signal”) of transistor
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`Q110 and the driving circuit of FIG. 9 controls the gate voltage of Q110. (Ex.
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`1002, ¶76; supra Section VII.C.) Driving transistor Q110 is a “sense amplifier
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`driver transistor” because it “driv[es] a plurality of sense amplifiers.” (Ex. 1005,
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`27:28-30.) Min also discloses the driving circuit of FIG. 9 may control the gate
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`voltage of more than one driving transistor instead a single driving transistor Q110.
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`(Ex. 1005, 28:4-8.) Accordingly, Min discloses “[a] method for generating a
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`control signal for controlling the operation of sense amplifier driver transistors”
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`(emphasis added). (Ex. 1002, ¶76.)
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`A POSITA would have understood Min discloses the driving transistors
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`(“sense amplifier driver transistors”) are “in an integrated circuit memory device,”
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`because Min relates to a “sense amplifier driving circuit which is suitable for use in
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`a high density semiconductor memory device.” (Ex. 1005, 1:4-9; see also id.,
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`12:12-13; Ex. 1002, ¶78; supra section VII.C; citations and analysis below for the
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`remaining elements of this claim.)
`
`b)
`providing a sense amplifier drive transistor having
`a control terminal coupled to receive the control signal and
`having a power node for supplying current to a preselected
`number of sense amplifiers;
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`Min discloses or suggests this feature. (Ex. 1002, ¶¶79-84.) As discussed
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`above for claim 14(a), the driving circuit of FIG. 9 controls the gate voltage of
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`transistor Q110, or a plurality of driving transistors, which drives a “plurality of
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`sense amplifiers.” (Ex. 1005, 27:28-30, 28:4-8; Ex. 1002, ¶79.)
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`FIG. 9 does not provide explicit details regarding how the plurality of
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`driving transistors would be connected to the “plurality of sense amplifiers.” (Id.)
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`However, FIG. 1B discloses such a configuration. (Ex. 1005, FIG. 1B.) In
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`particular, Min identifies problems with the driving circuitry that drives sense
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`amplifiers SA1-SAn in the conventional sense amplifier driving circuit of FIG. 1B.
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`(Ex. 1005, 5:11-34.) To overcome these disadvantages, Min discloses several
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`exemplary sense amplifier driving circuits, one of which is the sense amplifier
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`driving circuit of FIG. 9. (Id., 12:5-13:15, 27:22-26; Ex. 1002, ¶80.) A POSITA
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`would have been motivated to replace, and would have known how to replace, the
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`conventional driving circuitry in the top half of FIG. 1B with the driving circuit of
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`FIG. 9 such that the driving circuitry of FIG. 9 drives a plurality of driving
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`transistors Q11-Q1n. (Ex. 1002, ¶80.) A POSITA would have known how to
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`combine the driving circuit of FIG. 9 with the sense amplifier configuration of FIG.
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`1B because driving transistor Q110 in FIG. 9 drives latch node LAP, which is also
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`the latch node that is driven by the “plurality of driving transistors Q11-Q1N” in
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`FIG. 1B. (Id., ¶80; Ex. 1005, 29:21-29, FIG. 9, 4:13-23, FIG. 1B; supra Section
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`VII.C.) The combination may be pictorially represented as follows:
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`(Ex. 1005, FIG. 1B (annotated); Ex. 1002, ¶80.) The same configuration can also
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`be pictorially represented as:
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`
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`(Ex. 1005, FIG. 1B, FIG. 9 (annotated), 28:4-8 (explaining that Q110 can be
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`replaced by multiple driving transistors); Ex. 1002, ¶80.)
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`
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`A POSITA would have found the above combination of FIG. 9 and FIG. 1B
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`obvious because the driving circuit of FIG. 9 solves some of the problems
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`associated with conventional driving circuits (e.g., conventi