`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`____________
`
`Record of Oral Hearing
`Held: December 6, 2017
`____________
`
`
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`DAVID M. HOFFMAN, ESQUIRE
`JEFFREY SHNEIDMAN, ESQUIRE
`Fish & Richardson
`One Congress Plaza
`111 Congress Avenue, Suite 810
`Austin, Texas 78701
`
`ON BEHALF OF PATENT OWNER:
`KENNETH WEATHERWAX, ESQUIRE
`NATHAN LOWENSTEIN, ESQUIRE
`Lowenstein & Weatherwax, LLP
`1880 Century Park East
`Suite 815
`Los Angeles, California 90067
`
`
`
`
`
`
`
`The above-entitled matter came on for hearing on Wednesday,
`December 6, 2017, commencing at 1:00 p.m., at the U.S. Patent and
`Trademark Office, 600 Dulany Street, Alexandria, Virginia.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
` 2
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`
`P R O C E E D I N G S
`- - - - -
`JUDGE PARVIS: Good afternoon, everyone. This is an oral
`argument in IPR2017-00114 and IPR2017-00116. The challenged
`patents are U.S. patent numbers 7,206,978 B2 and 7,334,150 B2. Patent
`owner is Polaris Innovations Limited. Petitioner is Kingston Technology
`Company, Incorporated. I'm Administrative Patent Judge Parvis. Judge
`Medley is next to me and Judge Clements is appearing remotely.
`At this time we would like counsel to introduce yourselves,
`your partners and guests, starting with petitioner. Please use the
`microphone.
`MR. HOFFMAN: Your Honor, David Hoffman on behalf of
`the petitioner, Kingston. With me is my colleague, Mr. Jeff Shneidman
`as well as my colleague, Martha Hopkins.
`MR. LOWENSTEIN: Nathan Lowenstein of Lowenstein
`Weatherwax with lead counsel, Ken Weatherwax, and our colleague,
`Farrokh Aminifar.
`JUDGE PARVIS: Thank you. Before we begin, we want to
`remind the parties that this hearing is open to the public and a full
`transcript of it will become part of the record. As you know from our
`oral hearing order of November 13, 2017, each side is allotted a total of
`an hour and a half per side to present its case for the two proceedings.
`Because the petitioner has the burden to show unpatentability of the
`claims, petitioner will proceed first followed by the patent owner.
`Petitioner will begin by presenting its case regarding the challenged
`
`
`
`
` 3
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`claims and the grounds for which the Board instituted review in the
`proceedings. Patent owner will present its rebuttal to petitioner's case.
`Petitioner may reserve some time for rebuttal to patent owner's
`presentation.
`Also, please keep in mind whatever is projected on the screen
`will not be viewable by anyone reading the transcript or the judge
`appearing remotely. When you refer to a demonstrative slide or other
`document on the screen, please state in the microphone information to
`identify the document you are referring to such as petitioner's
`demonstratives and the slide number or the exhibit number and the page
`number. The judge appearing remotely has copies of the parties'
`demonstratives.
`So any time you are ready, counsel for petitioner, you may
`proceed.
`MR. HOFFMAN: One question, Your Honor, the parties had
`envisioned doing the 114 first with the petitioner opening and then a
`response and then back to petitioner and then separately doing the 116
`IPR. Is that acceptable?
`JUDGE PARVIS: The parties both agreed to that?
`MR. HOFFMAN: I believe so.
`MR. LOWENSTEIN: Yes.
`JUDGE PARVIS: That's fine.
`MR. HOFFMAN: Your Honor, my colleague, Mr. Shneidman,
`will be presenting.
`JUDGE PARVIS: You may proceed.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 4
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`MR. SHNEIDMAN: Thank you, Your Honors. My name is
`Jeffrey Shneidman. I represent the petitioner, Kingston. I would like to
`take about 20 minutes and reserve my remainder of time for rebuttal.
`I would like to talk to you today, turning to slide 2, about four
`things. The first is to introduce the claim technology and the '978 patent
`in particular and why it was allowed by the Patent Office. I then want to
`discuss the Raynham-based and Humphrey-based combinations that
`render the instituted claims obvious. Because Raynham was instituted on
`all of the claims, I'll be focusing there. And Humphrey is a secondary
`argument, so it does not address claim 14. And then I will close with a
`brief note about patent owner's expert's understanding of what a person of
`ordinary skill in the art is and why petitioner believes the Board should
`not rely on the patent owner's expert in this case for its evidence.
`Turning to slide 4, the '978 patent is about putting well-known
`circuitry on a memory chip. This is undisputed. On the left we have two
`XOR gates on a chip that is doing error detection on behalf of five
`DRAMs, and on the right of the slide we have that same XOR gate error
`detection circuitry distributed to the DRAMs. So it's taking this circuit
`and moving it from one chip to another.
`Moving to slide 5, during the prosecution, the applicant had a
`great deal of difficulty getting this out of the office as an issued patent,
`and it was only after the applicant amended to clarify that each circuit
`unit consists of a single integrated circuit memory chip that the patent
`was allowed. And so in our view, the patent is allowed explicitly
`because the claim they were moving to memory on-chip error detection.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 5
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`One comment, this patent issued prior to KSR. So short of a
`teaching, suggestion or motivation in Phelps, the office was obligated to
`issue the patent. We think that had Raynham or Humphrey been before
`the examiner or the Raynham- or Humphrey-based combinations, that the
`outcome would have been different.
`So I said the patent issued because of the memory on-chip error
`detection. If we move to slide 6, the Raynham combinations render all of
`the instituted claims obvious. If we jump to the bottom here and you
`look at Raynham, its title is DRAM On-Chip Error Correction/Detection.
`And this is a full 11 years prior to the '978 priority date.
`I do not believe that the patent owner disputes that Raynham
`discloses every element of the claims except for one which we'll talk
`about. The patent owner does not address any of the later bases for
`institution on grounds with respect to claims 6, 8 and 9. And unless the
`Board has questions on those, we would ask the Board to reach the same
`findings it did on institution for the reasons that we gave in our petition.
`So here is Raynham and Seyyedy, which Seyyedy on the
`bottom shows in the prior art a series of DRAMs. Raynham on top is
`about DRAM on-chip error correction/detection. I do not believe that the
`patent owner challenges that there would be reason to combine Raynham
`and Seyyedy. I did not see anything in the patent owner response.
`And indeed, there is on slide 8 ample reason to combine.
`Raynham provides a reason such that the requirement for transmitting
`error correction data over a bus represents a bottleneck in the error
`correction and detection process. And the additional references that we
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 6
`
`
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`cite below show that certainly it was known at the time of the '978 patent
`that you would want to perform error detection on a chip.
`Moving to slide 9, this is claim 1 of the '978 patent. There is no
`dispute in this trial over most of these elements. A circuit module
`comprising, module board, a plurality of circuit units, a bus, none of
`these are in dispute. And so it is within the wherein clause, excuse me,
`that there is a dispute between the parties. I want to zoom in on slide 10
`just on this wherein clause so it's easier to see.
`JUDGE PARVIS: Patent owner raised an argument that
`petitioner is pursuing two different claim constructions, one in these
`proceedings and one in District Court. Has the District Court issued a
`claim construction order?
`MR. SHNEIDMAN: My understanding, and I'm not counsel in
`that case is that, no, but we do not think so. Patent owner also, I will
`note, takes different claim constructions in the matter below. We believe
`that there is a difference in standard between Phillips and the BRI and
`whether or not the argument that the patent owner made to the District
`Court with respect to the difference in standards, whether or not that
`issue of law will be resolved in Kingston's favor is going to be a matter
`for the District Court. My understanding is that case is stayed.
`JUDGE PARVIS: The District Court proceedings have been
`
`stayed?
`
`
`
`
`
`MR. SHNEIDMAN: That's my understanding.
`JUDGE PARVIS: Thank you.
`
` 7
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`MR. SHNEIDMAN: So again, on claim 10 -- or excuse me, on
`slide 10, I'm highlighting or underlining, I suppose, the two areas where
`the parties have a dispute. The first is providing an indication signal.
`The second is based on a combination of signals received.
`Slide 11 points out Kingston's position, petitioner's position that
`the patent owner is adding nonexistent claim limitations into the set. And
`what I mean by that is there is at least four explicit limitations that are
`provided in the patent owner response that aren't supported by the claim
`language and which are not supported by the patent. The first is
`providing an indication signal. And the limitation that the patent owner
`adds is that this is a temporal limitation, that you must provide an
`indication signal before data is stored in the memory chip. Elsewhere in
`paper 17, the patent owner response at page 45, there is an argument that
`Raynham does not meet this limitation because it checks for errors not
`when the data was received. Again, there's nothing here to say when the
`indication signal is provided. You could have received data some time
`ago and provided an indication signal based on the data that you
`received. There's nothing there.
`The second explicit construction that they make is that signals
`received cannot include, quote, control signals or signals, quote,
`necessary for the logistics of the disclosed error correction operation or
`signals necessary for, quote, any other plausible operation. And this is
`just too broad -- well, I guess too limiting a construction.
`I want to also point out there's an implicit construction that they
`are imposing on the words "based on." And I believe that based on the
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 8
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`slides, the demonstratives that they have presented, they are going to
`present to you a version of "based on" that only looks at the time
`immediately prior to the time that the indication signal is sent, and that's
`not a temporal constraint that's correct. I believe they are also going to
`argue or claim that the petitioner's view of "based on" includes anything
`since the start of time. I think that's their Big Bang Theory even if it has
`nothing to do with the memory chip. And that's not correct either.
`Indeed, there are some very specific signals that are received on the
`plurality of lines of the sub-bus connected to the memory in Raynham
`and Humphrey that the indication signal is based on.
`So moving to slide 12, here is the overview picture of
`Raynham. Raynham provides an indication signal 42 which is shown on
`the right-hand side here based on the combination of the signals received
`into this block 50.
`And if we go in to slide 13, 13, 14 and 15 are all sort of an
`animation PDF of how this happens. And this is, if you look at
`Raynham, column 7, lines 3 through 32, it describes how this indication
`signal and the terms of the '978 patent or the error signal in terms of
`Raynham is provided.
`So first the address signals come in over a 10-bit bus that's
`depicted on line 62, the notation 10. The RAS -- yes, this is slide 13, 14
`and 15. The RAS signal 58 is asserted. The address signals are
`temporarily stored in the row address buffers and the combined and
`decoded in the row decoder. And then the signals are used to access the
`memory array. The RAS signal assertion causes the address signals next
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 9
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`to be combined. After the ECC signal is asserted, what Raynham teaches
`in column 7 is when the WE signal 54 in the upper left is raised, that
`causes the chip to perform the error detection and a possible correction
`process. And if there are more errors than were correctable, then ECC
`puts outset an indication signal on line 42.
`JUDGE PARVIS: Is there somewhat of an agreement between
`the petitioner and the patent owner as to the data? In other words, is
`petitioner agreeing that it is stored data that is checked and an indication
`signal unit is making its determination based on data that is already
`stored? The signals that are coming in that you should -- you have
`highlighted on the slide 16, those are control signals and address signals;
`is that correct?
`MR. SHNEIDMAN: So to your question, I think it's fair that
`the patent owner says that it's based on a combination of stored data.
`And I believe that that's correct with the note that the stored data, of
`course, is simply stored signals. It's the signals that have come in
`provided that data just perhaps, you know, a moment ago. And so --
`JUDGE PARVIS: Is it possible that that data has been stored a
`lot longer?
`MR. SHNEIDMAN: I think it would be possible and that there
`would be no temporal limitation in the claim so long as the indication
`signal is based on a combination say the signals received. It doesn't say
`the signals received in the last five seconds.
`So the next dispute is really with respect to the check signal.
`This is now on slide 17. Slide 18, Raynham does disclose a check signal.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 10
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`The petitioner's expert, in looking at the portion of the claim in his
`declaration regarding comprising a check signal, input for receiving a
`check signal, identifies a check signal. It says that it's this error
`correction code ECC line 60 from the memory controller 22. And then
`similarly, when asked at deposition what that ECC signal was, he testifies
`that it's the signal that's used to initiate the ECC check.
`The patent owner, on slide 19, again, adds a claim limitation
`that is not there explicitly limiting check signal. And the explicit
`limitation as found in the papers say it cannot initiate the error correction,
`it cannot be a control signal and it must contain check bits or parity bits.
`The primary reliance for patent owner on this point is its expert. So if we
`look to where patent owner's claim is, patent owner's claim slide 20 states
`that -- at the bottom of this first paragraph block that the check signal
`must contain substantive information used in the process of checking data
`for errors and same check signal.
`And purportedly, the patent owner's expert states the broadest
`reasonable interpretation of the phrase "check signal" in light of the '978
`patent specification is a signal that contains check bits or parity bits. So
`at a deposition I wanted to ask about this. So I said -- this is
`Exhibit 1020, the deposition of Bernstein, and this is page 76. I said, Do
`you have an opinion of what the broadest reasonable interpretation of
`check signal is?
`And Dr. Bernstein testified, “[o]n a specific term, as I said, I
`can't give you -- I haven't made that opinion. I was not given whatever
`information I would need, certainly not a proper legal opinion. And it
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 11
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`was not part of what I -- what opinions I formed. And I'm not going to be
`forming new opinions now as we sit here today because that's not what
`I'm here to do.”
`So the patent owner's expert, when asked about this, disclaims
`his testimony. The point we would make here is that how can one credit
`his opinions that Raynham does or does not disclose a check signal when
`he himself says that he doesn't have sufficient information to know what
`that is.
`
`In contrast, petitioner's expert, Dr. Subramanian, as I showed on
`this last slide, does have an opinion on page 18 as to what the check
`signal is.
`All right. So now I would like to go to slide 21 and address
`Humphrey.
`JUDGE PARVIS: In the patent owner response, the patent
`owner sets forth various contentions relating to the indication of the
`signal. And one of them claims to be the issue that you just raised about
`the timing. So the arguments are set forth in the patent owner response.
`Do you agree?
`MR. SHNEIDMAN: With respect to the timing?
`JUDGE PARVIS: In other words, the various -- the
`contentions that patent owner has raised with respect to the indication
`signal unit and it checking bits that have already been stored, those are
`set forth in the patent owner response and this temporal limitation, so to
`speak, that construction issue is set forth in the patent owner response.
`Does the petitioner agree?
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 12
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`MR. SHNEIDMAN: I believe so, but let me just answer this
`way. I believe that there is an explicit limitation. And I can point you to
`two parts of the patent owner response that I'm thinking of. Give me just
`a moment. I'm thinking of paper 17 at 44 where it states, Raynham does
`not meet this limitation as it is directed towards checking data that is
`already stored in the memory chip, and at 45 saying Raynham does not
`meet this limitation because it checks for errors. Not when the data was
`received. So, yes, I think I agree with you and I do not believe -- our
`position is it's not in the claim language.
`So slide 21, this is our secondary argument because it doesn't
`cover all of the claims. Humphrey also renders all relevant instituted
`claims obvious. The patent owner does not appear to dispute that
`Humphrey discloses every element of the claims except for two, which
`I'll talk about. The patent owner doesn't address any of the Cromer
`admitted bases. So unless the Board has questions about claim 9, we
`would ask the Board to reach the same finding it did on institution for the
`reasons advanced in our petition.
`Moving forward to slide 22, on the left you have Humphrey
`with its memory modules 21 which perform the on-memory chip error
`detection. On the right you have the admitted prior art which has the
`error detection on the next chip over.
`On slide 23 we point out there is ample reason to combine
`Humphrey and the admitted prior art. In fact, very relevant to this
`proceeding Humphrey states that satisfactory address error detection with
`a reasonable integrated circuit package count has been a problem in the
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 13
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`prior art. So the idea is we need to get everything onto a chip. And we
`point out that this knowledge would have been known to a POSITA, a
`person of ordinary skill in the art, at the time of the '978 through these
`additional references.
`So once again, we have claim 1 on slide 24. I have bolded the
`elements that are at issue between the parties here. With the
`Raynham-based references, there was no challenge as to the circuit unit
`comprising indication signal generating unit. That I would like to
`address first here with respect to Humphrey.
`So moving to slide 25, in petitioner's view, the patent owner has
`taken a narrow view of Humphrey's memory module to argue that
`Humphrey does not render the element obvious. And what the patent
`owner has done is focused really on Humphrey as it would have been
`understood at the time of Humphrey, which is not the correct test before
`the Board. The Board should be focused on what would a person of
`ordinary skill in the art have understood about the teachings at the time of
`the '978, which is 20 years later.
`One of the primary tacks that the patent owner puts forward is
`on 26, which is that a memory module is required to be multiple chips in
`Humphrey. And that's contrary to what petitioner's expert,
`Dr. Subramanian, testified to. When pressed at deposition, the expert for
`the petitioner pointed out that it's not constrained in Humphrey.
`Humphrey doesn't say this memory module block 21 must be
`implemented with one chip or must be implemented with multiple chips.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`
`
` 14
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`JUDGE PARVIS: Does Humphrey describe the operation of
`Figure 1 and the structure of Figure 1 with respect to a memory board?
`So memory module 21, for example, would be a board, and there would
`be multiple boards in the memory subsystem of Figure 1.
`MR. SHNEIDMAN: There is language about PC board that I'm
`aware of in Humphrey. The patent owner's expert agrees that a memory
`module can consist of one chip and points to the Microsoft Dictionary
`reference which says that it can consist of one chip. Under that reading,
`it would still render obvious the '978 claims.
`JUDGE PARVIS: Does Humphrey describe memory module
`21 as a chip, a single chip?
`MR. SHNEIDMAN: No, it doesn't constrain it either way, as is
`my recollection.
`JUDGE PARVIS: The patent owner argues that the data
`storage would require multiple chips; is that correct?
`MR. SHNEIDMAN: No, it's not. And one comment is that the
`patent owner acknowledges at the time of the '978 there were chips
`much, much larger than what they are assuming is used in Humphrey that
`were available. And in fact, you would not have implemented Humphrey
`with multiple chips. You would have increased your cost and increased
`the complexity for no payoff. So the answer is, we believe, no. Again,
`the focus and what I would ask is when the Board considers this, the
`question is, of course, what the person of ordinary skill at the time of the
`'978 would have understood. And they are focused entirely on the time
`of Humphrey.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 15
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`So moving to slide 27, the primary reliance of the patent owner
`of this notion of memory module having to be multiple chips comes from
`relying on this expert. I impeached the expert with the IEEE dictionary
`at his deposition which says, Located in the memory module, the
`physical component used in the implementation of a memory. There's
`nothing in there that says it has to be multiple things, multiple chips.
`And as Dr. Subramanian, petitioner's expert, argued, you really
`have to look at the context. And the context of Humphrey and what
`someone would have understood at the time of the '978, they would have
`understood that would be a single chip or certainly would suggest that.
`So in slide 28, I have already made this point about the focus on
`Humphrey. At the time of Humphrey is not the proper focus. They do
`put forward a series of arguments that are claiming that you would have
`to implement Humphrey in the series of chips. And that's not correct. To
`pick one, this first bullet, the patent owner, relying on its expert, claims
`the technology at the time of Humphrey prevented the logic required for
`the operation state machine 61 to be manufactured on a DRAM chip.
`And if you look at his -- the expert's testimony on this, he's arguing that
`CMOS was needed and that CMOS was not compatible with DRAM.
`I impeached him on this point in his deposition showing him
`articles from IEEE journals that even predated Humphrey that showed
`CMOS and DRAM coexisting and being on the same chip. And the
`expert's response was to say that a person of ordinary skill in the art
`wouldn't have considered such articles, which is wrong as a matter of
`law.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 16
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`So that is most of the argument as to -- with respect to our
`position with respect to Humphrey. There is this additional argument
`they make similar to Raynham, slide 29, where they argue that there's no
`combination of signals received. And on slide 30, what we lay out in the
`petition is, yes, indeed there are signals that are received in the plurality
`of the sub-bus that are the control bus and the address bus signals and
`that the indication --
`JUDGE PARVIS: You have got two or three minutes left.
`MR. SHNEIDMAN: And the indication signal is put out in 53.
`Let me briefly address, to reserve my time, on slide 31 and 32
`here, I don't want belabor this. It's in our briefing. I'll just point out that
`the expert testified, when asked about the various things he considered
`and what a person of ordinary skill in the art would have known, he says,
`I don't think I opined on that -- pardon me. Let me read exactly: I don't
`think I opined on what any POSITA that I put in this hypothetical
`situation, what art he actually read, what art he actually knows. Further, I
`have heard some conflicting -- maybe it's not clear what I don't really
`understand. So I'm not going to commit myself to what I considered him
`having to know -- having to have known.
`Yet he opines about what a POSITA would or would not have
`understood. So we do not think it would be a valid basis to rely on his
`opinions.
`Unless the panel has questions, I'll reserve the remaining time.
`Thank you very much.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`
`
` 17
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`MR. LOWENSTEIN: Good afternoon, Your Honors. So I
`thought there were a number of things that were interesting about the
`presentation you just heard. One observation was there was very little
`discussion of the arguments that were presented in the petition. The
`second thing I noticed was even now it seems that petitioner's counsel
`seems to fundamentally misapprehend some of the key aspects of our
`argument particularly as to Raynham. And the last thing I'll note, if you
`just heard that presentation and if you just read the reply brief, you would
`think that Humphrey -- I'm sorry, that Raynham was their lead reference.
`In fact, Humphrey was their lead reference in the petition. It was
`presumably the reference they thought was strongest at the time. And I'm
`going to get to you why they switched horses, why they put Humphrey
`second, it's something of an afterthought and why Raynham was their
`second reference to begin with.
`But before I get into that, I want to address a point that Judge
`Parvis raised which I thought was a very good question. And it's about
`the fundamental irreconcilable claim constructions with respect to what
`an indication signal generating unit is and whether it's a
`means-plus-function limitation. To the District Court the petitioner is
`alleging that's a means-plus-function limitation. Here they don't disclose
`that. They don't mention it. If we had not brought it to your attention,
`you would not know it. But here they just say, unhelpfully, the broadest
`reasonable construction is applied to all terms herein. But they make
`sure to say petitioner expressly reserves the right to advance different
`constructions in this court.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 18
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`
`Now, let's look at this actual construction. In the institution
`decision --
`JUDGE PARVIS: Quick question, is the District Court
`proceeding stayed?
`MR. LOWENSTEIN: Yes.
`JUDGE PARVIS: Has patent owner advanced a construction
`that this limitation, the indication signal unit is a means-plus-function --
`MR. LOWENSTEIN: No, we have always been consistent.
`We don't believe that it is, but I don't think that legally matters from the
`perspective of what the petitioner is arguing. In the institution decision,
`we are faulted for not presenting evidence that they argued this is a
`means-plus-function limitation. This is that evidence. They say the
`structure for an indication signal generating unit is a plurality XOR gates
`with a number of XOR gates being equal to the number of lines on the
`sub-bus being combined. They have no explanation as to why that's not
`the construction here. They have no explanation as to how that
`construction is met by the references.
`Now, sometimes you read petitions and you think that the
`petitioner believes you can change a construction by magically saying the
`BRI and that will cause a claim to transform. But that does not work as a
`matter of law with respect to means-plus-function limitations where the
`case law is overwhelmingly clear, as we point out in our briefing and I
`heard no response whatsoever to in the present as heard. In In re
`Donaldson there's no difference as to whether a limitation is subject to
`means-plus-function treatment in the Board and in the District Court. So
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`
`
` 19
`
`
`
`Case IPR2017-00114 (Patent 7,206,978 B2)
`Case IPR2017-00116 (Patent 7,334,150 B2)
`
`just to quote from In re Donaldson on slide 5, We hold that Section 112,
`paragraph 6, applies regardless of the context in which the interpretation
`of means-plus-function language arises.
`JUDGE PARVIS: The actual recitation is indication signal
`generating unit; is that correct?
`MR. LOWENSTEIN: Correct.
`JUDGE PARVIS: Is means used in any of the claims, the word
`"means"?
`MR. LOWENSTEIN: There were in some of the noninstituted
`claims. I will allow that the legal presumption does not arise, but I still
`think it's fundamentally important that a petitioner should have consistent
`positions. And if there's an inconsistency, at the very least, to try to
`reconcile those positions. Otherwise there's a regime in which a
`petitioner can take whatever position they find most advantageous in the
`District Court and whatever position they find most advantageous before
`Your Honors and never have to live with the consequences in either
`proceeding. And that's particularly hard to swallow here where
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
