Paper No. 33
`Trials@uspto.gov
`571-272-7822 Entered: March 29, 2018
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2017-00114
`Patent 7,206,978 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`PARVIS, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`I. INTRODUCTION
`Kingston Technology Company, Inc. (“Petitioner”) filed a Petition for
`inter partes review of claims 1–6 and 8–14 of U.S. Patent No. 7,206,978 B2
`(Ex. 1001, “the ’978 patent”). Paper 2 (“Pet.”). In support of its Petition,
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`Petitioner proffers a Declaration of Dr. Vivek Subramanian. Ex. 1003.
`Polaris Innovations Ltd. (“Patent Owner”) filed a Preliminary Response.
`Paper 6 (“Prelim. Resp.”). Upon consideration of the parties’ contentions
`and supporting evidence, we instituted an inter partes review pursuant to 35
`U.S.C. § 314, as to claims 1, 6, 8–11, 13, and 14 of the ’978 Patent. Paper
`10 (“Dec.”).
`Subsequent to institution, Patent Owner filed a Patent Owner
`Response (Paper 17, “PO Resp.”). In support of its Patent Owner Response,
`Patent Owner proffers the Declaration of Dr. Joseph Bernstein. Ex. 2004.
`Petitioner filed a Reply to Patent Owner’s Response (Paper 21, “Pet.
`Reply”). On December 6, 2017, we held an oral hearing. Paper 32 (“Tr.”).
`This Final Written Decision is entered pursuant to 35 U.S.C. § 318(a).
`For the reasons that follow, we determine that Petitioner has demonstrated
`by a preponderance of the evidence that claims 1, 6, 8–11, 13, and 14 of the
`’978 Patent are unpatentable.
`
`A. Related Matters
`The parties state that the ’978 Patent is the subject of a pending
`lawsuit in the Central District of California, i.e., Polaris Innovations Ltd. v.
`Kingston Tech. Co., Case No. 8:16–cv-300 (C.D. Cal.)1 and the lawsuit
`includes assertions against Petitioner. Pet. 1; Paper 3 (Patent Owner’s
`Mandatory Notices), 1.
`
`
`1 This lawsuit is referred to herein as the “companion district court lawsuit.”
`2
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`B. The ’978 Patent
`The ʼ978 Patent is directed to error detection in a circuit module. Ex.
`1001, 1:7–8. Figure 3 of the ’978 Patent is reproduced below.
`
`
`
`
`Figure 3 illustrates a schematic view of a memory module.
`As shown in Figure 3 above, each of dynamic random access memory
`(DRAM) chips 302 on module board 300 is connected to one of sub-buses
`310. Id. at 4:43–49. An indication signal generating unit 314 is embedded
`in each memory chip 302. Id. at 4:51–52. Clock, address, check, and error
`signals are received from the motherboard by terminals 320–324 in
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`Patent 7,206,978 B2
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`connector portion 306 (id. at 4:53–60), which is connected to buffer 304 via
`module main bus 308 (id. at 4:45–46).
`Indication signal generating unit 314 includes two exclusive OR
`(XOR) gates 341 and 342. Id. at 5:16–17. Indication signal generating unit
`314 receives command and address bits and the check signal. Id. at 5:18–26.
`Indication signal generating unit 314 outputs indication signal 346. Id. at
`5:26–33.
`
`C. Illustrative Claim
`We instituted an inter partes review as to claims 1, 6, 8–11, 13, and
`14 of the ’978 Patent. Dec. 33. Claims 1 and 13 are independent claims.
`Claims 6, 8–11, and 14 depend, directly or indirectly, from claims 1 or 13.
`Independent claim 1, reproduced below, is illustrative of the claimed subject
`matter:
`1. A circuit module comprising:
`a module board;
`a plurality of circuit units arranged on the module board, each
`circuit unit consisting of a single integrated circuit memory
`chip;
`a main bus having a plurality of lines, branching into a plurality
`of sub-buses having a plurality of lines, each of the sub-busses
`being connected to one of the plurality of circuit units;
`wherein each circuit unit comprises an indication signal
`generating unit for providing an indication signal based on a
`combination of the signals received on the plurality of lines
`of the sub-bus connected to the respective circuit unit, and an
`indication signal output for outputting the indication signal.
`Ex. 1001, 7:30–44.
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`D. Instituted Grounds of Unpatentability
`We instituted inter partes review as to claims 1, 6, 8–11, 13, and 14 of
`the ’978 Patent based on the following grounds (Pet. 10–12):
`Reference(s)
`Basis
`Challenged Claim(s)
`Raynham2 and Seyyedy3
`§ 103(a) 1, 10, 11, 13, and 14
`Raynham, Seyyedy, and Humphrey4 § 103(a) 6
`Raynham, Seyyedy, and Admitted
`§ 103(a) 8
`Prior Art5
`Raynham, Seyyedy, and Cromer6
`§ 103(a) 9
`Humphrey alone or in combination
`§ 103(a) 1, 6, 8, 10, 11, and 13
`with Admitted Prior Art
`Humphrey, Admitted Prior Art, and
`Cromer
`
`§ 103(a) 9
`
`II. DISCUSSION
`
`A. Overview
`A patent claim is unpatentable if the differences between the claimed
`subject matter and the prior art are such that the subject matter, as a whole,
`would have been obvious at the time the invention was made to a person
`having ordinary skill in the art to which said subject matter pertains.
`35 U.S.C. § 103(a). The question of obviousness is resolved on the basis of
`
`
`2 U.S. Patent No. 5,127,014, issued June 30, 1992 (Ex. 1005) (“Raynham”).
`3 U.S. Patent No. 6,282,689 B1, issued Aug. 28, 2001 (Ex. 1009)
`(“Seyyedy”).
`4 European Patent Application 0 084 460 A2, published July 27, 1983 (Ex.
`1008) (“Humphrey”).
`5 Admitted Prior Art (i.e., Ex. 1001, 1:11–38, 1:41–43, 1:57–59, Figs. 1, 2
`(cited in Pet. 15–18, 22, 23)).
`6 European Patent Application EP 1 029 326 B1, published Aug. 23, 2000
`(Ex. 1007) (“Cromer”).
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`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of skill in the art; and (4) when in evidence, objective
`evidence of nonobviousness, i.e., secondary considerations. See Graham v.
`John Deere Co., 383 U.S. 1, 17–18 (1966). In that regard, an obviousness
`analysis “need not seek out precise teachings directed to the specific subject
`matter of the challenged claim, for a court can take account of the inferences
`and creative steps that a person of ordinary skill in the art would employ.”
`See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
`
`B. Person of Ordinary Skill in the Art
`Relying on the testimony of Dr. Subramanian, Petitioner proposes that
`a person of ordinary skill in the art would have had a Master’s degree in
`Electrical Engineering and at least 2 years’ experience working in the field
`of semiconductor memory design. Ex. 1003 ¶¶ 17–19 (cited e.g., in Pet. 20,
`22). Dr. Subramanian further testifies that such a skilled artisan would have
`had understood that “memory and support circuitry could be
`fabricated/packaged on a single chip and multiple chips can be assembled
`onto one or multiple circuit boards” and that such matters were simply
`design choices, as demonstrated by “AAPA of the ’978 patent as well as
`sections of the prior art described below.” Id. ¶ 19.
`Patent Owner disputes Petitioner’s proposal and, relying on the
`testimony of Dr. Bernstein, proposes that a person of ordinary skill in the art
`would have had a bachelor’s degree in Electrical Engineering or the
`equivalent. Ex. 2004 ¶¶ 27–33 (cited in PO Resp. 7). Dr. Bernstein testifies
`that his opinion is based on “his experience” that “people working in the
`semiconductor memory design industry were more likely to have bachelor’s
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`degrees than to have master’s or higher degrees.” Id. ¶ 29. Dr. Bernstein
`testifies that fabricating and packaging “integrated circuits is a complex
`technology” and the person of ordinary skill “would not have had experience
`designing chips at all, except at most, the design of small standard memory
`chips.” Id. at ¶ 32. Based on this testimony, Patent Owner contends “the
`entirety of the Petition and its supporting expert declaration are premised on
`an incorrect and artificially increased level of ordinary skill in the art and,
`should, therefore, be given little weight.” PO Resp. 7 (citing Ex.
`2004 ¶¶ 27–33).
`In its Reply, Petitioner contends that Dr. Bernstein’s testimony is
`entitled to no weight because Dr. Bernstein’s testimony reflects
`inconsistencies regarding his understanding of the level of skill. Pet. Reply
`8 (citing e.g., Ex. 1020, 102:21–106:17, 121:5–14, 154:25–155:12, 217:10–
`13). In particular, Petitioner points to (id.) Dr. Bernstein’s deposition
`testimony that a person having ordinary skill in the art would have had “a
`bachelor’s with two years or three years or so of industrial experience.” Ex.
`1020, 217:10–13; see also id. at 103 (testifying that the skilled artisan had a
`“bachelor and two years” experience), 105 (testifying that the skilled artisan
`had a “bachelor’s degree” and “two or three years of industrial
`experience”). Petitioner also contends that Dr. Bernstein’s testimony is
`“artificially limited” to certain prior art and not consistent with the legal
`principles regarding the hypothetical skilled artisan and available prior art
`references. Pet. Reply 8–9 (citing e.g., Ex. 1020, 219:6–220:9, 238:6–
`239:21).
`Petitioner’s proposed skill level that a person of ordinary skill in the
`art would have had a Master’s degree in Electrical Engineering and at least 2
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`years’ experience working in the field of semiconductor memory design (Ex.
`1003 ¶ 17) is consistent with the level of skill implied by the disclosures of
`the prior art references, with the caveat that such a skilled artisan could also
`have had the equivalent of such experience. See Okajima v. Bourdeau, 261
`F.3d 1350, 1355 (Fed. Cir. 2001) (the prior art itself can reflect the
`appropriate level of skill in the art). Moreover, Dr. Bernstein’s testimony
`that a person having ordinary skill in the art would have had “a bachelor’s
`with two years or three years or so of industrial experience” (see, e.g., Ex.
`1020, 217:10–13) is consistent with Petitioner’s proposed skill level, as
`acknowledged by Petitioner (Pet. Reply 8 n. 7). Neither party has explained,
`nor do we find, a reason in the record why additional industrial experience
`would not have been equivalent to a Master’s degree. Patent Owner’s
`contention, based on Dr. Bernstein’s testimony, that a skilled artisan could
`have had a bachelor’s degree with no work experience, or the equivalent
`(Ex. 2004 ¶ 29) reflects a skill level that is too low in view of the prior art of
`record, and is not consistent with the skill level reflected by Dr. Bernstein’s
`other testimony (see, e.g., Ex. 1020, 217:10–13).
`Additionally, this person is of ordinary creativity, not an automaton.
`KSR, 550 U.S. at 421. The “Field of the Invention” relates to error detection
`in a circuit module comprising circuit chips arranged on the module board.
`Ex. 1001, 1:7–10. The prior art of record, including that relied upon by Dr.
`Subramanian in forming his view of the skilled artisan (Ex. 1003 ¶¶ 17–19,
`referring to the “AAPA” and asserted prior art) includes disclosures of error
`detection and correction in computer memory and, in particular, to on-chip
`error detection and correction in dynamic random access memory (DRAM).
`Ex. 1005, 1:6–10. Dr. Bernstein testifies that the skilled artisan would have
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`had a bachelor’s degree with no work experience, or the equivalent (Ex.
`2004 ¶ 29) because the skilled person “would not have had experience
`designing chips at all, except at most, the design of small standard memory
`chips” (id. ¶ 32). Dr. Bernstein’s testimony acknowledges that fabrication of
`integrated circuits is “a complex technology,” as is packaging. Id. Dr.
`Bernstein’s testimony also acknowledges that the skilled artisan would have
`been working in the semiconductor industry. Id. ¶ 29.
`Accordingly, we adopt Petitioner’s proposal that a person of ordinary
`skill in the art would have had a Master’s degree in Electrical Engineering,
`and at least 2 years’ experience working in the field of semiconductor
`memory design (Ex. 1003 ¶ 17), with the caveat that such a skilled artisan
`also could have had the equivalent of such experience in place of the
`Master’s degree. Regarding Patent Owner’s contention that the Petition and
`Dr. Subramanian’s testimony should be given little weight (PO Resp. 7
`(citing Ex. 2004 ¶¶ 27–33)) and Petitioner’s contention that Dr. Bernstein’s
`testimony is entitled to no weight (Pet. Reply 8), we decline to give the
`entirety of the Petition and the testimonial evidence of both parties little to
`no weight. Instead, we give the contentions in the Petition and the parties’
`testimonial evidence more or less persuasive value depending on the degree
`to which the testimony is supported by reasoning, fact, and the evidence of
`record, as well as our findings set forth herein. We address the testimonial
`evidence regarding the understanding and knowledge that a skilled artisan
`would have had regarding designing, fabricating, and packaging integrated
`circuits (Ex. 1003 ¶ 19; Ex. 2004 ¶¶ 27–33) infra in Section II.D. We agree
`with Petitioner’s contentions that the hypothetical skilled artisan has
`available the prior art references (Pet. Reply 9) and we discuss the
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`sufficiency of rationales regarding reasons to combine or modify the prior
`art in the manner proposed by Petitioner infra in Section II.D.
`
`C. Claim Construction
`Claim 1 recites “wherein each circuit unit comprises an indication
`signal generating unit for providing an indication signal based on a
`combination of the signals received on the plurality of lines of the sub-bus
`connected to the respective circuit unit.” Ex. 1001, 7:39–43.7 In the
`Petition, Petitioner contends that “the broadest reasonable construction is
`applied to all terms herein, and further details of how the claims are being
`interpreted are discussed in the relevant sections below.” Pet. 12.
`Patent Owner responds that “[i]n litigation, Petitioner presently
`contends that the ‘indication signal generating unit’ limitation is subject to
`means-plus-function treatment” (PO Resp. 58 (citing Ex. 2006, 2)) and
`“Petitioner has failed to satisfy its burden of construing the claims” in the
`instant proceeding. Id. at 60–61 (citing e.g., 37 C.F.R. § 42.104(b)(3)).
`Patent Owner further responds “Patent Owner, by contrast, has never
`contended that ‘indication signal generating unit’ is subject to means-plus-
`function treatment.” Id. at 58.
`Patent Owner does not provide an explicit construction for this term,
`but Patent Owner does contend that the aforementioned “indication signal
`generating unit” recitation in claims 1 and 13 “[r]eflect[s] one of the ’978
`Patent’s goals of checking for error on the sub-bus received at each memory
`
`7 Claim 13 recites “wherein the memory unit comprises an indication signal
`generating unit for providing an indication signal based on a combination of
`the signals received on the plurality of lines of the memory bus connected to
`the memory unit.” Ex. 1001, 8:42–46.
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`chip.” Id. at 44. Patent Owner, more specifically, points to the ’978 Patent
`Specification’s disclosure that “errors that happen on a command/address
`bus on a memory module become significant for the error rate of the whole
`system,” therefore, “indication signal generating units are embedded within
`each chip of a circuit module.” PO Resp. 43 (citing Ex. 1001, 3:35–40)
`(emphasis omitted). Patent Owner also points to “[t]he indication signal
`generating units comprise check sum calculation means that allow to
`indicate an error on the lines of the sub-bus connected to the respective
`circuit chip.” Id. (emphasis omitted).
`Petitioner counters that “providing an indication signal based on a
`combination of the signals received” recited in claims 1 and 13 is broad
`enough to encompass the received signals providing the indication signal.
`Pet. Reply 2–3. Petitioner additionally contends “Patent Owner tries to
`impose a claim limitation—not found in the ’978 claim language or
`specification—that control signals cannot be part of the ‘combination of
`signals received.’” Id. at 3. Petitioner also contends “Patent Owner reads in
`a non-existent temporal claim limitation.” Id. at 4.
`Patent Owner does not point us to any construction provided in the
`companion district court lawsuit for “indication signal generating unit” or
`any decision in the companion district court lawsuit that this recitation is a
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`means-plus-function limitation. See generally PO Resp.8 In the instant
`proceeding, neither party contends that the independent claims include
`limitations that recite “means” or “means for,” or contends that
`35 U.S.C. § 112, ¶ 6 should apply to “an indication signal generating unit.”
`Pet. 12; PO Resp. 58; Pet. Reply 2–10. Patent Owner cites to a chart of
`litigation claim construction positions that provides only the parties’
`positions in district court, but does not argue or explain why any
`constructions it advanced there should apply in this proceeding. PO Resp.
`58 (citing Ex. 2006, 2). Based on the entire trial record before us, we are not
`persuaded that 35 U.S.C. § 112, ¶ 6 should apply to “indication signal
`generating unit” recited in claims 1 and 13.9
`We now turn to Patent Owner’s contention that the aforementioned
`“indication signal generating unit” recitation in claims 1 and 13 “[r]eflect[s]
`one of the ’978 Patent’s goals of checking for error on the sub-bus received
`
`
`8 Although we are not bound by a construction by the district court, we will
`consider such an order. See Power Integrations, Inc. v. Lee, 797 F.3d 1318,
`1326 (Fed. Cir. 2015) (“The fact that the board is not generally bound by a
`previous judicial interpretation of a disputed claim term does not mean,
`however, that it has no obligation to acknowledge that interpretation or to
`assess whether it is consistent with the broadest reasonable construction of
`the term.”).
`9 Patent Owner contends that “Petitioner’s inconsistent constructions”
`cannot be based on the broadest reasonable interpretation standard versus a
`district court-type approach. PO Resp. 59. Although a claim in an
`unexpired patent that will not expire before a final written decision is issued
`shall be given its broadest reasonable construction in light of the
`specification of the patent in which it appears (see 37 C.F.R. § 42.100), we
`note that our determinations regarding claim construction in the instant
`proceeding are the same under a district court-type claim construction
`approach.
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`at each memory chip.” PO Resp. 44. In the portion of the ’978 Patent
`Specification identified by Patent Owner, the ’978 Patent Specification
`describes “[t]herefore, according to the inventive arrangement, indication
`signal generating units are embedded within each circuit chip of a circuit
`module (a memory module, for example).” Ex. 1001, 3:30–33.
`This portion of the Specification appears to be consistent with the
`recitation “wherein each circuit unit comprises an indication signal” in claim
`1. Ex. 1001, 8:39 (emphasis added). Claim 13 recites “[a] memory unit,
`consisting of a single integrated circuit memory chip” “wherein the memory
`unit comprises an indication signal generating unit.” Ex. 1001, 8:38–43.
`The recitation “based on a combination of the signals received” is in both
`claims 1 and 13, but in claim 1 the signals are received “on the plurality of
`lines of the sub-bus connected to the respective unit,” whereas in claim 13
`the signals are received “on the plurality of lines of the memory bus
`connected to the memory unit.” Id. at 7:39–44, 8:38–47. Claim 1 needs no
`further construction as Patent Owner’s proposal is recited expressly in the
`claim. To the extent that Claim 13 is broader, we decline to read into the
`recitation “based on a combination of the signals received” further
`limitations in addition to what is recited in the claims.
`Patent Owner also points to (PO Resp. 43) subsequent description that
`“[t]he indication signal generating units comprise check sum calculation
`means that allow to indicate an error on the lines of the sub-bus connected to
`the respective circuit chip by way of calculating a check sum of the signals
`of the sub-bus and by providing an indication signal.” Id. at 3:35–40
`(emphasis added). We note that claim 2, recites “means for providing a
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`check signal to each of the circuit unit.” Id. at 7:45–51.10 “The concept of
`claim differentiation ‘normally means that limitations stated in dependent
`claims are not to be read into the independent claim from which they
`depend.’” Nazomi Comms., Inc. v. Arm Holding, PLC, 403 F.3d 1364, 1370
`(Fed. Cir. 2005) (quoting Karlin Tech., Inc. v. Surgical Dynamics, Inc., 177
`F.3d 968, 971–72 (Fed. Cir. 1999)); see also Envtl. Designs, Ltd. v. Union
`Oil Co., 713 F.2d 693, 699 (Fed. Cir. 1983) (explaining it is not proper “to
`read into an independent claim a limitation explicitly set forth in another
`claim.”). To the extent Patent Owner is trying to limit claim 1
`impermissibly in accordance with the “means” recitation in claim 2 so as to
`read into claim 1 a requirement that the error must be of the signals received
`on lines of the sub-bus (Ex. 1001, 3:35–40), we decline to read this
`limitation into independent claims 1 and 13.
`Instead, we agree with Petitioner that “providing an indication signal
`based on a combination of the signals received” recited in claims 1 and 13
`encompasses the received signals causing the providing of the indication
`signal. Pet. Reply 2–3. Patent Owner contends “Petitioner’s own expert,
`Dr. Subramanian testified in deposition that the phrase ‘based on’ in the
`Claims is more than a mere ‘but for’ causation, and requires that the
`‘indication signal’ be ‘directly dependent’ upon, ‘a combination of the
`signals received’ by the memory chip such that ‘the value of the indication
`signal’ is ‘directly dependent on the sub-bus combinations.’” PO Resp. 48
`(citing Ex. 2007, 128:22–129:21, 146:9–16, 147:5–7). Dr. Subramanian,
`
`
`10 In our Institution Decision, we did not institute inter partes review with
`respect to claim 2 because we determined that Petitioner failed to satisfy the
`identification requirement of 37 C.F.R. § 42.104(b)(3). Dec. 32–33.
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`however, testifies that “based on” recited in claim 1 “is a causation” and
`what he means by “direct dependency” is that in “an equation” “the output is
`based on the inputs.” Ex. 2007, 146:9–23 (emphasis added). Patent Owner
`also points to Dr. Subramanian’s testimony that factors (weight of aircraft,
`wind) indirectly impacting the input (where the aircraft is within the past
`hour) are not part of a calculation that uses the actual location of the airplane
`as an input. Id. at 128:22–129:21. Patent Owner has not explained
`sufficiently how this analogy, which is not an embodiment described in the
`’978 Patent, pertains to its claim construction contentions regarding
`independent claims 1 and 13, as understood in light of the Specification of
`the ’978 Patent. Nonetheless, factors indirectly impacting the inputs are not
`the same as the inputs. We are not persuaded that Dr. Subramanian’s
`testimony supports further limiting these claims to include the description in
`the ’978 Patent Specification that Patent Owner identifies, which expressly
`describes details regarding “the check sum calculation means” (Ex. 1001,
`3:35–40).
`Patent Owner further contends that its claim construction contentions
`are supported by the testimony of Dr. Bernstein. PO Resp. 48 (citing Ex.
`2004 ¶¶ 99–102). Dr. Bernstein testifies regarding Dr. Subramanian’s
`testimony and repeats Patent Owner’s contentions above. Ex. 2004 ¶¶ 99–
`101. We do not credit Dr. Bernstein’s testimony in this regard for the
`reasons discussed above. Dr. Bernstein also testifies that in an embodiment
`of the ’978 Patent, the signals are themselves checked for potential errors.
`Id. ¶ 102 (citing Ex. 1001, 5:29–33). The embodiment Dr. Bernstein
`testifies about pertains to calculating a check sum, similar to the description
`in the ’978 Patent Specification that Patent Owner identifies, which
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`expressly describes details regarding the check sum calculation means. Ex.
`1001, 7:45–51 (“means for providing a check signal to each of the circuit
`unit,” and “wherein said indication signal generating unit generates said
`indication signal . . . so that the indication signal represents an error signal.”)
`For the same reasons discussed above, we are not persuaded to limit claims
`1 and 13 to this particular description in the ’978 Patent Specification.
`Additionally, we agree with Petitioner that the “combination of the
`signals received” recited in claims 1 and 13 does not exclude control signals
`and does not include a temporal limitation regarding when the signals are
`received. Pet. Reply 3–4. Regarding the exclusion of control signals, the
`’978 Patent Specification describes that errors “happen on a
`command/address bus” and sets forth “for example” that “a memory
`command/address sub-bus” is connected to a circuit chip. Ex. 1001, 3:27–
`35. Regarding a temporal requirement, neither the claims nor the portions of
`the ’379 Patent Specification identified by Patent Owner indicate any
`temporal requirement. For instance, even regarding the “check sum
`calculation means” the ’379 Patent Specification describes that such means
`“allow to indicate an error on the lines of the sub-bus connected to the
`respective circuit chip,” without describing when signals on those lines are
`received. Id. at 3:36–38.
`Accordingly, regarding “wherein each circuit unit comprises an
`indication signal generating unit for providing an indication signal based on
`a combination of the signals received on the plurality of lines of the sub-bus
`connected to the respective circuit unit” (Ex. 1001, 7:39–43) recited in claim
`1, and the similar limitation recited in claim 13, consistent with the parties’
`contentions in the instant proceeding, we find that neither “means” nor
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`“means for” is recited and we determine that 35 U.S.C. § 112, ¶ 6 should not
`apply. Additionally, we are not persuaded that this recitation should be
`limited to the check sum calculation means embodiment disclosed in the
`’978 Patent Specification (see, e.g., Ex. 1001, 3:35–40) or that “‘but for’
`causation” (PO Resp. 48) is distinguishable from “based on” recited in
`claims 1 and 13. Instead, we agree with Petitioner that “providing an
`indication signal based on a combination of the signals received” recited in
`claims 1 and 13 encompasses the received signals causing the providing of
`the indication signal. Pet. Reply 2–3. We need not make further
`determinations regarding the broadest reasonable interpretation of the
`“wherein” clauses recited in independent claims 1 and 13 to resolve a
`controversy in the instant proceeding and, additionally, because neither party
`provides a proposed claim construction for any terms recited in these
`clauses. See Wellman, Inc. v. Eastman Chem. Co., 642 F.3d 1355, 1361
`(Fed. Cir. 2011) (“[C]laim terms need only be construed ‘to the extent
`necessary to resolve the controversy’”) (quoting Vivid Techs., Inc. v. Am.
`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)); see also Nidec
`Motor Corp. v. Zhongshan Broad Ocean Motor Co. Ltd., Matal, 868 F.3d
`1013, 1017 (Fed. Cir. 2017) (citing Vivid Techs. in the context of an inter
`partes review).
`
`D. Obviousness of Claims 1, 6, 8–11, 13, and 14 over Raynham with
`other art
`Petitioner contends claims 1, 10, 11, 13, and 14 are unpatentable
`under 35 U.S.C. § 103(a) as obvious over Raynham and Seyyedy. Pet. 39–
`58. Petitioner also contends that claims 6, 8, and 9 are unpatentable under
`35 U.S.C. § 103(a) as obvious over Raynham, Seyyedy, and other art,
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`IPR2017-00114
`Patent 7,206,978 B2
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`specifically, Humphrey (as to claim 6), Admitted Prior Art (as to claim 8), or
`Cromer (as to claim 9). Id. at 58–62. We instituted on each of these claims
`based on the aforementioned grounds. Dec. 33.
`
`1. Overview of Raynham
`Raynham is directed to providing error detection and correction on the
`same chip as DRAM memory. Ex. 1005, Abstract. Figure 3 of Raynham is
`reproduced below.
`
`
`
`Figure 3 illustrates a block diagram showing memory
`subsystem components.
`Figure 3 depicts memory subsystem 48 having memory controller 22
`and bus transceiver 26. Id. at 5:4–6. Memory subsystem 48 also includes a
`DRAM memory array that outputs a hard error signal over signal line 42 to
`system bus 12. Id. at 5:12–13. Data line 34 carries data between the DRAM
`memory array and bus transceiver 26. Id. at 5:13–15. The Error Correction
`Code (ECC) checking and generating circuit is formed on the same chips as
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`the DRAM memory array. Id. at 5:7–9. A DRAM chip usable in the
`DRAM memory array is illustrated in Figure 4 of Raynham (id. at 5:16–17),
`which is reproduced below.
`
`
`
`Figure 4 is a block diagram of a DRAM.
`DRAM chip 52 receives control signals and address signals on lines
`54, 56, and 58, and error correction code signals on line 60. Id. at 5:16–21.
`These signals are used during the operation of ECC circuitry 92. Id. at 6:58–
`60.
`
`2. Overview of Seyyedy
`Seyyedy is directed to a memory module, such as a DIMM or a single
`inline memory module (SIMM), which incorporates error correction
`circuitry. Ex. 1009, Abstract. Figure 2 of Seyyedy is reproduced below.
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`Figure 2 is a block diagram of a conventional SIMM.
`As shown above in Figure 2, the SIMM includes DRAMs 100–100'''
`mounted on circuit board 200. Id. at 4:27–28. DRAMs 100–100''' are
`integrated circuit chips that are mounted directly on circuit board 200 and
`environmentally encapsulated. Id. at 4:40–43.
`
`3. Overview of Humphrey
`Humphrey is directed to detecting errors in a computer memory
`system. Ex. 1008, Abstract. Figure 1 of Humphrey is reproduced below.
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`
`
`Figure 1 is block diagram of a memory system.
` As shown in Figure 1 above, memory system 11 includes a processor
`subsystem and a memory subsystem. Id. at 7:23–33. The processor
`subsystem includes map/memory control 13 (id. at 7:23–25), which is
`connected by bus 27 to central processing unit (CPU) 23 (id. at 7:34–35) and
`by bus 29 to I/O channel 25 (id. at 8:1–4). The memory subsystem includes
`memory modules 21. Id. at 7:29–31. Each memory module 21 has five bus
`connections, including write and read data buses 45 and 47, address bus 33,
`and control bus 39. Id. at 8:28–9:8.
`
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`Figure 2 is reproduced below.
`
`
`
`Figure 2 is a block diagram of the memory module
`portion of the memory system.
`As illustrated in Figure 2 above, memory module 21 stores data in
`semiconductor storage array 55. Id. at 10:26–30. Memory module 21 also
`checks its operations using operation state machine 61. Id. at 10:33–35.
`
`4. Overview of Admitted Prior Art11
`According to the ’978 Patent, a conventional structure of computer
`main memory systems includes a memory controller, a main memory bus
`and memory chips, such as DRAM chips, that are arranged on memory
`
`
`11 This overview is of portions of the Background of the Invention of the
`’978