Trials@uspto.gov
`571-272-7822
`
`
`Paper No. 38
`Entered: May 18, 2018
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NETAPP, INC.,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES II, LLC,
`Patent Owner.
`____________
`
`Case IPR2017-00276
`Patent 6,633,945 B1
`____________
`
`
`Before JEFFREY S. SMITH, JENNIFER S. BISK, and
`BEVERLY M. BUNTING, Administrative Patent Judges.
`
`SMITH, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`
`571-272-7822
`
`
`Paper No. 38
`Entered: May 18, 2018
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NETAPP, INC.,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES II, LLC,
`Patent Owner.
`____________
`
`Case IPR2017-00276
`Patent 6,633,945 B1
`____________
`
`
`Before JEFFREY S. SMITH, JENNIFER S. BISK, and
`BEVERLY M. BUNTING, Administrative Patent Judges.
`
`SMITH, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
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`IPR2017-00276
`Patent 6,633,945 B1
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`I. INTRODUCTION
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision issues pursuant to 35 U.S.C. § 318(a). For the reasons that follow,
`we determine Petitioner has shown by a preponderance of the evidence that
`claims 1 and 6 (all the challenged claims) of U.S. Patent No. 6,633,945 B1
`(Ex. 1001, “the ’945 patent”) are unpatentable.
`A. Procedural History
`Petitioner filed a Petition1 for inter partes review of claims 1 and 6. Paper
`13 (“Pet.”). Patent Owner filed a Preliminary Response. Paper 8 (“Prelim.
`Resp.”). Pursuant to 37 C.F.R. §§ 42.4(a) and 42.108 and 35 U.S.C.
`§ 314(a), the Board instituted an inter partes review of: claims 1 and 6 as
`unpatentable under 35 U.S.C. § 103 over Ekanadham2 and Hagersten3;
`claims 1 and 6 unpatentable under 35 U.S.C. § 103 over Sharma4 and
`Hagersten; and claims 1 and 6 as unpatentable under 35 U.S.C. § 103 over
`Sharma. See Paper 14, 24 (“Dec. on Inst.”).
`After institution of trial, Patent Owner filed a Patent Owner Response
`(Paper 19, “PO Resp.”), to which Petitioner filed a Reply (Paper 23,
`“Reply”).5
`
`
`1 Petitioner filed an Original Petition on Nov. 18, 2016 (Paper 1), and a
`Corrected Petition on May 8, 2017 (Paper 13). In this Decision we cite to
`the Corrected Petition.
`2 US 6,085,295, issued Jul. 4, 2000, filed Oct. 24, 1997 (Ex. 1003).
`3 US 5,754,877, issued May 19, 1998, filed Jul. 2, 1996 (Ex. 1004).
`4 US 6,055,605, issued Apr. 25, 2000, filed Oct. 24, 1997 (Ex. 1002).
`5 Petitioner filed evidentiary objections to Patent Owner’s Response (Paper
`20) and Patent Owner filed evidentiary objections to Petitioner’s Reply
`(Paper 24). Neither party filed a motion to exclude, which is required to
`preserve any evidentiary objection. See 37 C.F.R. § 42.64(c).
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`An oral argument was held on March 1, 2018. A transcript of the oral
`argument is included in the record. Paper 32 (“Tr.”).
`On May 10, 2018, we supplemented our Decision on Institution to
`include in the trial the ground that claims 1 and 6 are unpatentable under 35
`U.S.C. § 103 over Ekanadham alone, so as to institute trial on all Challenged
`Claims and all grounds. See Paper 37; see also SAS Inst., Inc. v. Iancu, 2018
`WL 1914661, at *10 (U.S. Apr. 24, 2018) (“Because everything in the
`statute before us confirms that SAS is entitled to a final written decision
`addressing all of the claims it has challenged and nothing suggests we lack
`the power to say so, the judgment of the Federal Circuit is reversed and the
`case is remanded for further proceedings consistent with this opinion.”).
`During a conference call on May 9, 2018, to discuss the impact of the SAS
`Inst., Inc. decision on this proceeding, the parties were unsure whether they
`believed the ground based on Ekanadham alone would require additional
`consideration. As we indicated in our supplement to the Decision to
`Institute, if either Patent Owner or Petitioner believes that the ground based
`on Ekanadham alone requires additional consideration in this proceeding,
`the parties may file a rehearing request pursuant to 37 C.F.R. § 42.71(d).
`Paper 37.
`
`B. Related Matters
`Both parties identify that the ’945 patent was asserted against NetApp
`Inc. in Intellectual Ventures I, LLC v. NetApp Inc., Case No. 1:16-cv-10868-
`IT (D. Mass.), filed May 11, 2016. Pet. 17; Paper 4, 1.
`C. The ’945 Patent
`The ’945 patent relates generally to a fully connected multiple flow
`control unit (FCU) based architecture to reduce memory read latencies. Ex.
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`1001, 1:66–2:1. A symmetric multiprocessor system includes a switch
`matrix for data transfers that provides multiple concurrent buses that enable
`increased bandwidth between processors and shared memory. Ex. 1001,
`Abstract. A high-speed point-to-point channel couples command initiators
`and memory with the switch matrix and with input/output (I/O) subsystems.
`Id. Figure 2 of the ’945 patent is reproduced below.
`
`Figure 2, above, shows a symmetric shared-memory multiprocessor
`system using a switched-fabric data path architecture centered on FCU 220.
`Ex. 1001, 2:59–62. Point-to-point (PP) interconnections 112, 113, and 114
`provide channel interfaces between FCU 220 and dual CPU interface units
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`(DCIUs) 210, memory control units (MCUs) 230, and bus bridge units
`(BBUs) 240, respectively. Id. at 2:67–3:8, 3:11–15.
`Figure 12 of the ’945 patent is reproduced below.
`
`
`
`Figure 12, above, shows fully connected multiple FCU architectures.
`Id. at 6:22–23, 6:62–7:57. The interconnections between FCUs are
`point-to-point. Id. at 7:14–15. Each FCU has a direct connection to all other
`FCUs and maintains cache coherency for transactions that belong to its
`memory region via the point-to-point interconnections. Id. at 7:15–21.
`D. Illustrative Claim
`Challenged claims 1 and 6 of the ’945 patent are independent. Claim
`1 is illustrative of the claimed subject matter:
`1. A multi-processor shared memory system comprising:
`a first set of point-to-point connections;
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`a first set of processors each coupled to one of the first set
`of point-to-point connections;
`a first memory coupled to one of the first set of point-to-
`point connections;
`a first flow control unit including a first data switch
`coupled to the first set of point-to-point connections wherein the
`first data switch is configured to interconnect the first set of
`point-to-point connections to provide first data paths between the
`first memory and the first set of processors;
`a second set of point-to-point connections;
`a second set of processors each coupled to one of the
`second set of point-to-point connections;
`a second memory coupled to one of the second set of
`point-to-point connections;
`a second flow control unit including a second data switch
`coupled to the second set of point-to-point connections wherein
`the second data switch is configured to interconnect the second
`set of point-to-point connections to provide second data paths
`between the second memory and the second set of processors;
`and
`
`a third point-to-point connection coupled to the first data
`switch and to the second data switch wherein the first data switch
`is configured to interconnect the first set of point-to-point
`connections to the third point-to-point connection and the second
`data switch is configured to interconnect the second set of point-
`to-point connections to the third point-to-point connection to
`provide third data paths between the second memory and the first
`set of processors and between the first memory and the second
`set of processors.
`Ex. 1001, 9:2–36.
`E. Instituted Grounds of Unpatentability
`Petitioner contends that claims 1 and 6 of the ’945 patent are
`
`unpatentable based on the following specific grounds. Pet. 25.
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`References
`Ekanadham and Hagersten
`Ekanadham
`Sharma and Hagersten
`Sharma
`
`
`Basis
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`
`Challenged Claims
`1 and 6
`1 and 6
`1 and 6
`1 and 6
`
`II. ANALYSIS
`A. Legal Principles
`In inter partes reviews, petitioner bears the burden of proving
`unpatentability of the challenged claims, and the burden of persuasion never
`shifts to the patent owner. Dynamic Drinkware, LLC v. Nat’l Graphics, Inc.,
`800 F.3d 1375, 1378 (Fed. Cir. 2015). To prevail in this proceeding,
`Petitioner must support its challenge by a preponderance of the evidence. 35
`U.S.C. § 316(e); 37 C.F.R. § 42.1(d). Accordingly, all of our findings and
`conclusions are based on a preponderance of the evidence.
`A claim is unpatentable under § 103(a) if the differences between the
`claimed subject matter and the prior art are such that the subject matter, as a
`whole, would have been obvious at the time the invention was made to a
`person having ordinary skill in the art to which said subject matter pertains.
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of
`obviousness is resolved on the basis of underlying factual determinations,
`including: (1) the scope and content of the prior art; (2) any differences
`between the claimed subject matter and the prior art; (3) the level of skill in
`the art; and (4) where in evidence, so-called secondary considerations.
`Graham v. John Deere Co. of Kansas City, 383 U.S. 1, 17–18 (1966).
`We analyze the following ground based on obviousness in accordance with
`the above-stated principles. Because Patent Owner did not argue or provide
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`evidence of secondary considerations, our analysis focuses on the first three
`factors.
`
`B. Level of Skill in the Art
`The level of skill in the art is “a prism or lens” through which we view
`the prior art and the claimed invention. Okajima v. Bourdeau, 261 F.3d
`1350, 1355 (Fed. Cir. 2001). Petitioner contends that a person of ordinary
`skill in the art would have had at least a bachelor’s degree in computer
`science or electrical engineering and at least four years of experience in the
`field of multiprocessing computer systems. Pet. 19. Patent Owner contends
`that a person of ordinary skill in the art would have had at least a bachelor’s
`degree in computer science or electrical engineering and at least three years
`of experience in the field of multiprocessor systems. PO Resp. 14.
`Factual indicators of the level of ordinary skill in the art include “the
`various prior art approaches employed, the types of problems encountered in
`the art, the rapidity with which innovations are made, the sophistication of
`the technology involved, and the educational background of those actively
`working in the field.” Jacobson Bros., Inc. v. United States, 512 F.2d 1065,
`1071 (Ct. Cl. 1975); see also Orthopedic Equip. Co., Inc. v. United States,
`702 F.2d 1005, 1011 (Fed. Cir. 1983) (quoting with approval Jacobson
`Bros.). We find both parties assert very similar definitions of the level of
`ordinary skill in the art. Both definitions include a degreed engineer with
`three or four years of experience. As such, we see no meaningful difference
`between the level of ordinary skill proposed by Petitioner and the level of
`ordinary skill proposed by Patent Owner.
`We find, based on our review of the complete record, that the
`evidence of record supports a level of ordinary skill in the art consistent with
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`the parties’ definitions— a bachelor’s degree in computer science or
`electrical engineering and at least four years of experience in the field of
`multiprocessing computer systems. Further, our patentability analysis
`presented below would reach the same findings and determinations under
`either party’s definition of the level of ordinary skill in the art.
`C. Claim Construction
`On February 14, 2017, we granted Patent Owner’s Motion for district
`court type claim construction under 37 C.F.R. § 42.100(b). Paper 7. The
`Board interprets claims of an expired patent using the principles set forth in
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). See 37
`C.F.R. § 42.5(b); see also In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir.
`2012) (“While claims are generally given their broadest possible scope
`during prosecution, the Board’s review of the claims of an expired patent is
`similar to that of a district court’s review.”) (internal citation omitted)
`(“Phillips” standard). Under this approach, claim terms are given their
`ordinary and customary meaning, as would be understood by a person of
`ordinary skill in the art, at the time of the invention, in light of the language
`of the claims, the specification, and the prosecution history of record.
`Phillips, 415 F.3d at 1313.
`Petitioner proposes construction of the claim term “point-to-point
`connection” as encompassing a statically configured communications link
`between two devices. Pet. 20–25. Patent Owner contends that the plain and
`ordinary meaning of this claim term is clear, and that construction is not
`necessary to resolve the controversy in this proceeding. PO Resp. 15.
`Moreover, Patent Owner does not propose that any other term requires
`construction. See generally PO Resp. 14–15.
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`Having considered the entire record, our determination regarding the
`obviousness of the challenged claims does not turn on the interpretation of
`any of the terms or limitations. Thus, based on the final trial record, we
`determine no terms need an explicit construction to resolve a controversy in
`this case. See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`(Fed. Cir. 1999) (only those terms which are in controversy need to be
`construed and only to the extent necessary to resolve the controversy).
`
`D. Asserted Obviousness Over Ekanadham alone
`Petitioner, relying on the Declaration of Mr. Ian Jestice (Ex. 1006),
`challenges claims 1 and 6 as obvious over Ekanadham.
`
`1. Ekanadham (Ex. 1003)
`Ekanadham relates to providing cache coherence in a shared memory
`system composed of a network of multiprocessor nodes. Ex. 1003, 1:9–11;
`2:48–50. Figure 3a of Ekanadham is reproduced below.
`
`
`Figure 3a, above, shows two symmetric multiprocessor (SMP) nodes,
`where each node includes a plurality of processors P1 through Pn, a memory
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`module M, and adapter A, interconnected to each other through a switch. Id.
`at 3:37–43. The nodes are connected to each other through a network. Id. at
`3:43–45. All communications between the processors, memories, and
`adapters are made point-to-point without the need for broadcasts within the
`SMP node. Id. at 2:14–16.
`When a cache line needs to be invalidated, an adapter at the local node
`consults its node list for the line to determine which remote nodes to forward
`the invalidations to, and sends a message to all such nodes. Id. at 2:52–57,
`4:52–60, 8:39–43. The adapter at the remote node consults its local
`processor list and issues invalidation commands over the switch to each of
`the processors on the list. Id. at 2:57–61, 4:60–63.
`2. Discussion
`Petitioner contends Ekanadham teaches “a first set of point-to-point
`connections,” as recited in claim 1, in teaching that all communications
`between the processors, the memories, and the adapters are made point-to-
`point without the need for broadcasts within the SMP node. Pet. 35 (citing
`Ex. 1003, Fig. 3a, 2:14–16; Ex. 1006 ¶¶ 57–58). Patent Owner does not
`challenge Petitioner’s contention. We agree with Petitioner and find that
`Ekanadham teaches “a first set of point-to-point connections,” as recited in
`claim 1. See Ex. 1003, Fig. 3a, 2:14–16; Ex. 1006 ¶¶ 57–58.
`Petitioner contends that Ekanadham teaches “a first set of processors
`each coupled to one of the first set of point-to-point connections,” and “a
`first memory coupled to one of the first set of point-to-point connections,” as
`recited in claim 1, in teaching that a plurality of processors and a memory
`are connected to a local data switch via a first set of point-to-point
`connections. Id. at 35–38 (citing Ex. 1003, Fig. 3a; 2:14–16; 3:37–45; Ex.
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`1006 ¶¶ 59–62). Patent Owner does not challenge Petitioner’s contention.
`We agree with Petitioner and find that Ekanadham teaches “a first set of
`processors each coupled to one of the first set of point-to-point connections,”
`and “a first memory coupled to one of the first set of point-to-point
`connections,” as recited in claim 1. See Ex. 1003, Fig. 3a; 2:14–16; 3:37–
`45; Ex. 1006 ¶¶ 59–62.
`Petitioner contends Ekanadham teaches “a first flow control unit
`including a first data switch coupled to the first set of point-to-point
`connections wherein the first data switch is configured to interconnect the
`first set of point-to-point connections to provide first data paths between the
`first memory and the first set of processors,” as recited in claim 1, in
`teaching a switch and adapter coupled to the point-to-point connections to
`the processors and the memory. Pet. 38–40 (citing Ex. 1003, Fig. 3a;
`2:14–16; 3:37–43; Ex. 1006 ¶¶ 63–66). Patent Owner does not challenge
`Petitioner’s contention. We agree with Petitioner and find that Ekanadham
`teaches “a first flow control unit including a first data switch coupled to the
`first set of point-to-point connections wherein the first data switch is
`configured to interconnect the first set of point-to-point connections to
`provide first data paths between the first memory and the first set of
`processors,” as recited in claim 1. See Ex. 1003, Fig. 3a; 2:14–16; 3:37–43;
`Ex. 1006 ¶¶ 63–66.
`Petitioner, relying on testimony of Mr. Jestice, contends Ekanadham
`teaches
`
`a second set of point-to-point connections;
`a second set of processors each coupled to one of the
`second set of point-to-point connections;
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`a second memory coupled to one of the second set of
`point-to-point connections;
`a second flow control unit including a second data switch
`coupled to the second set of point-to-point connections wherein
`the second data switch is configured to interconnect the second
`set of point-to-point connections to provide second data paths
`between the second memory and the second set of processors
`as recited in claim 1 (Ex. 1001, 9:15–26), in teaching a second node that has
`identical components as the first node discussed above. Pet. 40–41 (citing
`Ex. 1006 ¶ 68). Patent Owner does not challenge Petitioner’s contention.
`We agree with Petitioner and credit the testimony of Mr. Jestice in finding
`that Ekanadham teaches these limitations. See Ex. 1006 ¶ 68 (“Each node
`described recites the same structure and function as the other nodes in the
`system of Ekanadham”).
`Further, claim 1 recites:
`a third point-to-point connection coupled to the first data
`switch and to the second data switch wherein the first data switch
`is configured to interconnect the first set of point-to-point
`connections to the third point-to-point connection and the second
`data switch is configured to interconnect the second set of point-
`to-point connections to the third point-to-point connection to
`provide third data paths between the second memory and the first
`set of processors and between the first memory and the second
`set of processors.
`Ex. 1001, 9:27–36 (“the third point-point connection limitation”). Claim 6
`recites a similar limitation. Ex. 1001, 10:14–16. Petitioner argues that
`Ekanadham teaches the third point-to-point connection limitation, because
`each of the plurality of nodes is connected to each other through a network.
`Pet. 41 (citing Ex. 1003, 3:43–44; Ex. 1006 ¶¶ 53). Petitioner annotated
`Figure 3a of Ekanadham to illustrate how this limitation is satisfied.
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`Figure 3a of Ekanadham as illustrated by Petitioner. Id. at 42 (citing Ex.
`1003, Fig. 3a)
`According to Petitioner, all of the connections between adapters
`within the yellow box are point-to-point. Id. at 43 (citing Ex. 1003, 2:14–16;
`Ex. 1006 ¶ 71). Petitioner’s declarant, Mr. Ian Jestice, testifies that
`“Ekanadham teaches that all communications between the adapters are made
`point to point.” Ex. 1006 ¶ 71 (citing Ex. 1003, 2:14–15). Petitioner
`concludes that “a POSA would understand Ekanadham as disclosing that the
`data switches in any two nodes can be coupled through their corresponding
`adapters to the third point to-point connection between nodes, i.e., the
`claimed third point-to-point connection of the ’945 Patent.” Id. at 43 (citing
`Ex. 1006 at ¶¶ 70–73).
`Ekanadham discloses “[a]ll communications between the processors,
`the memories and the adapters are made point to point without the need for
`broadcasts within the SMP node.” Ex. 1003, 2:14–16. We understand this
`passage in Ekanadham as teaching that the point-to-point communications
`are “within the SMP node” (Ex. 1003, 2:16), not between adapters in
`different nodes connected over a network. In light of this, we do not find
`Mr. Jestice’s declaration that “Ekanadham teaches that all communications
`between adapters are made point to point” to be supported by his
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`corresponding citation to Ekanadham. See Ex. 1006 ¶ 71 (citing Ex. 1003,
`2:14 –15). As such, Petitioner does not present sufficient arguments and
`credible evidence to support a finding that Ekanadham teaches that the
`communications between adapters over the network shown in Figure 3a are
`point-to-point.
`For the reasons discussed above, we conclude, based on the complete
`trial record, that the Petition and supporting evidence does not establish that
`Ekanadham renders claims 1 and 6 obvious.
`
`E. Asserted Obviousness Over Ekanadham and Hagersten
`Petitioner, again relying on the Declaration of Mr. Ian Jestice (Ex.
`1006), challenges claims 1 and 6 as obvious over the combination of
`Ekanadham and Hagersten. Pet. 25–49.
`1. Hagersten (Ex. 1004)
`Hagersten is related to the architectural connection of multiple
`processors within a multiprocessor computer system. Ex. 1004, 1:7–9. The
`computer system includes multiple SMP nodes that are connected to each
`other by point-to-point links. Id. at Abstract. Figure 7 of Hagersten is
`reproduced below.
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`Figure 7, above, shows an extended symmetric processor (XMP)
`system 130 with three SMP nodes 120A–C. Id. at 13:41–44. XMP interface
`128A of SMP node 120A is point-to-point connected to XMP interface
`128B of SMP node 120B by point-to-point link 142. Id. at 13:62–64. The
`point-to-point linking structure comprising point-to-point connections 140,
`142, and 144 is a transaction synchronous structure. Id. at 14:49–52. Thus,
`each SMP node 120 may send and receive transactions at approximately the
`same time as each other SMP node 120, without running into latency
`problems or arbitration delay. Id. at 14:2–10, 52–57; 15:4–7.
`2. Claim 1
`Petitioner also argues, as an alternative to Ekanadham alone teaching
`the point-to-point connection between nodes, “[t]o the extent there is any
`ambiguity whether the disclosure in Ekanadham that ‘communications
`between … the adapters are … point to point’ is sufficient to establish the
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`third point-to-point connection of the challenged claims, it would have been
`obvious to modify Ekanadham in view of Hagersten to include a point-to-
`point connection between nodes.” Pet. 43 (citing Ex. 1006 at ¶¶ 142–156).
`Specifically, Petitioner argues that Hagersten teaches SMP nodes
`connected to each other by point-to-point connections, such as SMP node
`120A that is point-to-point connected to SMP node 120B by point-to-point
`link 142. Pet. 43 (citing Ex. 1004, Abstract; Fig. 7; 13:63–64; 14:3–10; Ex.
`1006 ¶ 133). Petitioner further relies on Hagersten to show the benefits of
`using a point-to-point connection to connect SMP nodes, including reduced
`latency, separate data transmissions during the same clock cycle, and no
`arbitration delay. Pet. 43–44 (citing Ex. 1004, 14:3–10, 49–57; 15:4–7).
`We agree with Petitioner and determine Hagersten shows the benefits of
`using a point-to-point connection to connect nodes include reduced latency,
`separate data transmissions during the same clock cycle, and no arbitration
`delay. See Ex. 1004, 14:3–10, 49–57; 15:4–7.
`Petitioner reasons that (1) coupling a third point-to-point connection
`to the data switches of a first node and second node as claimed is not
`functionally different from coupling a point-to-point connection through the
`adapters to the switches (as described in Ekanadham) (Id. at 45 (citing Ex.
`1006 at ¶¶ 154–155)); (2) in both cases the data path from the first node to
`the second node is point-to-point and are coupled to each node’s respective
`switch as required by the claim (Id. (citing Ex. 1006 ¶ 155)); Ekanadham’s
`adapter provides this coupling (Id. (citing Ex. 1006 ¶ 155)); and Hagersten
`demonstrates that internode point-to-point connections were known (Id. at
`46).
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`Petitioner relies on testimony of Mr. Jestice to contend that it would
`have been obvious to modify Ekanadham to include the point-to-point
`connection between nodes as taught by Hagersten for the benefit of reducing
`latency. Pet. 30–34, 43 (citing Ex. 1006 ¶¶ 136–1576). Mr. Jestice testifies
`that Hagersten teaches the advantages of using point-to-point connections
`between nodes, which include allowing several SMP nodes to be linked
`together without running into many of the physical constraints and latency
`problems associated with other architectures. Ex. 1006 ¶ 133 (citing Ex.
`1004, 14:3–10). Mr. Jestice also testifies that Hagersten teaches the
`advantages include separate broadcasts during the same clock cycle
`originating from each SMP node, which allows for increased utilization of
`the system and enhanced productivity. Ex. 1006 ¶ 134 (citing Ex. 1004,
`15:4–7).
`Patent Owner disputes Petitioner’s proposed combination of
`Hagersten and Ekanadham. PO Resp. 51–52. Specifically, Patent Owner
`contends that completely replacing the adapter of Ekanadham with the XMP
`interface of Hagersten destroys the principle of operation of Ekanadham and
`renders it unsatisfactory for its intended purpose of maintaining data
`coherency in a computer system having a plurality of interconnected nodes.
`Id. at 56–57. According to Patent Owner, the adapter addresses the
`problems associated with providing shared-memory access across multiple
`switch-based SMP nodes by appearing as either a local processor or local
`memory, and using the local SMP coherence protocol within a node to
`accomplish the tasks, without any changes to the memory controllers. Id.
`
`
`6 Although Petitioner cites Ex. 1006 ¶ 39 on page 33 of the Petition, we view
`this as a clerical error and treat this as citing Ex. 1006 ¶ 139.
`18
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`Patent Owner contends that the XMP interface of Hagersten does not act as a
`local processor or a local memory, and does not use any local SMP
`coherence protocol. PO Resp. 57. Patent Owner concludes that replacing
`Ekanadham’s adapter with Hagersten’s XMP interface renders Ekanadham
`unsatisfactory for its intended purpose of maintaining data coherency. Id.
`Petitioner counters that a person of ordinary skill in the art would have
`connected the first and second nodes of Ekanadham using the
`point-to-point connections of Hagersten to connect the adapter of the first
`node of Ekanadham with the adapter of the second node of Ekanadham.
`Reply 6–7 (citing Ex. 1006 ¶¶ 152–156). Petitioner reasons that linking the
`point-to-point connections of Hagersten via adapters to the nodes in
`Ekanadham is a choice among a finite number of identified, predictable
`solutions. Pet 45 (citing Ex. 1006 ¶ 151). Petitioner further maintains that
`coupling a first node to a second node is accomplished in Ekanadham by the
`adapter, and Hagersten reinforces that internode point-to-point connections
`were known in SMP systems. Pet. 45–46 (citing Ex. 1006 ¶ 155).
`We disagree with Patent Owner’s contention that Petitioner’s
`combination of Ekanadham and Hagersten results in replacing the adapter of
`Ekanadham with the XMP interface of Hagersten. Instead, we are persuaded
`by Petitioner, and credit the supporting testimony of Mr. Jestice, that the
`functionality of the adapter of Ekanadham would not be eliminated based on
`the proposed combination. See Reply 6–7; Pet. 45–46; Ex. 1006 ¶¶ 151–
`156. Namely, because each node in the proposed combination would
`include the adapter of Ekanadham, which maintains coherency. Ex. 1003,
`1:36–43, 2:48–3:4.
`
`19
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`
`Patent Owner further argues that this configuration of retaining, rather
`than replacing, the adapter of Ekanadham, and connecting the adapter to the
`XMP interfaces of Hagersten, destroys the principle of operation of
`Ekanadham. PO Resp. 57–58. According to Patent Owner, Ekanadham
`requires that the adapter must not rely on broadcast of memory commands
`within a multiprocessor node, and that Hagersten teaches that transactions
`incoming from other SMP nodes are broadcasted by the XMP interface. Id.
`However, Petitioner’s proposed combination does not rely on using
`the individual SMP nodes of Hagersten in the computer system of
`Ekanadham, but rather, relies on using the network of point-to-point
`connections of Hagersten as the network connection shown in Figure 3a of
`Ekanadham, to connect the individual SMP nodes of Ekanadham. See Pet.
`43 (“it would have been obvious to modify Ekanadham in view of Hagersten
`to include a point-to-point connection between nodes” (citing Ex. 1006 ¶¶
`142–156)). Based on the entire record, we determine that using the network
`of point-to-point connections of Hagersten to connect the SMP nodes of
`Ekanadham, satisfies Ekanadham’s principle of operation that an adapter
`must not rely on broadcasts within an SMP node, because the combination
`includes the SMP nodes of Ekanadham, where all communications within a
`given node are made point-to-point, without the need for broadcasts. Ex.
`1003, 2:14–16.
`Further, Patent Owner contends that Petitioner and its expert do not
`articulate a sufficient reason why a person of ordinary skill in the art would
`have used a point-to-point connection in place of a switched connection to
`reduce latency in Ekanadham’s system. PO Resp. 58–61. According to
`Patent Owner, a person of ordinary skill in the art, reading Ekanadham,
`
`20
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`
`would not have considered latency as a deficiency that needs to be solved.
`PO Resp. 61.
`Petitioner directs us to passages in Hagersten teaching that a network
`of point-to-point connections allows SMP nodes to be linked together
`without running into latency problems associated with other architectures.
`Pet. 43 (citing Ex. 1004, 14:3–10, Ex. 1006 ¶ 133). Based on this
`understanding, we determine that Hagersten teaches latency was a known
`problem in the art, and would be avoided using point-to-point connections.
`See Ex. 1004, 14:6–10. Indeed, Ekanadham “must be read, not in isolation,
`but for what it fairly teaches in combination with the prior art as a whole.”
`See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986). We also
`credit the testimony of Mr. Jestice that the combination as a whole teaches
`that a person of ordinary skill in the art would avoid known latency
`problems in an SMP system by using the point-to-point connections of
`Hagersten. See Ex. 1006 ¶¶ 133, 143, 146, 149.
`Patent Owner further contends that a person of ordinary skill in the art
`would not have been readily able to combine Ekanadham and Hagersten.
`PO Resp. 61–62. Patent Owner highlights that Mr. Jestice testified that
`combining Ekanadham with Hagersten is “something that would probably
`take months to do.” PO Resp. 62 (citing Ex. 2005, 201:8–10). According to
`Patent Owner, a person of ordinary skill in the art would not have an
`expectation of success when combining the teachings of Ekanadham and
`Hagersten. Id.
`Petitioner contends that the Petition does not assert that a person of
`ordinary skill in the art would have been able to bodily incorporate the
`teachings of Hagersten into the system of Ekanadham. Reply 13–14 (citing
`
`21
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`In re Keller, 642 F.2d 413, 425 (CCPA 1981)). According to Petitioner,
`although Mr. Jestice t
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