midi
`
`2316E
`
`16K (2K x 3) ROM
`
`a Fast Access Tirne—45O ns Max.
`
`- EPROMIHOM Pin Compatible for
`Cost-Effective System
`
`II Single +5V‘_". 10% Power Supply
`
`DeV9'°P""'°'“
`
`I
`.
`:1 ntel MCS 80 and B5 Compatible
`a Three Programmable Chip
`Selects for Simple Memory
`Expansion and System Interface
`
`I Completly Static Operation
`_ Inputs and outputs TTL
`compatible
`- Three-State Output for Direct
`Bus interface
`
`The lntelm‘ 231EE is a 16,384-bit static, N-channel MOS read only memory {ROM} organized as 2048 words by 8 bits. Its
`high bit density is ideal for large, non-volatile data storage applications such as program storage. The three-state outputs and
`TTL lnputfoutput levels allow for direct interface with common system bus structures. The 2316E single +5V power supply
`and 450 ns access time are both ideal for usage with high performance microcomputers such as the Intel MCSTM-80 and
`MCSTM-85 devices.
`
`A costeffective system development program may be Implemented by using the pin compatible Intel 2?16 16K UV EPROM
`for prototyping and the lower cost 2616 FROM and 23165 ROM for production. The 2716 is fully compatible to the 23lEE
`in all respects. The three 2315E programmable chip selects may be defined by the user and are fixed during the masking pro-
`cess. To simplify the conversion from 2716 prototyping to 23165 Production, it is recommended that the 23165 program-
`mable chip select logic levels be defined the same as that shown in the below data sheet pin configuration. This pin configu ra-
`tion and these chip select logic levels are the same as the 2?16.
`
`PIN CONFIGURATION
`
`BLOCK DIAGRAM
`
`Duntuznafl-IDsDa D:
`
`
`1:51 4353 CHIP SELECY mnurs
`
`DLIVPU? BufFEFl5
`-I-I-II
`Y DECODER | OF '6 I 3
`
`I6. 154811
`CEKL UAYFIIK
`
`
`
`IIJFITOCIERII23
`
`DEIEIEDE
`
`CHIP
`SELECI
`FROG
`
`CHI?
`SELECT
`INPLJY
`BLIFFERS
`
`PIN NAMES
`flgnfltn
`aounzssmr-urs
`U',|I—|'.‘ll2|
`can nu‘rru‘iS
`
`‘
`
`“ID
`“'-'
`
`U!atu.-u.
`5:-Dn.
`EV.‘v--.u:1’1::0C
`
`201
`
`201
`
`

`
`2316E
`
`ABSOLUTE MAXIMUM RATINGS*
`
`Ambient Temperature Under Bias.
`Storage Temperature .
`.
`.
`.
`.
`.
`.
`.
`.
`Voltage On Any Pin With Respect
`to Ground .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Power Dissipation .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.—10°C to 30°C
`.
`.
`.—E5°C to +15C|°C
`
`.
`.
`
`.
`.
`
`. -0.90‘ to -i-TV
`.
`.
`.
`.
`. 1.0 Watt
`
`‘COMMENT: Stresses above those listed under "Absolute lll'Ia)ti~
`murn Ratings" n-rev cause permanent damage to the device. This is a
`stress rating only and functional operation oi the device at these or
`at any other conditions above those indicated in the operational
`sections of this specification is not implied. Exposure to absolute
`maximum rating conditions for extended periods may afiect device
`reliability.
`
`D.C. AND OPERATING CHARACTEFHSTICS
`
`TA = 0°C to +70°C, Vcc = 5V i1lJ%. unless otherwise specified.
`
`TEST CONDITIONS
`
`Von
`
`Input Load Current
`IIAII Input Pins]
`
`1
`
`Output Leakage Current
`Power Supply Current
`Input "Low" Voltage
`Input "High" Voltage
`
`Output “Low” Voltage
`Output "High" Voltage
`NOTE: 1, Typical values for TA = 25°C and nominal supply voltage.
`
`A.C. CHARACTERISTICS
`
`TA = 0°C to +?0”C. Vcc = +5V 110%. unless otherwise specified.
`
`SYMBOL
`
`PARAMETER
`
`Address to Output Delay Time
`
`Chip Select to Output Enable Delay Time
`
`Chip Deselect to Output Data Float Delay Time
`
`to;
`
`CON DITIONS O F TEST FOR
`A.C. CHARACTERISTICS
`
`CAPACITANCE“ TA= 25°C, r= 1 rum:
`
`. 1 TTL Gate and C;_= 100 pF
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Output Load .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.l‘.|.8 to 2.4V
`.
`.
`.
`.
`.
`.
`Input Pulse Levels .
`Input Pulse Rise and Fall Times l10% to 90%} .
`.
`.
`. .20 ns
`Timing Measurement Reference Level
`Input
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Output .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`. IV and 2.2V
`.
`.
`. .().BV and 2.0V
`
`.
`.
`
`.
`.
`
`SY MBO L
`
`TEST
`
`
`
`All Pins Except Pin Under
`Test Tied to AC Ground
`
`All Pins Except Pin Under
`Test Tied to AC Ground
`
`NOTE: 2. This parameter is periodically sampled and is not 100%
`tested.
`
`Ti‘-6
`
`202
`
`202
`
`

`
`.C. waveforms
`
`mm[SS
`
`nnnn AMIIABLE.
`
`CHIISEI.[CIS
`
`23'|6E
`
`‘A
`
`I
`
`’ypical System Application (BK X 8 ROM Memory)
`
`ADDR E55 BUS
` MCSEO
`CONT EDI. BUS
`SYSTEM
`EUS
`DA'l'k BUS
`
`
`
`
`CHIP
`8: Lin
`DECODER
`1m1‘EI.
`
`
`
`T-T
`
`203
`
`203
`
`

`
`
`
`I-"-SI-"-S
`
`
`
`204204
`
`204
`
`

`
`Welfl
`
`3703
`
`8192 BIT ERASABLE AND ELECTRICALLY
`
`REPROGRAMMABLE READ ONLY MEMORY
`
`0 8708 1024xB Organization
`
`it Fast Programming— _
`
`= static-——No Clocks Ftequired
`
`II Low Power During Programming
`I Access Time—450 ns
`
`Compatible During Both Read
`and P'°9"=‘“1 I‘-“Odes
`
`is a high speed 8192 bit erasable and electrically reprogrammable ROM IEPFIOM)
`The Intel” STDEI
`fast turn around and pattern experimentation are important requirements.
`
`ideally suited where
`
`The 8708 is packaged in a 24 pin dual-in—1lne package with transparent lid. The transparent lid allows the user to expose the
`chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device.
`
`A pin for pin mask programmed ROM. the Intel” 3308, is available for large volume production runs of systems initially
`using the B?'DB.
`
`The 8}'IJ8 is fabricated with the time proven N-channel silicon gate technology.
`
`PIN CONFIGURATION
`
`BLOCK DIAGRAM
`
`barn uumn‘
`at D!
`li‘?J:_:‘:'I
`
` output’ Euseefis
`
`
`
`V GATING
`
`6! I133
`HDM ARRAY
`
`INFUPS
`
`an -1..
`ADD H E SS
`
`PIN NAMES
`
`DITIQ UUIPUIS
`CHlPSELEC'[I'WRl‘E ENKBLE |Nl’U\'
`
`4!:
`EEI
`
`
`743
`
`205
`
`205
`
`

`
`PROGRAMMING
`The programming specifications are Identicai Io those of the 2708. (See ROM and PROM Programming Instructions,
`P85’-‘3 6'--74}.
`
`ABSOLUTE MAXIMUM RATINGS‘
`
`8708
`
`.
`.
`.
`.
`.
`.
`.
`Temperature Under Bias .
`.
`.
`.
`.
`.
`.
`.
`Storage Temperature .
`.
`.
`.
`.
`.
`.
`.
`.
`VDD With Respect to V33 .
`Vgc and V35 With Respect to V55 .
`All Input or Output Voltages With
`Flespect to V35 During Head .
`CHSM E Input With Respect to V33
`.
`.
`.
`During Programming .
`.
`.
`.
`.
`.
`Program Input With Respect to V33 .
`Power Dissipation .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`
`. -25°C to +85°C
`.—65°C to +‘I25°C
`.
`. +2€|V to -0.3V
`.
`. +15V to —D.3V
`
`.
`
`.
`.
`.
`
`. +15V to -0.3V
`
`. +2OV to —0.3V
`. +35V to -0 3V
`.
`.
`.
`.
`.
`.
`‘I.5W
`
`‘COMMEN T: Stresses above those Ifsred under “Absa.*ure
`Maximum Ratings" may cause permanent damage to the
`device. T.-‘H's is a stress raring orrfy and functional opera-
`tron of the device at these or any other conditions above
`those indicated in the operaobnai sections of this goeciffi
`cation is not implied. Exposure to absolute maximum
`raring conditions for ex tended periods may affect device
`refiabrflty.
`
`READ OPERATION
`
`D.C. AND OPERATING CHARACTERISTICS
`
`TA = 0°C to ru°c. vcc = +5v 25%, V3,, = +12v tars, V33 = —5v :5%, V55 = 0V, Unless Otherwise Noted.
`
`T\rp.m
`I
`I
`50
`6
`
`30
`
`Max.
`10
`10
`55
`10
`
`45
`
`i Unit
`,uA
`.uA
`mA
`mA
`
`Conditions
`V." = 5.25 V or \I'm = V"_
`Vour = 5.25V, CEIW E = 5V
`Worst Case Supply Currents:
`All Inputs High
`
`rnA
`
`C§M‘E = 5V: To = 0°C
`
`
`
`—I Min.
`Parameter
`Symbol
`||_|
`1 Addressand Chip Select |nput5ink Current—I
`ILQ
`Output Leakage Current
`Ian I?" LVDD Supply Cu rrent
`lccm
`Vcc Supply Current
`
`IBBWI
`V33 Supply Current
` w Voltage
`V|H -1 Input High Voltage
`
`="v_.,5
`3.0
`
`1 Output Low Voltage
`VOL
`Output High Voltage
`VOH1
`IQ“ = —‘In1A
`—_I
`Output High Voltage
`V932
`mW i_T,. = 70°C
`300
` n T
`NOTES:
`1. Typical values are forTA = 125°C and nominal SUI‘-'I'-||\I' \I'0|1i|G|!$—
`is not Ialwlahln by mmming tin: uarinux I:I.l1'VInls
`2. The Int-al power dissipation of the MOB is spaclfied at EDI] mw. It
`IIDD, Icc, and lggl multiplied by their resaelrtive voltages since current path: exist between the various power supplies and
`V55. Tha Inn, ICC, and lag current: should be used to determine power supply capacity only.
`
`_L
`
`3.?
`2 4
`
`TYPICAL D.C. CHARACTERISTICS
`
`MAXIMUM JUNCTION TEMPERATURE
`VS. AMBIENT TEMPERATURE
`
`RANGE OF SUPPLY CUFIHENTS
`VS. TEMPERATURE
`nu rams L: ovmanuo
`DOIIDIYIONSL
`vac - szsu
`
`OUTPUT SINK CURRENT
`VS. OUTPUT VOLTAGE
`
`Im_Imnl1
`
`//WUlrv
`
`
`
`sul-PWI.'.I.IFIllENISImfl-I
`
`?-‘I['.'
`
`206
`
`206
`
`

`
`B708
`
`A.C. CHARACTERISTICS
`
`TA = We to 'rc"c, vac = +5v 15%, V95. = +12v ssei, V33 = —sv 25%, v55 = 0V, Unless Otherwise Noted.
`
`Parameter
`
`Address to Output Delav
`Chip Select to Output Delay
`Chip De-Select to Output Float
`
`Symbol
`
`tacc
`
`
`
`
`
`
`Address to Output Hold
`
`Note . This parameter is periodically sampled and not 100% tested.
`
`A.C. TEST CONDITIONS
`Output Load:
`1 '|'|'L gate and CL = 100pF
`Input Rise and Fall Times:
`€2Elns
`Timing Measurement Reference Levels: ELEV and 2.3V for inputs; 0.8V and 2.4V for outputs
`Input Pulse Levels: O.B5V to 3.|JV
`
`WAVEFORMS
`
`ADDRESS
`
`
`
`ERASURE CHARACTERISTICS
`
`The erasure characteristics of the BT03 are such that
`erasure begins to occur when exposed to light with
`wavelengths shorter than approximately 4000 Angstroms
`(A). It should be noted that sunlight and certain types of
`fluorescent lamps have wavelengths in the 3000-AUODA
`range. Data show that constant exposure to room level
`tlourescent
`lighting could erase the typical 8'l'Cl8 in
`approximately 3 years while it would tal-teapproximatelyl
`week to cause erasure when exposed to direct sunlight. If
`the 3703 is to be exposed to these types oi
`lighting
`conditions tor extended periods oltirne. opaque labels are
`avallable from Intel which should be placed over the B708
`window to prevent unintentional erasure.
`
`The recommended erasure procedure [see page 3-55} for
`the M03 is exposure to shortwave ultraviolet light which
`has a wavelength at 253? Angstroms (A). The integrated
`dose (i,e.. UV intensity X exposure time} for erasure
`should be a minimum of 15W-secilcrnz. The erasure time
`with this dosage is approximately 15 to 20 minutes using
`an ultraviolet tamp with a ‘l2{lE|E|pWl'cm3 power rating.The
`8?05 should be placed within one inch from the lamp tubes
`during erasure. Some lamps have a filter on their tubes
`and this lilter should be removed helore erasure.
`
`?~1 ‘I
`
`207
`
`207
`
`

`
`
`
`7'127'12
`
`
`
`208208
`
`208
`
`

`
`2716
`
`16K (2Kx8) UV ERASABLE PROM
`
`I Single -I-5V Power Supply
`
`I Pin Compatible To Intel 2316E ROM
`
`9 Simple Programming Floquiromonts
`
`_
`
`Programs with One 50ms Pulse
`
`I Low power Dissipation
`525mW' Max. Active Power
`132mW Max. Standby Power
`
`I Inputs and Outputs TTL
`Cflmpatible D|"i|'|9 R9-‘ad
`And Program
`
`The lnteI® 2?16 is a 15,384-bit ultraviolet erasable and electrically programmable readvonly rnarrlonl lEPROM|. The 2}"i6
`operates from a single 5-volt power supply, has a static power down mode, and features {est single address location program-
`ming. It makes designing with EPROMS faster, easier and more economical. For production quantities, the 2716 user can
`convert rapidly to Intel's new pin-for-pin compatible ll-BK ROM. the 231!-SE.
`
`Since the 450«nsec 2715 operates from a single 5-volt supply, it is ideal for use with the newer high performance 4-5V micro-
`processors such as Intel's 8085 and SD48. The 2?16 is also the first EPROM with a static power down mode which reduces
`the power dissipation without increasing access time. The maximum active power dissipation is 525 rnw while the maximum
`standby power dissipation is only 132 mW. a 'r‘5% savings.
`The 2?lfi has the simplest and fastest method vet devised for programming EPFl0ll.lls + single pulse TTL level programming.
`No need for high voltage pulsing because all programming controls are handled bv TTL signals. Now, it is possible to program
`on—board.
`in the system, in the field. Program anv location at any time — either individually. sequentially or at random, with
`the 2716's single address location programming. Total programming time for all 16,384 bits is only 100 seconds.
`
`PIN CONFIGURATION
`
`,_e|__
`""5
`
`_
`i
`..
`
`. MGDE
`i Rue
`' Dnrleu
`:__
`Power Down
`E "uteri-n
`i Pragrlm Verde
`._.
`mam-. inn-n.:
`
`MODE SELECTION
`
`i
`|
`!
`
`ci
`£201
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`Vi.»
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`
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`.
`
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`litlll
`'5
`'5
`‘5
`'5
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`-25
`-9
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`-5
`-25 ~
`«s
`
`.
`_
`._
`
`'
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`
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`D.-.
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`Hug“ a
`
`..
`
`i
`
`-
`_ .
`
`
`OUTPUTS
`
`Vcc o--—--—
`6NDO——-.——
`Up’ fi1-—|—a-or
`
`pg,,u,,.
`
`M__,“,
`
`BLOCK DIAGRAM
`one ounrufs
`up-01
`
`clue s£LEI: T.
`rowel? pawn. Mil:
`9395 Log];
`5'
`DE EDD!‘
`
`X
`DECEJDER
`
`DI.l‘I'PUl BUFFEIIS
`
`V-GAIING
`
`l5.I8o|-BIT
`
`CELLI|lA'I'RlX 00-01
`
`roman
`
`ADDRESSES
`eowse oowmeaocrmm
`
`7-13
`
`209
`
`209
`
`

`
`2716
`
`
`PROGRAMMING
`The programming s,aeci'i'icari'ar:s are described in the PROM/ROM Pra§’5"“”””Si r‘»"i5ff¢-if-‘|'t'D'?-F 0” W39 3'55
`
`Absolute Maximum Ratings‘
`
`.
`.
`.
`.
`.
`.
`Temperature Under Bias.
`-
`.
`.
`.
`.
`.
`.
`Storage Temperature .
`.
`.
`All input or Output Voltages with
`Respefl to Ground '
`'
`‘
`’
`'
`'
`‘
`'
`VPP SUPPIY V‘-$1399 Wm‘ R9593“
`to Ground .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`
`‘
`
`.
`
`.
`.
`
`'
`
`.
`
`.
`.
`
`'
`
`.
`
`n
`.—1£i°Cto +BiJ:C
`.
`.
`. .-65 C to +125 C
`
`'
`
`.
`
`'
`
`.
`
`'
`
`' *5‘; to ‘Gav
`
`. +28V to +iJ.3V
`
`-
`.4
`.
`.
`.
`'COMMENT.‘ Stresses above those imea under “Absolute Maxi-
`SHIISS fflliflg DD ‘ii an
`UTIC 10413 Dflefiillflfl D
`E‘
`SINCE 3
`E
`I’
`mum Ratings
`lrnav {claims i:‘Iern1a|u-inn:damageftehinfideuiceimiixza
`any other conditions above those indicated in the operational sec-
`tions of
`this specification is not
`implied. Exposure to absolute
`maximum rating conditions for extended period: may affect device
`reiiauiimn
`
`READ OPERATION
`
`DI). and Operating Characteristics
`
`TA = o"c to 'ro“c. vac“-11 = mi 15%, vppitl = vac :n.avi3l
`
`Parameter
`
`Condition!
`
`
`
`VOUT = 5.25V
`
`Vpp = 5.85\.r‘
`
`PDIPGM = V"... E§= V”_
`
`C_S= PDIPGM = v,L
`
`I;,,_ = 2.1 mA
`
`I5... = -400 ,uA
`
`V
`
`V
`
`V
`
`V
`
`[L45
`
`input Load Current
`
`Output Leakage Current
`
`Vpp Current
`
`Vcc Current [Standbv]
`
`Vcc Current [Active]
`
`Input Low Voltage
`
`Input High Voltage
`
`Output Low Voltage
`
`Output High Voltage
`
`NOTES:
`
`I. Vac must be applied simuitanepusiv or before win and removed sirnuitanepusly or after Vpp.
`2. Vpp may be connected directly to UL-C except during programming. The suppfv current would then be the sum DI icc and |pp1.
`3. The tolerance of DEV allow! the use ot a driver circuit I'D! twitching the \.-''pp supply pirr Irum Vcc in read to 25V for mogram‘
`|'Y‘lil'I§.
`4. Typical values are for TA = 25°C and norniriai supply voltages.
`G1
`. This parameter is only sampled and is not 100% tested.
`6.
`(‘A553 is referenced to PDJPGM or the addresses, whichever occurs iast.
`
`Typical Characteristics
`
`lcc CURRENT
`VI’.
`TEMPERATURE
`
`ACCESS TIME
`VS.
`CAPACITANCE
`
`ACCESS TIME
`IFS.
`TEMPERATURE
`
`W‘ UR N
`rorrau - vu,
`
`TIMIERAYIJHE 1'6!
`
`IceEmil 100
`
`IEIIFKIIATURE I'll!
`
`500
`
`SDI!
`
`I00
`CL TpF|
`
`?-14
`
`210
`
`210
`
`

`
`2715
`A.C. Characteristics
`
`r,. = o”c to ?o”c, vccfil = +5v :5%, veem = vac :u.ev‘31
`
`
`,.
`C
`T
`m Tvpflal a est ondmons
`
`
`
`
`
`1 TTL gate and CL = 100 5:?
`Output Load:
`Input Rise and F311 Times:
`€20 ns
`Input Pu1se Levels: 0.8V to 2.2V
`Timing Measurement Reference Level:
`Inputs
`IV and 2V
`Outputs
`0.8V and 2V
`
`
`
`Parameter
`
`
`
`
`tpp
`
`Address to Output Deiav
`enresu to Output Delay
`4551
`PD./PGM = V“_
`Chip Select to Output De1ay I 120
`I30
`E = v1._
`PDIPGM to Output Float
`
`PDIPGM = v.._
`Chip Deselect to Output Float
`mu
`E Address to Output Hem
`PDIPGM = E; = v.._
`Capacitancem Te. = 25°C, f= 1 MHz
`A.C. Test Conditions:
`
`
`-'W'"*=°'m@
`TE
`
`
`HIE
`
`
`
`NOTE: Please re In to page 2 [or notes.
`
`WAVEFORMS
`A. Read Mode
`PD,-‘PGM = v.._
`
`AD DR ES
`
`125
`
`EILHFUI
`
`DATA BUY VALID
`
`B. Standby Mode
`a = V 1L
`
`nannzss
`
`nnuaessm
`
`gnnnfssuun.
`
`
`
`
`STANDBY MODE
`
`
`ICYIVEMDDE
`
`DITR V-ILID FUR fiDDHE§N
`
`DAVA VfiL|D FOR ADDRESSNOM
`
`7-15
`
`211
`
`PDEPGNV
`
`UUYPUY
`
`211
`
`

`
`2716
`
`ERASURE CHARACTEMSTICS
`The erasure characteristics of the 2716 are such that erasure
`begins to occur when exposed to light with wavelengths
`shorter than approximately 4000 Angstrorns IA}. is should
`be noted that sunlight and certain types of fluorescent
`lamps have wavelengths in the 3l.'l0O—4l.'lD0}l. range. Data
`show that constant exposure to room level fluorescent
`lighting could erase the typical 2ir'16 in approximately 3
`years, while it would take approximatley 1 week to cause
`erasure when exposed to direct sunlight. If the 2}'l6 is to
`be exposed to these types of lighting conditions for ex-
`tended periods of time. opaque labels are available from
`Intel which should be placed over the 2?16 window to
`prevent unintentional erasure.
`The recommended erasure procedure {see page 3-55] for
`the H16 is exposure to shortwave ultraviolet light which
`has a wavelength of 253? Angstroms (Al. The integrated
`close ii.e.. UV intensity X exposure time} for erasure should
`be a minimum of 15 W-secfcmz. The erasure time with this
`dosage is approximately 15 to 20 minutes using an ultra-
`violet lamp with a 12000 ,pll\ll'cm2 power rating. The 2?'l6
`should be placed within 1
`inch of the lamp tubes during
`erasure. Some lamps have a filter on their tubes which
`should be removed betore erasure.
`
`DEVICE OPERATION
`
`The six modes of operation of the 2'l'16 are listed in Table
`i. It should be noted that all inputs for the six modes are at
`TTL levels. The power supplies required are a +5V V5; and
`a Vpp. The Vpp power supply must be at 25V during the
`three programming modes. and must be at 5V in the other
`three modes.
`
`TABLE I. MODE 5EI.ECl'lDN
`
`""5
`
`
`
`Port-GM
`l'lBl
`
`
`
`E
`L2|!I
`
`V9;
`I21!
`
`V5;
`ll-ii
`
`vsli
`
`OUTPUTS
`[9-‘l'l.1’.‘f-'l‘.l'l
`Dout
`i-«.9»:
`
`Power Down
`
`Prcuram
`
`READ MODE
`
`Data is available at the outputs in the read mode. Eata is
`available 450 ns ltacgl from stable addresses with CS low
`or 120 ns ltcol from G3 with addresses stable.
`
`_
`DESELECT MODE
`The outputs of two or more 2'ir"l6s -may be OR-tied to-
`gather on the sante_data bus. Only one 27l'fishbti|d have its
`outputs selected [CS low} to prevent data bus content_ion_
`between 2716;
`in this configuration. The outputs of, the.
`other 27165 should be deselected with the 3 input at a
`high TTL level.
`
`_
`
`POWE Fl DOWN MODE
`
`The 2716 has a power down mode which reduces the active
`power dissipation by 75%,
`from 525 mW to 132 rnw.
`Power down is achieved by applying a TTL high signal to
`the PDIPGM input.
`in power down the outputs are in a
`high impedance state. independent of the (-3 input.
`
`PROGRAMMING
`
`Initially. and after each erasure, all bits of the 2716 are in
`the "1" state. Data is introduced by selectively program-
`ming "Cl’s" into the desired bit locations. Although only
`"D's" will be programmed. both "l’s" and ''0's'' can be
`presented in the data word. The only way to change a “O"
`to a "1" is by ultraviolet light erasure.
`
`The 2T16 is in the programming mode when the Vpp power
`supply is at 25V and C5 is at VH4. The data to be pro-
`grammed is applied 3 bits in parallel to the data output
`pins. The levels required for the address and data inputs are
`TTL.
`
`when the addresses and data are stable, a 50 msec, active
`high, TTL program pulse is applied to the PDJPGM input.
`A program pulse must be applied at each address location
`to be programmed. You can program any location at any
`time — either
`individually, sequentially, or at random.
`The program pulse has a maximum width of 55 msec. The
`2}"l6 must not be programmed with a DC signal applied to
`the PD/PGM input.
`Programming of multiple 2'r'16s in parallel with the same
`data can be easily accomplished due to the simplicity of
`the programming requirements. Like inputs of the paral-
`leled 2715s may be connected together when they are pro-
`grammed with the same data. A high level TTL pulse
`avplied to tha PDIPGM input programs the paralleled
`2116;
`PROGRAM INHIBIT
`
`Programming of multiple 27155 in parallel with different
`data is also easily accomplished. Except for POIPGM, all
`like inputs {including fill of the parallel 27165 may be
`common. A TTL level program pulse applied to a 2?i6's
`PDXFGM input with Vpp at 25V will program that 2}'l6.
`A low level PDKPGM input inhibits the other 27155 from
`being programmed.
`PROGRAM VERIFY
`
`A verity should be performed on the programmed bits to
`determine that they were correctly programmed. The verify
`may be performed wth Vpp at 25V. Except during pro-
`gramming and program verify, Vpp must be at 5V.
`
`7-15
`
`212
`
`212
`
`

`
`MU
`
`8101A-4
`
`1024 BIT STATIC MOS RAM
`
`WITH SEPARATE I/O
`
`* 450 nsec Access Time Maximum
`
`* 256 Word by 4 Bit Organization
`
`5 Single +5V Supply Voltage
`
`I Powerful Output Drive Capability
`
`I Directly TTL compatible: All inputs and
`Outputs
`
`I Low Cost Packaging: 22 Pin Plastic Dual
`In-Line configuration
`
`I static MOS: No Clocks or Refreshing
`Reqmred
`' sI"”P'° M°“"°'5' E"Pa“5I°“‘ chip E"ab'°
`Input
`
`I Low Power: Typically 15t)mW
`I Three-State Output: OF!-Tie Capability
`I! Output Disable Provided for Ease of Use
`in Common Data Bus Systems
`
`The inteifl‘ 8101A-rtls a 256 word by 4-bit static random access memory element using N-channel MOS devices integrated
`on a monolithic array. It uses iulty DC stable {static} circuitry and therefore requires no cioci-cs orreireshing to operate.
`The data is read out nondestructiyely and has the same polarity as the input data.
`The 8101A-4 is designed for memory applications where high performance. low cost. large bit storage. and simple
`interfacing are important design obiectives.
`it is directly TTL compatible in all respects: inputs. outputs. and a single +5V supply. Two chip-enables allow easy
`selection of an individual paoltagewhen outputs are OR-tied. An output disable isprovidedso thatdata inputs and outputs
`can be tied for common I/O systems. The output disable function eliminates the needtor bi—directionai logic in a common
`IICI system.
`The inteli‘-‘J 8101A-4 is fabricated with N-channel silicon gate technology. This technology allows the design and
`production of high performance. easy-to-use MOS circuits and provides a higher Iunctionel density on e monollthlcchip
`than either conventional MOS technology or P-channel silicon gate technology.
`Intel's silicon gate technology also provides excellent protection against contamination. This permits the use of low cost
`plastic packaging.
`
`
`PIN CONFIGURATION
`
`LOGIC SYMBOL
`
`BLOCK DIAGRAM
`
`st, .
`
`_
`
`:2 commits
`
`3: news
`
`..>.2’.,=-.>I.93:- RJW CE! CE1
` Ci LL AH HAY
`0OD.-..E,.-_-
`
`
`
`
`
`cu
`an .
`
`O - rm ivuniesns
`
`PIN NAMES
`IIHIP ENABLE 2
`DATA INPUT
`CE,
`_
`OIJTPUT Dl5J\§I.E
`ADDRESSINPUTS
`U0
`HE-§Dl'|'I'fiIl'E INPUT
`DD,-DO, DJITA DIJTFLIT
`CHIP ENABLE I
`V“
`
`POWER I*5\|'|
`
`?-1?
`
`213
`
`213
`
`

`
`8101A-4
`
`ABSOLUTE MAXIMUM RATINGS*
`
`Ambient Temperature Under Bias .
`Storage Temperature .
`.
`.
`.
`.
`.
`.
`.
`.
`_
`Vnltége 0" AW P"-'
`wflh Respect to Gmund '
`Pawer Dissipation .
`.
`.
`.
`.
`.
`.
`
`'
`.
`
`'
`.
`
`‘
`.
`
`.
`.
`
`'
`.
`
`.
`.
`
`'
`.
`
`.
`
`. -10°C to 30°C
`-E5“C to +15G°C
`
`'
`.
`
`'
`.
`
`'05“ 1° av
`.
`.
`.
`.
`1 Watt
`
`.
`
`‘
`.
`
`COMMENT-‘
`Stresses above those listed under "1-Ibsolute Maximum
`I-'1‘arr'ng"may cause permanent damage to the device. This
`is a stress rating orfly and functional operation of the de-
`vice at these or at any other condition above more End!-
`cared in the operational sections of rm‘: :oec:‘fr'carr‘on is
`not imp)‘.-‘ed. Exposure to absolute maximum raring corr-
`ditfons for extended periods may effect dew'r:e reffebrlfnr.
`
`D.C. AND OPERATING CHARACTERISTICS
`
`TA = 0°C to 70°C, Vcc = 5V 15% unless otherwise specified.
`
`
`
`Parameter
`
`
`Symbol
`
`
`
`IOH E '40”!-IA
`
`IDL = 2.DrrIA
`
`TYPICAL D.C. CHARACTERISTICS
`
`CIUTPUTSDURCE CURRENT VS.
`OUTPUT VOLTAGE
`I
`AMI! TENT 'I' EMPE Il.I'l’IJ|1 E
`
`OUTPUT SINK CURRENT VS.
`OUTPUT VOLTAGE
`V '
`mmam mmnu-um: - MC ’
`IIIIIA
`
`
`nu'rPI.rr "HI|1H"YVFhCAL um wens}
`
`vcc - MW
`
`rmInull
`
`NOTES:
`
`1. Typical values are for T3; = 25°C and nnrnlnal supply voltage.
`2.
`Input and Output tied together.
`
`'i"-18
`
`214
`
`IL.
`ILOH
`ILOL
`Icm
`
`lccg
`
`Inpul Current
`
`
`U0 Leakage Currentlill
`
`IICI Leakage Currentm
`
`Power Supply
`
`Current
`
`Power Supply
`
`Current
`
`Input "Low" Voltage
`
`Input "High" Voltage
`
`Output "Low" Voltage
`VQL
`
`Output "High"
`Von
`Voltage
`
`Test Conditions
`
`Vm = D to 525V
`Output Disabled, Vgu-r=4.0V
`Output Disabled, Vgu-1-=D.45V
`Vw - 5.25V, IQ = Eln-IA
`Tg = 25°C
`Vw = 5.25V, lg = lJn'IA
`TA = 0°C
`
`
`214
`
`

`
`8101A-4
`
`A.C. CHARACTERISTICS
`READ CYCLE Te = u“c to ?0°C, Va; = 5V :5-re, unless otherwise specified.
`Parameter
`
`
`
`Head Cycle
`Access Time
`
`Chip Enable To Output
`
`
`
`
`
`
`0
`
`Output Disable To Output
`Data Output to High 2 State I
`Previous Read Data Valid
`after change of Address
`
`
`
`
`
`
`
`2?!)
`20
`250
`250
`
`._
`
`Test Conditions
`
`
`[See Be Iowi
`
`Test cOl'l|:IltICIl'IS
`
`
`(See Below}
`
`Pap-amgggr
`Write Cycle
`
`Write Delay
`Chip Enable To Write
`Data Setup
`Data Hold
`Write Pulse
`Write Recovery
`
`
`
`
`tgH
`twp
`
`
`
`
`
`Output Disable Setup
`
`20
`
`A.C. CONDITIONS OF TEST
`
`CAPACITANCE
`
`TA = 25"'C,f= 1MHz
`
`I3]
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`tntf
`.
`.
`.
`.
`Input Levels .
`Timing Reference .
`Load .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`
`. 20 l'IS
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`. 0.8V or 2.0V
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`1.5V
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. 1TTL Gate and c,_ = 100 [F
`
`Svmbol
`C
`
`W
`
`Cour
`
`WAVEFORMS
`HEAD CYCLE
`
`Test
`Tan 9
`C
`I
`"F'”‘
`film‘
`'3
`lA|l1npi.it Pins} Um = 0V
`
`Limits [PF]
`T m M“
`"”°'
`4
`
`8
`
`12
`
`
`
`WRITE CYCLE
`
`ADDRESS
`
`l.j.—_—_ '31: ———j.
`
`ADDRESS
`
`l
`
`teeL-I
`
`
`
`65
`
`EE2
`
`4. DD should be tied low lor separate I.FD operation.
`
`no
`-— dcaamou not "‘
`
`I‘.[I
`
`CE?
`
`DD
`icon MON iiol '“
`
` _j._—.-
`
`DAY fl
`
`OUT
`
`4
`
`P
`
`DAT R O U I’
`
`VALID
`
`
`
`INCITES:
`
`1. "Typical values are for Tg ' 25"C and nominal supply voltage.
`2.
`t5}: iswith respect to the trailing edge of E1, CB2, or 0D,
`whichever occurs first.
`3. This parameter is periodically sampled and is not 100% tested.
`
`T-19
`
`215
`
`215
`
`

`
`
`
`F-20F-20
`
`
`
`216216
`
`216
`
`

`
`fin”
`
`8111A-4
`
`1024 BIT STATIC MOS RAM
`
`WITH COMMON I/O
`
`* 450 nsec Access Time Maximum
`
`* 256 Word by 4 Bit Organization
`
`13 Single +5V Supply Voltage
`
`cl Powertul Output Drive Capability
`
`El Directly TTL Compatible: All
`and Outputs
`
`Inputs
`
`El Low Cost Packaging:1B Pin Plastic Dual
`In-Line Configuration
`
`III Static MOS: No Clocks or Fteireshing
`Required
`5' 5““P'*‘-' 'V'°"“°'Y E"P3"5'°"= Chip E“3b'°
`'"P‘“
`
`to Low Power: Typically 15lJl11W
`CI
`Three-State Output: OF!-Tie Capability
`an output Disable Provided for Ease of Use
`in Common Data Bus systems
`
`The |nte|® 3111A-4is a 256 word by 4-bitstatlc random access memory element using N-channel MOS devices integrated
`on a monolithic array. It uses fully DC stable (static) circuitry and lhereiore requires no clocks or refreshing to operate.
`The data is read out nondestructively and has the same polarity as the input data. Common inputlioutput pins are provided.
`The 81'l‘lA-4 is designed for memory applications in small systems where high performance, low cost, large bit storage,
`and simple interlacing are important design objectives.
`it is directly TTLoompatible in all respects: inputs, outputs. and asingle +5V supply. Separate chip enable tfi) leads allow
`easy selection oi an individual package when outputs are OF!-tied.
`The lntelfl 8111A-4 is fabricated with N-channel silicon gate technology. This technology allows the design and
`production of high performance. easy-to-use MOS circuits and provides a higher functional density on a monolithic chip
`than either conventional MOS technology or F’-channel silicon gate technology.
`Intel‘s silicon gate technology also provides excellent protection against contamination. This permits the use of low cost
`plastic packaging.
`
`PIN CONFIGURATION
`
`LOGIC SYMBOL
`
`BLOCK DIAGRAM
`
`M E Mon \' ARM av
`31FhDt\lS
`32 SDI LIltll\I5
`
`D
`IZDLIJMNIJO clrlcuns
`BDLEJMII SELECT
`
`
`
`
`
`
`
`It.
`
`5
`
`_o
`
`J’.3‘3‘J‘
`
`"1:
`*5
`
`‘ii
`
`‘i
`3
`
`PIN lvArvll=.s
`
`Aocluzss mrurs _
`LAn'$?
`' o'o_'_ Dfifii fi'.TtL£T
`' a.Mr__ nzmnvnlrsllvrur
`_i:E_t_ _
`Cl'£E_l_\|-BELE 1
`CE}
`CHIF ENRELE 2
`' Flor-175: "olrnfiificufiur"
`
`‘F-21
`
`217
`
`-"
`
`cs,
`‘,1 @
`' @
`‘
`oo -—’C>-
`
`0 win NUMIE 5:
`
`217
`
`

`
`8111A-4
`
`
`ABSOLUTE MAXIMUM RATINGS‘
`
`"COMMENT:
`
`Ambient Temperature Under Bias .
`
`.
`
`.
`
`.
`
`Storage Temperature .
`Voltage 0:1 Any Pin
`with Respect to Ground .
`Power Dissipation .
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`
`.
`.
`
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`. -10°C to 80°C
`
`-65°C to 1-150°C
`
`.
`.
`
`-0.5V to +?V
`.
`.
`.
`.
`1 Watt
`
`.
`
`Stresses above those iisted under III‘-lbsaiuta Maximum
`Raring"may cause permanent damage to the device. This
`is a stress rating om‘? and functional operation of the de-
`vice at these or at any other condition above those indi-
`cated in the operations! sections of this specification is
`not im,oi'ied. Exposure to absolute maximum raring con-
`ditions for ex tended periods may affect device reliabifiry.
`
`
`
`D.C. AND OPERATING CHARACTERISTICS
`
`TA = 0°C 10 70°C. Vcc = 5V 15% , unless otherwise specified.
`
`Symbol
`
`Parameter
`
`Min.
`
`Ty;-.l1l Max.
`
`Unit
`
`Test Conditions
`
`Input Load Current
`V0 Leakage Current
`IIO Leakage Current
`Power Supply
`Current
`P
`5
`I
`0W9’
`“I39 ‘I’
`Current
`
`1
`1
`-1
`35
`
`10
`10
`-‘ID
`55
`
`60
`
`,uA
`{IA
`mA
`
`mA
`
`VW = D to 5.25V
`Output Disabled. V”o=4.UV
`Output Disabled, V”o=lJ.45V
`VIN "' 5-25V
`0
`lug = DmA, TA = 25 C
`V
`= 5.25V
`
`0
`W
`l|,ro=UI'l1A,T,q =0 C
`
`I“
`ILOH
`ILOL
`I331
`I
`
`CC2‘
`
`\i"_
`VH4
`'Vo|_
`
`Von
`
`
`
`Input Low Voltage m
`Input High Voltage
`Vcc
`V
`Output Low Voltage
`0.45
`V
`Output High
`Vohage
`
`2.4
`
`IQL 1' 2.ClrnA
`
`lag = -4DU,[.1A
`
`V
`
`OUTPUT SINK CURRENT VS.
`OUTPUT VOLTAGE
`
`RMBIENY TEMPERATURE -
`
`IZEII
`mail
`
`In[MAI
`
`um lV01‘I'SI
`
`OUTPUT SOURCE CURRENT VS.
`OUTPUT VOLTAGE
`I
`
`l u
`
`m, wousi
`
`NOTE: 1. Typicai values are {or Tp, = 25°C and nominal supply voltage.
`
`?-22
`
`218
`
`218
`
`

`
`A.C. CHARACTERISTICS
`
`B111A—4
`
`Test Conditions
`
`READ CYCLE TA = 0°C to ?0°C, Um; = 5U 35%, unless otherwise specified.
`
`TVA.‘ I
`1
`Mil‘!
`Symbol
`‘
`Parameter
`rm;
`Read Cycle
`45!)
`
`
`IA +Access Time
`
`[559 Belflwl
`
`
`
`1.39
`[OD
`
`
`
`
`
`Chip Enable To Output
`Output Disable To Output
`Data Output to High Z State
`Previous Read Data Valid
`after change of Address
`
`
`
`Parameter
`Write Cycle
`Write Delay
`Chip Enable To Write
`
`
`
`Data Setup
`Data Hold
`
`Tupi.”
`
`Min.
`2?O
`20
`250
`
`250
`n
`250
`
`
`
`Unit
`:19
`ns
`
`ns
`as
`ns
`
`l
`l
`
`Test Conditions
`
`'8" B°‘°“"
`
`
`
`
`-a-——
`Output Disable Setup
`20
`u
`
`[:1]
`CAPACITANCE TA = 25“C,f=1MHz
`
`5lr‘|'"h"-‘ll
`
`_
`C
`I
`(:‘l’I“l‘np:‘:“Ff‘_'r::;““'v‘*l~ = W
`
`HO Capacitance Vhro = 0V
`
`
`
`
`A.C. CONDITIONS OF TEST
`. 20 ns
`.
`.
`.
`tntf
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. . .
`.
`input Levels .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. . . 0.3V or 20V
`
`Timing Reference .
`Load .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`
`1.5V
`.
`.
`.
`.
`.
`. . .
`.
`.
`.
`.
`.
`.
`.
`1 TTL Gate and c._ = we pl:
`
`WAVEFOHMS
`HEAD CYCLE
`
`cm
`ENAELES
`(CH. CE?!
`
`Egg:
`
`I:A1'AI.rcI -__ ------ -_
`
`
`nfafnm
`-_
`
`
`WRITE CYCLE
`——
`
`um: T T _
`
`can
`ELAHI._s_s
`leer '35:‘
`
`oumrr
`DISABLE
`
`DATAIID
`REED!
`
`waits
`
`NOTES: 1. Typical values are for TA I 25°C and nominal supply voltage.
`2.
`rm: is with respect to the trailing edge of CE1, CE2, or OD, whichever occurs first.
`3. This parameter is periodically sampled and is not 100% tefled.
`
`Ti’-23
`
`219
`
`219
`
`

`
`
`
`II"-24II"-24
`
`
`
`220220
`
`220
`
`

`
`5101 FAMILY
`
`256 X 4 BIT STATIC CMOS RAM
`
`PIN
`
`5‘l0'lL
`
`Typ. Current @ 2V Typ. Current @ 5V Max Access
`{FA}
`{PM
`{H9}
`0.1‘!
`0.2
`850
`
`__5101L-‘I
`51 0‘! L-3
`5101-3
`
`0:14
`0.70
`——
`
`1-0
`10.0
`
`_H
`
`450
`650
`000
`
`II Single +511 Power Supply
`
`as Directly Tl'L Compatible:
`
`Operation (51 01 L)
`
`a Three-State Output
`
`The Inte|® 5101 is an ultra-low power 1024-bit (256 words X 4 bits] static HAM fabricated with an advanced ion-implanted
`silicon gate CMOS technology. The device has two chip enable inputs. Minimum standby current is drawn by this device when
`CE? is at a low level. When deseiected the 5101 draws from the single 5—volt supply only 10 microamps. This device is ideally
`suited for low power applications where battery operation or battery backup tor non-volatility are required.
`The 5101 uses fully DC stable istaticl circuitry: it is not nemsarv to pulse chip select for each address transition. The data is read
`out non-destruttivelv and has the same polarity as the input data. All inputs and outputs are directly TTL compatible. The 5101
`has separate data input and data output terminals. An output disable function is provided so that the data inputs and outputs may
`be wire OR-ed for use in common data U0 systems.
`The 51011‘. has the additional’ feature of guaranteed data retention at a power supply voltage as low as 2.0 volts.
`A pin compatible N-channel static HAM. the Intel” 2101A, is also available for low cost applications where a 256K 4 organiza-
`tion is needed.
`
`The Intel ion-implanted. silicon gate. Complementary MOS {CMO8l process allows the design and production of ultra-low power.
`high performance memories.
`
`
`PIN CONFIGURATION
`LOGIC SYMBOL
`
`BLOCK DI AG RAM
`
`.Z"}'..P."..."‘..".*'.”
`
`IZEI. L AH RIY
`12 RDW3
`3! COLUMNS
`
`
`
`
`
`I30
`€0I.Ll'Mlll
`CIRC UITS
`
`
`
`—
`,0‘
`(in. COLUNH
`BL“ SELECT
`BUFFEIIS
`
`
`COLUMN
`
`cu, .
`.,_ _
`
`
`
`Q - am NUMEEIIS
`
`125
`
`221
`
`221
`
`

`
`5101 FAMILY
`
`.1.
`
`.
`.
`Absolute Maximum Ratings
`Ambient Temperature Under Bias .
`.
`.
`.
`.—10°C to 30°C
`.,
`.
`Storage Tempemnfm '
`'
`'
`'
`'
`'
`'
`'
`'
`'
`-B5 C to +150 C
`v°lta_9E 0" An” Pm
`‘ ‘0'3V "3 “CC +0'3V
`'
`'
`Wm‘ Respect "3 Gwund '
`M3*"'|'|'-|"T‘ p0W9l' 5|-IDPIV VONBQE -
`-
`-
`-
`-
`-
`V
`-
`-
`+7-