NVIDIA Corporation (Petitioner)
`v.
`Polaris Innovations Limited (Patent Owner)
`
`Demonstratives
`Case IPR2017-00381
`U.S. Patent No. 7,886,122
`
`Before Hon. Sally C. Medley, Barbara A. Parvis, and William M. Fink,
`Administrative Patent Judges
`
`1
`
`NVIDIA 1022
`NVIDIA v. Polaris
`IPR2017-00381
`
`
`v.
`Polaris Innovations Limited (Patent Owner)
`
`Demonstratives
`Case IPR2017-00381
`U.S. Patent No. 7,886,122
`
`Before Hon. Sally C. Medley, Barbara A. Parvis, and William M. Fink,
`Administrative Patent Judges
`
`1
`
`NVIDIA 1022
`NVIDIA v. Polaris
`IPR2017-00381
`
`
`
`Table of Contents
`
`Topics
`Overview
`
`Instituted Grounds
`The ’122 Patent
`Ground 1 and Disputed Issues
`Overview
`Issue 1: Lee discloses read and write operations
`Issue 2: Lee discloses a memory device with a memory array
`Issue 3: Lee discloses a means for interfacing
`Grounds 3-4 and Disputed Issues
`Overview
`Issue 4: Disclosure of Two External Clocks and STROBE in Lee
`Issue 5: Yoo’s Disclosure of a Read Clock Generated from a Data Clock
`Issue 6: Reasons to Combine Yoo with Lee
`Issue 7: Reasons to Combine Kyung with Lee
`
`Ground 5
`
`Gould Confirms that LP-DDR was known prior to the ’122 Patent
`
`Slide No.
`3
`4
`5
`8
`9
`12
`22
`33
`39
`40
`45
`50
`56
`60
`65
`67
`
`2
`
`
`
`Instituted Grounds
`
`Instituted Grounds
`
`3
`
`
`
`Grounds
`
`Grounds Instituted in Inter Partes Review
`
`Ground Reference(s)
`
`Basis
`
`Lee (US Pat. No. 6,496,445)
`
`§ 102(b)
`
`Lee and Yoo (US Pat. No.
`6,477,110)
`
`§ 103(a)
`
`Lee and Kyung (US Pat. App. Pub.
`No. 2005/0047246)
`
`§ 103(a)
`
`1
`
`3
`
`4
`
`5
`
`Challenged Claims
`
`1, 5, 6, 8, 9, 13, 14,
`16, 20, and 24
`
`2–4, 10–12, 17–19,
`21–23, and 25–28
`
`2, 3, 10, 11, 17, 18,
`21, 22, 25, 26, and
`28
`
`Lee and Gould (US Pat. App. Pub.
`No. 7,571,297)
`
`§ 103(a)
`
`7 and 15
`
`4
`
`
`
`The ’122 Patent
`
`The ’122 Patent
`
`5
`
`
`
`Overview of the ’122 Patent
`
`’122 Patent (NVIDIA-1001) at 1:5, 1:49-65
`
`US 7,886,122 (“the ’122 Patent”)
`
`’122 Patent (NVIDIA-1001) at 2:12-26.
`
`6
`
`
`
`Purported Novelty of the ’122 Patent
`
`’122 Patent – FIG. 4
`
`’122 Patent (NVIDIA-1001) at Fig. 4
`
`’122 Patent Purported Novelty:
`• “A first, low-frequency clock signal for command signals”
`• “A second, high-frequency clock signal for data signals”
`Petition at 2
`
`7
`
`
`
`Ground 1: Lee
`
`Ground 1: Lee
`
`8
`
`
`
`Lee Discloses the Same Two Clocks as the ’122 Patent
`
`Lee – FIG. 6
`
`Lee (NVIDIA-1004)
`Lee Discloses the Purportedly Novel Features of the ’122 Patent
`• Slow clock (“CLK1” in Green) for commands/addresses
`• Fast clock (“CLK2” in Red) for data
`
`- Dr. Jacob Declaration
`(NVIDIA-1003) at ¶¶ 102-105
`
`9
`
`
`
`Lee Discloses the Same Two Clocks as the ’122 Patent
`
`Lee
`
`Lee (NVIDIA-1004) at Fig. 6 (from
`NVIDIA-1003 Jacob Dec at ¶ 106)
`
`Lee (NVIDIA-1004) at 7:18-42
`
`10
`
`
`
`Ground 1 (Anticipation by Lee): Three Issues
`
`•
`
`•
`
`•
`
`Issue 1: Lee discloses read and write operations
`– Applies to all independent claims
`Issue 2: Lee discloses a memory device with a memory array
`– Applies to only independent claim 16
`Issue 3: Lee discloses a means for interfacing
`– Applies to only independent claim 24
`
`11
`
`
`
`Ground 1 (Anticipation by Lee): First Issue
`
`•
`
`•
`
`•
`
`Issue 1: Lee discloses read and write operations
`– Applies to all independent claims
`Issue 2: Lee discloses a memory device with a memory array
`– Applies to only independent claim 16
`Issue 3: Lee discloses a means for interfacing
`– Applies to only independent claim 24
`
`12
`
`
`
`Issue 1: Lee discloses read/write operations
`
`NVIDIA’s Reply
`
`Polaris’s Argument Fails:
`1) Polaris Provides No Evidence
`– Leaves Dr. Jacob’s opinion
`unrebutted
`2) Relies on Overly Narrow Construction
`– Improperly imports “memory
`array” into read/write operations
`3) Polaris’s Construction is Irrelevant
`– Lee discloses read/write
`operations to “a memory array”
`
`Petitioner’s Reply at 2
`
`13
`
`
`
`Issue 1: Dr. Jacob Explained How Lee Discloses
`Read/Write Operations
`
`Dr. Jacob’s Declaration
`
`NVIDIA-1003 at 117
`
`NVIDIA-1003 at 120-121
`
`•
`
`“Lee explicitly discloses that the Data Buffer is used for both data
`input (i.e., write operations) and data output (i.e., read operations).”
`NVIDIA-1003 at 121
`
`14
`
`
`
`Issue 1: Polaris Provides No Evidence to the Contrary
`
`Polaris’s Response
`
`• Polaris lacks evidence that
`DRAM devices do not perform
`read and write operations.
`• Polaris does not cite to Dr.
`Przybylski in countering
`NVIDIA’s argument.
`
`Patent Owner Response at 27-28
`
`15
`
`
`
`Issue 1: Dr. Przybylski Confirmed that Lee’s DRAM
`Memory Devices Perform Read and Write Operations
`
`Dr. Przybylski’s Deposition
`
`“Lee contemplates … DRAM
`semiconductor memory
`devices.”
`(NVIDIA-1012) at 54:12-20
`(emphases added).
`
`(NVIDIA-1012) at 54:12-20
`
`(NVIDIA-1012) at 52:04-10
`
`“SDRAMs perform … column read
`and column write operations.”
`(NVIDIA-1012) at 52:04-10
`(emphases added).
`
`16
`
`
`
`Issue 1: Polaris’s Construction is Overly Narrow
`
`Polaris’s Construction:
`
`Patent Owner’s Response at 22
`
`Polaris’s Construction is Incorrect:
`• Fails Claim Differentiation
`– Renders language from claim 16
`redundant and unnecessary
`• The ’122 Patent Does Not Support
`Importing “Memory Array”
`– The ’122 Patent describes “data
`access” and refers to “memory array”
`as an example
`
`See Petitioner Reply at 3-4
`
`17
`
`
`
`Issue 1: Polaris’s Construction Fails Claim
`Differentiation
`
`’122 Patent – Claim 1
`
`’122 Patent – Claim 16
`
`’122 Patent at Claim 1
`
`’122 Patent at Claim 16
`
`•
`
`“if read and write operations already required a memory array, the
`additional language in claim 16 would be redundant and unnecessary.”
`Petitioner Reply at 3-4
`
`18
`
`
`
`Issue 1: Polaris’s Construction Fails Claim
`Differentiation
`
`Case Law on Claim Differentiation
`
`– AllVoice Computing PLC v. Nuance Communications, Inc., 504 F.3d 1236,
`1247–48 (Fed. Cir. 2007) (internal citations omitted).
`
`– SRI Intern. v. Matsushita Elec. Corp. of America, 775 F.2d 1107, 1122 (Fed. Cir.
`1985) (internal citations omitted).
`
`[Case law cited in Petitioner Reply at 4]
`
`19
`
`
`
`Issue 1: the '122 Patent Specification Does Not Support
`Importing "Memory Array"
`
`NVIDIA’s Reply
`
`’122 Patent
`
`Petitioner Reply at 4-5
`
`’122 Patent at 3:45-53
`
`’122 Patent at 4:16-38
`
`20
`
`
`
`Issue 1: Polaris’s Construction is Irrelevant
`
`NVIDIA’s Reply
`
`Petitioner Reply at 6
`
`21
`
`
`
`Ground 1 (Anticipation by Lee): Second Issue
`
`•
`
`•
`
`•
`
`Issue 1: Lee discloses read and write operations
`– Applies to all independent claims
`Issue 2: Lee discloses a memory device with a memory array
`– Applies to only independent claim 16
`Issue 3: Lee discloses a means for interfacing
`– Applies to only independent claim 24
`
`22
`
`
`
`Issue 2: Lee discloses a memory device
`with a memory array
`
`Petitioner’s Reply at 10
`
`Polaris’s Argument Fails Because:
`• Lee’s Memory Chip Includes a Memory Array
`• Polaris’s Construction of Memory Device is Overly Narrow
`• Lee’s Memory Module is a Memory Device with a Memory Array of Chips
`
`23
`
`
`
`Issue 2: Lee’s Memory Chips are Normal DRAM Chips
`that Include Memory Arrays
`
`Lee
`
`Dr. Jacob
`
`(NVIDIA-1004) at 1:39-45
`
`(NVIDIA-1004) at 1:45-55
`
`See Petition at 38.
`
`(NVIDIA-1003) at ¶ 41
`
`(NVIDIA-1003) at ¶ 153
`
`24
`
`
`
`Issue 2: Lee’s Memory Chips are Normal DRAM Chips
`that Include Memory Arrays
`
`Dr. Jacob’s Declaration
`
`(NVIDIA-1003) at ¶ 24
`
`(NVIDIA-1003) at ¶ 41
`
`25
`
`
`
`Issue 2: Dr. Przybylski Agrees that Lee’s DRAM Chips
`Include Memory Arrays
`
`Dr. Przybylski’s Deposition
`
`(NVIDIA-1012) at 54:12-20
`
`“DRAM semiconductor memory
`devices … were required to
`have DRAM cells.”
`(NVIDIA-1012) at 54:12-20
`(emphases added).
`
`“If there were no DRAM storage
`cells it would not be a DRAM.”
`(NVIDIA-1012) at 27:3-9.
`(emphases added).
`
`(NVIDIA-1012) at 27:3-9
`
`26
`
`
`
`Issue 2: Polaris’s Construction of Memory Device
`is Overly Narrow
`
`Polaris’s Construction
`
`Patent Owner’s Response at 22
`
`Polaris’s Construction Fails:
`– Improperly imports
`limitations missing from
`the ’122 patent
`– At odds with
`contemporaneous
`understanding of the
`term by a POSITA
`– Contrary to case law
`Petitioner’s Reply at 10
`
`27
`
`
`
`Issue 2: The ’122 Patent Broadly Describes the Term
`“Memory Device”
`
`NVIDIA’s Reply
`
`Petitioner’s Reply at 10-13
`
`’122 Patent
`
`’122 Patent (NVIDIA-1001) at 3:48-51.
`
`28
`
`
`
`Issue 2: Evidence Proves a Broad Understanding of the
`Term “Memory Device”
`
`Dr. Jacob
`
`Third Party Evidence
`
`Transcript of Dr. Jacob Deposition at 25:15-19.
`
`Transcript of Dr. Jacob Deposition at 26:1-6.
`
`Pax
`(NVIDIA-1015) at 1:07-13
`
`Geiger
`(NVIDIA-1016) at 13:56-64
`
`29
`
`
`
`Issue 2: Dr. Przybylski’s Own Work Broadly Describes the
`Term "Memory Device"
`
`Dr. Przybylski
`
`Przybylski ’495 Patent (NVIDIA-1017) at 3:03-37
`
`Przybylski ’395 Patent (NVIDIA-1017) at 11:35-40
`
`30
`
`
`
`Issue 2: The Federal Circuit Has
`Already Confirmed Polaris is Incorrect
`
`In Re Rambus
`
`Petitioner Reply at 12., quoting Rambus at 46-47.
`
`In re Rambus, 694 F.3d 42, 46-48 (Fed. Cir. 2012) (Cited in Petitioner Reply at 5)
`
`31
`
`
`
`Issue 2: Lee’s Memory Module is a Memory Device with
`a Memory Array of Chips
`Lee
`
`Dr. Jacob
`
`Lee (NVIDIA-1004) at Fig. 4, as
`annotated in Petitioner Reply at 14.
`
`Transcript of Dr. Jacob
`Deposition at 32:13-22.
`
`Petitioner Reply at 14
`
`32
`
`
`
`Ground 1 (Anticipation by Lee): Third Issue
`
`•
`
`•
`
`•
`
`Issue 1: Lee discloses read and write operations
`– Applies to all independent claims
`Issue 2: Lee discloses a memory device with a memory array
`– Applies to only independent claim 16
`Issue 3: Lee discloses a means for interfacing
`– Applies to only independent claim 24
`
`33
`
`
`
`Issue 3: Lee Discloses a Means for Interfacing
`
`Polaris’s Construction
`
`Polaris’s Construction Fails:
`
`1)
`
`2)
`
`3)
`
`Polaris Provides No
`Evidence
`
`Polaris’s Construction is
`Overly Narrow
`
`Lee Discloses a
`Memory Interface
`
`See Petitioner Reply at 14-16
`
`Patent Owner’s Response at 41
`
`34
`
`
`
`Issue 3: Polaris Provides No Evidence on Construction
`of Means for Interfacing
`
`Polaris’s Response
`
`Dr. Przybylski’s Declaration
`
`(POLARIS-1003) at Table of Contents
`
`Patent Owner Response at Table of Contents
`
`• Polaris argues for a narrow construction of “means for interfacing a
`control device,” yet cites to no evidence for this construction.
`• Polaris’s Expert’s Declaration is devoid of any argument on the
`corresponding structure for the “means for interfacing.”
`See Petitioner Reply at 14-15
`
`35
`
`
`
`Issue 3: Polaris’s Construction Improperly Extends
`Beyond the Claimed Function
`
`’122 Patent – Claim 24
`
`’122 Patent – Claim 25
`
`…
`
`NVIDIA’s Reply
`
`Petitioner Reply at 16
`
`36
`
`
`
`Issue 3: Polaris’s Construction Improperly Includes
`Non-Structural Elements
`
`In Re Nuijten
`
`In re Nuijten, 500 F.3d 1346, 1357 (Fed. Cir. 2007).
`
`NVIDIA’s Reply
`
`Petitioner Reply at 16
`
`37
`
`
`
`Issue 3: Lee Discloses a Memory Interface
`
`Dr. Jacob
`
`NVIDIA-1003 at 102-103
`
`Lee
`
`(NVIDIA-1004) at Fig. 4 (as annotated in Petition at 39)
`38
`
`
`
`Grounds 3 and 4: Lee in view of Yoo or Kyung
`
`39
`
`
`
`Primary Feature Relevant to Grounds 3 and 4
`
`’122 Patent – Claim 10
`
`• Primary Feature Relevant to Grounds 3 and 4
`– “read clock signal” that is “generated from the
`second clock signal”
`– Double Data Rate (DDR) Operation: “separate
`read data are read at rising and falling edges”
`
`40
`
`
`
`Relevant Feature of the ’122 Patent
`
`’122 Patent
`(NVIDIA-1001) at Fig. 1
`
`’122 Patent
`(NVIDIA-1001) at 5:26-36
`
`41
`
`
`
`Relevant Feature of the ’122 Patent
`
`’122 Patent – FIG. 4
`
`’122 Patent
`(NVIDIA-1001) at Fig. 4, as
`annotated in Jacob Declaration
`(NVIDIA-1003) at 67.
`
`•
`
`In the ’122 patent timing diagram, the read clock (RDQS2X)
`has the same frequency as the fast clock (WDQS_RCLK2x).
`
`- Dr. Jacob Declaration
`(NVIDIA-1003) at ¶¶ 96-99
`
`42
`
`
`
`Lee’s Strobe is the Same as the ’122 Patent Read Clock
`
`’122 Patent – FIG. 4
`
`Lee – FIG. 6
`
`(NVIDIA-1001) at Fig. 4, as annotated in
`Jacob Declaration (NVIDIA-1003) at 67.
`
`(NVIDIA-1004) at Fig. 6, as annotated in
`Petitioner Reply at 21.
`
`43
`
`
`
`Grounds 3 and 4 – Four Issues
`
`•
`•
`
`•
`•
`
`Issue 4: Disclosure of Two External Clocks and STROBE in Lee
`Issue 5: Yoo’s Disclosure of a Read Clock Generated from a Data
`Clock
`Issue 6: Reasons to Combine Yoo with Lee
`Issue 7: Reasons to Combine Kyung with Lee
`
`44
`
`
`
`Grounds 3 and 4: Fourth Issue
`
`•
`•
`
`•
`•
`
`Issue 4: Disclosure of Two External Clocks and STROBE in Lee
`Issue 5: Yoo’s Disclosure of a Read Clock Generated from a Data
`Clock
`Issue 6: Reasons to Combine Yoo with Lee
`Issue 7: Reasons to Combine Kyung with Lee
`
`45
`
`
`
`Issue 4: Disclosure of Two External Clocks and
`STROBE in Lee
`
`Polaris’s Response
`
`Patent Owner Response at 2-3
`
`46
`
`
`
`Issue 4: Disclosure of Two External Clocks and
`STROBE in Lee
`
`Lee – FIG. 6
`
`(NVIDIA-1004) at Fig. 6, as annotated
`in Petitioner Reply at 21.
`
`47
`
`
`
`Issue 4: Disclosure of Two External Clocks and
`STROBE in Lee
`
`Lee – Explicit Disclosure of STROBE in Second Embodiment
`
`(NVIDIA-1004) at 7:36-41.
`
`Petitioner Reply
`at 20.
`
`48
`
`(NVIDIA-1004) at Fig. 6, as annotated
`in Petitioner Reply at 21.
`
`
`
`Issue 4: Disclosure of Two External Clocks and
`STROBE in Lee
`
`Lee – Claims 16-18
`
`“16….a first clock signal, a
`second clock signal having a
`frequency which is greater
`than that of the first clock
`signal…a data buffer which
`inputs/outputs data at a timing
`of the second clock signal.
`
`8. The semiconductor
`memory system according to
`claim 16, wherein the data
`buffer receives a data strobe
`signal and inputs/outputs the
`data at every rising and falling
`edge of the data strobe signal.”
`
`…1
`
`(NVIDIA-1004) at Claims 16, 18 (11:32-53)
`
`49
`
`
`
`Grounds 3 and 4: Fifth Issue
`
`•
`•
`
`•
`•
`
`Issue 4: Disclosure of CLK2 and STROBE in Lee
`Issue 5: Yoo’s Disclosure of a Read Clock Generated from a Data
`Clock
`Issue 6: Reasons to Combine Yoo with Lee
`Issue 7: Reasons to Combine Kyung with Lee
`
`50
`
`
`
`Issue 5: Similarity of Yoo’s STROBE Generation Circuit
`to the ’122 Patent’s OCD 126
`
`Yoo – FIG. 7
`
`’122 Patent – FIG. 1
`
`Yoo (NVIDIA-1006) at Fig. 7 (annotated)
`
`’122 Patent (NVIDIA-1001) at Fig. 1 (annotated)
`
`51
`
`
`
`Issue 5: Yoo’s int-CLK-RD is Required to Generate
`STROBE Output
`Dr. Jacob
`
`Dr. Jacob Reply Declaration (NVIDIA-1011) at ¶¶ 15, 17
`
`52
`
`
`
`Issue 5: Yoo’s int-CLK-RD is Required to Generate
`STROBE Output
`
`Dr. Przybylski
`
`Transcript of Dr. Przybylski Deposition (NVIDIA-1012) at 60:23-64:20
`
`53
`
`
`
`Issue 5: Synchronization of STROBE Generated From
`int-CLK-RD
`
`Dr. Jacob
`
`Yoo – FIG. 7
`
`Dr. Jacob Reply Declaration (NVIDIA-1011) at ¶¶ 25-29.
`
`Yoo (NVIDIA-1006) at Fig. 7, as annotated in
`Jacob Declaration at 150.
`
`Dr. Jacob Reply Declaration (NVIDIA-1011) at ¶ 16.
`
`54
`
`
`
`Issue 5: Synchronization of STROBE Generated From
`int-CLK-RD
`
`Dr. Pryzyblski Declaration
`
`(POLARIS-1003) at ¶ 83
`
`55
`
`
`
`Grounds 3 and 4: Sixth Issue
`
`•
`•
`
`•
`•
`
`Issue 4: Disclosure of CLK2 and STROBE in Lee
`Issue 5: Yoo’s Disclosure of a Read Clock Generated from a Data
`Clock
`Issue 6: Reasons to Combine Yoo with Lee
`Issue 7: Reasons to Combine Kyung with Lee
`
`56
`
`
`
`Issue 6: Reasons to Combine Yoo with Lee
`
`Yoo – FIG. 7
`
`NVIDIA’s Petition
`
`Petition at 74
`
`Petition at 74
`
`57
`
`Yoo (NVIDIA-1006) at Fig. 7, as
`annotated in Jacob Declaration at 150.
`
`
`
`Issue 6: Reasons to Combine Yoo with Lee
`
`Yoo – FIG. 7
`
`NVIDIA’s Reply
`
`Petitioner Reply at 22
`
`Yoo (NVIDIA-1006) at Fig. 7, as annotated
`in Jacob Declaration at 150.
`
`58
`
`
`
`Issue 6: Reasons to Combine Yoo with Lee
`
`NVIDIA’s Petition
`
`Yoo
`
`Petition at 74
`
`Yoo (NVIDIA-1006) at Abstract
`
`59
`
`
`
`Grounds 3 and 4: Seventh Issue
`
`•
`•
`
`•
`•
`
`Issue 4: Disclosure of CLK2 and STROBE in Lee
`Issue 5: Yoo’s Disclosure of a Read Clock Generated from a Data
`Clock
`Issue 6: Reasons to Combine Yoo with Lee
`Issue 7: Reasons to Combine Kyung with Lee
`
`60
`
`
`
`Issue 7: Reasons to Combine Kyung with Lee
`
`NVIDIA’s Reply
`
`Petitioner Reply at 26
`
`61
`
`
`
`Issue 7: Reasons to Combine Kyung with Lee
`
`NVIDIA’s Reply
`
`Kyung – FIG. 6
`
`Petitioner Reply at 27
`
`Kyung (NVIDIA-1005) at Fig. 6, as
`annotated in Petition at 87.
`
`62
`
`
`
`Issue 7: Reasons to Combine Kyung with Lee
`
`NVIDIA’s Petition
`
`Kyung (NVIDIA-1005) at Fig. 7, as annotated in Petition at 88-89
`
`Petition at 89
`
`63
`
`
`
`Issue 7: Reasons to Combine Kyung with Lee
`
`NVIDIA’s Petition
`
`Kyung (NVIDIA-1005) at Fig. 7, as annotated in Petition at 88-89
`
`Petition at 89-90.
`
`64
`
`
`
`Ground 5: Lee in view Gould
`
`65
`
`
`
`Primary Feature Relevant to Ground 5
`
`’122 Patent
`
`NVIDIA-1001 at Claim 15 (8:61-63)
`
`NVIDIA-1001 at 3:48-59
`
`NVIDIA-1001 at 3:60-65
`
`Primary Feature Relevant to Grounds 3 and 4:
`– “The memory device may be…a low-power type (LP-DDR)
`memory device as specified by the Joint Electron Device
`Engineering Council (JEDEC) LP-DDR synchronous
`dynamic random access memory (SDRAM) Specification”
`
`66
`
`
`
`Ground 5: Gould Confirms that LP-DDR was known
`prior to the ’122 Patent
`
`Gould
`
`NVIDIA-1007 3:1-6
`
`“Lee uses double-data rate memory…Gould confirms that low-power double-
`data rate (LPDDR) memory was known prior to the ’122 patent and provides
`motivation to use LPDDR as the double-data rate memory in Lee’s system.”
`- Petition at 95
`
`67
`
`
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