Trials@uspto.gov Paper No. 38
`571.272.7822 Entered: June 19, 2018
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`____________
`
`Case IPR2017-00381
`Patent 7,886,122 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`MONICA S. ULLAGADDI, Administrative Patent Judges.
`
`PARVIS, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`I. INTRODUCTION
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73.
`The evidentiary standard is a preponderance of the evidence. See 35 U.S.C.
`§ 316(e); 37 C.F.R. § 42.1(d). For the reasons that follow, we determine that
`NVIDIA Corporation (“Petitioner”) has shown by a preponderance of the
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`evidence that claims 1–23 and 28 of U.S. Patent No. 7,886,122 B2 (Ex.
`1001, “the ’122 Patent”) are unpatentable. Petitioner has not shown by a
`preponderance of the evidence that claims 24–27 of the ’122 Patent are
`unpatentable.
`
`Background
`A.
`Petitioner filed a Petition for inter partes review of claims 1–28 (“the
`challenged claims”) of the ’122 Patent. Paper 2 (“Pet.”). Polaris
`Innovations Limited (“Patent Owner”) filed a Preliminary Response. Paper
`7 (“Prelim. Resp.”). Pursuant to 35 U.S.C. § 314, we instituted trial on all
`challenged claims, but not on all challenged grounds. See Paper 9 (Inst.
`Dec.”), 26–27.1
`After institution of trial, Patent Owner filed a Patent Owner Response
`(Paper 18, “PO Resp.”), to which Petitioner filed a Reply (Paper 21, “Pet.
`Reply”). Patent Owner filed a Motion for Observation, Paper 25 (“PO Mot.
`Obs.”) and Petitioner filed a Response to the Motion for Observation, Paper
`29 (“Pet. Resp.”). A transcript of the hearing held on March 8, 2018 has
`been entered into the record as Paper 32 (“Tr.”).
`Following the hearing, on April 24, 2018, the Supreme Court held that
`a decision to institute under 35 U.S.C. § 314 may not institute on less than
`all claims challenged in the petition. SAS Inst., Inc. v. Iancu, 138 S. Ct.
`1348, 1359–60 (2018). In light of the Guidance on the impact of SAS on
`AIA trial proceedings posted on April 26, 2018 (at
`
`
`1 Patent Owner filed a Request for Rehearing of the Decision to Institute
`(Paper 12, “Reh’g Req.”), which we denied (Paper 15, “Dec. on Reh’g
`Req.”).
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`Patent 7,886,122 B2
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`https://www.uspto.gov/patents-application-process/patent-trial-and-appeal-
`board/trials/guidance-impact-sas-aia-trial), we modified our Institution
`Decision to institute on all the challenged claims and all the grounds
`presented in the IPR2017-00381 Petition (Paper 2). See Paper 35 (“DI
`Supp.”). We also granted the parties’ joint request for additional briefing.
`Id. On May 18, 2018, Patent Owner filed a supplemental brief pertaining to
`only the previously non-instituted ground (Paper 36, “PO Supp. Br.”) and on
`May 25, 2018, Petitioner filed a supplemental brief responsive to Patent
`Owner’s submission (Paper 37, “Pet. Supp. Br.”).
`
`Related Matters
`B.
`The parties state that the ’122 Patent is the subject of a pending
`lawsuit that includes assertions against Petitioner. Pet. 100; Paper 4
`(“PATENT OWNER’S INITIAL MANDATORY NOTICES”) (hereinafter “PO Init.
`Mand. Not.”), 2–3; Paper 23 (“PETITIONER’S UPDATED MANDATORY
`NOTICES”) (hereinafter “Pet. Updated Mand. Not.”), 2. The parties identify
`a lawsuit pending in the Northern District of California, i.e., Polaris
`Innovations Ltd. v. Dell Inc., Case No. 4:16–cv-07005 (N.D. Cal.).2 PO Init.
`Mand. Not. 2–3; Pet. Updated Mand. Not. 2.
`
`
`2 This lawsuit is referred to herein as the “companion district court lawsuit.”
`The companion district court lawsuit was transferred from the United States
`District Court for the Western District of Texas on December 5, 2016. Id.
`That case was Polaris Innovations Ltd. v. Dell Inc., Case No. 5:16–cv-00451
`(W.D. Tex). Id.
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`Patent 7,886,122 B2
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`B. The ’122 Patent
`The ʼ122 Patent is directed to clock signals used in memory devices.
`Ex. 1001, 1:8–10. Figure 1 of the ’122 Patent is reproduced below.
`
`
`
`Figure 1 of the ’122 Patent, reproduced above, illustrates a block diagram of
`system 100 having memory device 110 and control device 102, as well as
`interface 150 between control device 102 and memory device 110. Id. at
`3:37–43.
`Control device 102 provides first clock signal (CLK1x), second clock
`signal (WDQS_RCLK2x), command and address signals
`(COMMAND/ADDRESS), and write data signal (DQ(WRITE)) to memory
`device 110. Id. at 3:64–4:4. Memory device 110 provides read clock signal
`(RDQS2x) and read data signal (DQ(READ)) to control device 102. Id. at
`4:5–6.
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`C. Illustrative Claim
`Petitioner challenges claims 1–28 of the ’122 Patent. Pet. 1. Claims
`1, 9, 16, 20, 24, and 28 are independent claims. Claims 2–8, 10–15, 17–19,
`21–23, and 25–27 depend, directly or indirectly, from claims 1, 9, 16, 20, or
`24. Independent claim 1, reproduced below, is illustrative of the claimed
`subject matter:
`1. A method for transmitting clock signals, the method
`comprising:
`receiving, at a memory device, a first clock signal and a second
`clock signal, wherein a frequency of the first clock signal is
`less than a frequency of the second clock signal;
`performing two or more data access operations using the second
`clock signal, wherein at least one of the two or more data
`access operations includes a read operation and wherein at
`least one of the two or more data access operations includes a
`write operation; and
`performing a command processing operation using the first clock
`signal.
`Id. at 7:55–67.
`
`D. Instituted Grounds of Unpatentability
`Petitioner asserts the following grounds of unpatentability (Pet. 1–2):
`Reference(s)
`Basis
`Challenged Claim(s)
`Lee3
`§ 102(b)
`1, 5, 6, 8, 9, 13, 14, 16, 20, and 24
`Lee
`§ 103(a)
`2–4, 10–12, 17–19, 21–23, and 25–28
`Lee and Yoo4
`§ 103(a)
`2–4, 10–12, 17–19, 21–23, and 25–28
`
`
`3 U.S. Patent No. 6,496,445 B2, issued Dec. 17, 2002 (Ex. 1004) (“Lee”).
`4 U.S. Patent No. 6,477,110 B2, issued Nov. 5, 2002 (Ex. 1006) (“Yoo”).
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`Challenged Claim(s)
`Basis
`Reference(s)
`2, 3, 10, 11, 17, 18, 21, 22, 25, 26, and 28
`Lee and Kyung5 § 103(a)
`7 and 15
`Lee and Gould6 § 103(a)
`Petitioner offers Declarations of Bruce Jacob, Ph.D. (Ex. 1003; Ex.
`1011). Patent Owner offers a Declaration of Steven A. Przybylski, Ph.D.
`(Ex. 2003). We initially instituted on all challenged claims and modified our
`initial Institution Decision to subsequently include all grounds presented in
`the Petition. Inst. Dec. 26–27; DI Supp. 2–3.
`
`II. DISCUSSION
`Claim Construction
`A.
`In the Petition, Petitioner provides proposed claim constructions for
`“means for storing data” and “means for interfacing a control device” recited
`in claim 24. Pet. 11–13. Petitioner contends, “[a]ll remaining terms should
`be given their broadest reasonable ordinary meaning.” Id. at 11.
`Patent Owner argues: (1) “[r]ather than stretching the meaning of the
`phrase ‘memory device’ to encompass a memory module or board,” the term
`should be interpreted “to mean a memory integrated circuit” (PO Resp. 20);
`and (2) “the phrases ‘read operation’ and ‘write operation’ should be
`interpreted as getting data from and placing data in, respectively, a memory
`array” (id. at 25). Patent Owner also contends that it does not dispute
`Petitioner’s contentions regarding the means-plus-function limitations
`
`
`5 U.S. Patent Application Publication No. 2005/0047246 A1, published Mar.
`3, 2005 (Ex. 1005) (“Kyung”).
`6 U.S. Patent No. 7,571,297 B2, issued Aug. 4, 2009, filed Dec. 30, 2005
`(Ex. 1007) (“Gould”).
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`recited in claim 24, because the Petition does not show that Lee discloses the
`“means for interfacing a control device” recited in claim 24 “as the petition
`has interpreted that limitation.” Id. at 22. In its Reply, Petitioner responds
`to Patent Owner’s contentions regarding the meanings of the terms “memory
`device” and “read” and “write” operations. Pet. Reply 3–14. Below, we
`address the parties’ disputes regarding the meanings of the terms “memory
`device,” “read operation,” and “write operation,” as well as Petitioner’s
`contentions for “means for interfacing a control device” recited in claim 24.
`
`Principles of Law
`1.
`Only those terms that are in controversy need to be construed, and
`only to the extent necessary to resolve the controversy. Vivid Techs., Inc. v.
`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). A claim in an
`unexpired patent that will not expire before a final written decision is issued
`shall be given its broadest reasonable construction in light of the
`specification of the patent in which it appears. See 37 C.F.R. § 42.100.7 We
`interpret the claim terms of the ’122 Patent according to their ordinary and
`customary meaning in the context of the patent’s written description. See In
`re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). An
`inventor is entitled to be his or her own lexicographer of patent claim terms
`by providing a definition of the term in the specification with reasonable
`clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480
`(Fed. Cir. 1994).
`
`7 We further note that our determinations regarding claim construction in the
`instant proceeding are the same under a district court-type claim
`construction approach.
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`Limitations with the language “means” or “means for” are presumed
`to invoke 35 U.S.C. § 112 ¶ 6.8 See Williamson v. Citrix Online, LLC, 792
`F.3d 1339, 1348–49 (Fed. Cir. 2015) (en banc in relevant part) (“use of the
`word ‘means’ [in a claim element] creates a presumption that § 112, ¶ 6
`applies”); see also In re Donaldson Co., Inc., 16 F.3d 1189, 1193 (Fed. Cir.
`1994) (“[P]aragraph six applies regardless of the context in which the
`interpretation of means-plus-function language arises, i.e., whether as part of
`a patentability determination in the PTO or as part of a validity or
`infringement determination in a court”). The sixth paragraph of 35 U.S.C.
`§ 112 provides that “[a]n element in a claim for a combination may be
`expressed as a means or step for performing a specified function without the
`recital of structure, material, or acts in support thereof, and such claim shall
`be construed to cover the corresponding structure, material, or acts described
`in the specification and equivalents thereof.” Where a challenged claim
`contains a means-plus-function limitation under 35 U.S.C. § 112, sixth
`paragraph, the Petitioner “must identify the specific portions of the
`specification that describe the structure, material, or acts corresponding to
`each claimed function.” 37 C.F.R. § 42.104(b)(3).
`
`
`8 Section 4(c) of the Leahy-Smith America Invents Act, Pub. L. No. 112–29,
`125 Stat. 284 (2011) (“AIA”) re-designated 35 U.S.C. § 112 ¶ 6, as
`35 U.S.C. § 112(f). Because the ’122 Patent has a filing date before
`September 16, 2012, the effective date of § 4(c) of the AIA, we will refer to
`the pre-AIA version of 35 U.S.C. § 112.
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`2.
`
` “memory device,” “read operation,” and “write operation”
`(Independent Claims 1, 9, 16, 20, 24, and 28)
`We turn to Patent Owner’s contentions regarding “memory device,”
`“read operation,” and “write operation,” recited in the independent claims.
`Starting with the term “memory device,” Patent Owner contends that
`“‘memory device’ in the memory art is a memory integrated circuit (IC),”
`which also is “referred to in the art as a ‘chip.’” PO Resp. 15. Based on the
`entire trial record we can accept Patent Owner’s proposed construction that
`“memory device” means a “memory integrated circuit (IC)” or a memory
`“chip” (id.) because we are persuaded by Petitioner’s contentions, even
`under Patent Owner’s proposed construction. See Vivid Techs., 200 F.3d at
`803 (Fed. Cir. 1999) (“[O]nly those [claim] terms need be construed that are
`in controversy, and only to the extent necessary to resolve the controversy”).
`More specifically, in its analysis of the asserted prior art discussed
`infra in Section II.D.2, Petitioner points to a memory device that is the same
`as the example in the ’122 Patent, i.e., a dynamic random access memory
`(DRAM), as well as disclosure that this device is a memory chip. Pet. 14–
`16, 19–22, 24, 38, 40–43, 49 (citing, e.g., Ex. 1003 ¶¶ 103, 136–139, 148–
`172; Ex. 1004, 3:38–52, 6:41–67, 7:27–35, 8:59–62, Figs. 4, 5). The ’122
`Patent describes that “memory device 110 may also include any type of
`memory device . . . [f]or example, in one embodiment, the memory device
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`may be a volatile memory device such as a dynamic, random access memory
`(DRAM) device.” Ex. 1001, 3:50–59 (emphasis added).9
`We now turn to the meaning of the terms “read operation” and “write
`operation.” Neither party contends that these terms have any special
`meaning or that the ’122 Patent provides a lexicographical definition of the
`terms. Indeed, Patent Owner contends its proposed construction is dictated
`by the understanding of those skilled in the memory art, relying on the
`testimony of Dr. Przybylski. PO Resp. 25–26. In particular, Dr. Przybylski
`testifies that “the LP DDR SDRAM standard” describes a “write operation
`as comprising the flow of data into the memory array” and “[t]he same
`applies to read operations.” Id. (citing Ex. 2003 ¶¶ 46–48). Dr. Przybylski
`also testifies that this standard provides further details regarding
`“transferring data to/from the memory array, an active row, or one of the
`banks in the memory array” and “the prior art DDR SDRAM JEDEC
`standard contains similar references.” Ex. 2003 ¶ 48.
`Patent Owner’s proposed construction is that “read operation” and
`“write operation” mean “accessing data from a memory array” and “placing
`
`
`9 Although we do not need to reach Patent Owner’s argument that the
`“memory device” is a single integrated circuit or chip, we note that we are
`persuaded by Petitioner’s contention that Patent Owner’s construction is too
`narrow in view of the ’122 Patent’s description that “memory device 110
`may also include any type of memory device.” Ex. 1001, 3:50–59 (emphasis
`added). Patent Owner relies on extrinsic evidence (e.g., Lee and Kyung), as
`well as the ’122 Patent’s mention of DRAM IC standards, which allow the
`“memory device” at least to comprise multiple DRAMs or chips. PO Resp.
`14–20. Contrary to Patent Owner’s contention (id. at 16 n.1), we need not
`determine if system board 400 is a “memory device” because Petitioner’s
`alternate contention pertains to Lee’s memory module 420 comprising
`multiple DRAMs.
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`data in a memory array,” respectively. PO Resp. 22; see also id. at 25
`(“[T]he phrases ‘read operation’ and ‘write operation’ should be interpreted
`as getting data from and placing data in, respectively, a memory array.”)
`Independent claims 1, 9, 20, and 28 recite “memory device,” but not
`“memory array.” Patent Owner directs us to the ’122 Patent Specification,
`explaining that “[c]laims are not interpreted in a vacuum, but are part of and
`read in light of the specification.” PO Resp. 23–25 (quoting Slimfold Mfg.
`Co. v. Kinkead Indus., Inc., 810 F.2d 1113, 1116 (Fed. Cir. 1987)). Patent
`Owner, however, does not explain why we should import “memory array”
`into claims 1, 9, 20, and 28, which recite “memory device,” but not
`“memory array.” As explained above, for the patentability determinations
`before us, we can accept Patent Owner’s proposed construction for “memory
`device,” because Petitioner’s showing is sufficient even under Patent
`Owner’s construction. In particular, Petitioner points to a dynamic random
`access memory (DRAM) device in its analysis of the asserted prior art
`discussed infra in Section II.D.2, which is the same as an example in the
`’122 Patent Specification.
`Patent Owner also contends that, “[a] ‘read operation’ or ‘write
`operation’ includes more than just data transfers onto or off of the memory
`device” because “a ‘memory device’ of the kind referred to in the claims—
`an IC that accepts data, addresses, and commands and is the subject of ‘read
`operations’ and ‘write operations’—stores the data at specific locations in a
`memory array and retrieves data from specific locations in the memory
`array.” PO Resp. 23. That those skilled in the memory art would have
`known that certain memory devices operated in a manner set forth in prior
`art standards documents, for example, “the LP DDR SDRAM standard” and
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`“the prior art DDR SDRAM JEDEC standard” (Ex. 2003 ¶¶ 46–48) does
`not mean that a person having ordinary skill in the art would have
`understood the terms “read operation” and “write operation” to require that
`operation.10
`We, instead, agree with Petitioner that Patent Owner’s proposed
`constructions for terms “read operation” and “write operation” “improperly
`inject ‘a memory array’ into the claimed operations.” Pet. Reply 3.
`Accordingly, we determine that “read operation” and “write operation”
`mean “getting data from” and “placing data in,” respectively, a memory
`device.
`
`3.
`
`“means for interfacing a control device” (Independent Claim 24)
`Petitioner contends that the “means for interfacing a control device”
`recited in claim 24 “is governed by 35 U.S.C. § 112 ¶ 6.” Pet. 12. Petitioner
`contends:
`
`Here, the recited function is “interfacing a control device.”
`The corresponding structure for performing the function
`“interfacing a control device” is “memory interface 150,” which
`is depicted in FIG. 1 “between the control device 102 and the
`memory device 110.” NVIDIA-1001, 3:41–64. As shown in
`FIG. 1, “the control device 102 may communicate to the memory
`device 110 across a memory interface 150.” NVIDIA-1001,
`3:60–61.
`Pet. 13.
`Petitioner, additionally, provides annotations to Figure 1 of the ’122
`Patent highlighting interface 150 in yellow.
`
`
`10 The Petition need not specify where the asserted reference discloses
`details set forth in prior art DRAM standards, just because the specification
`describes DRAM memory as exemplary.
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`Figure 1 of the ’122 Patent, reproduced above with Petitioner’s annotations,
`is a block diagram depicting system 100 that includes memory device 110,
`highlighted in blue, control device 102, highlighted in green, and interface
`150, highlighted in yellow, between control device 102 and memory device
`110. Pet. 13; Ex. 1001, 2:39–41, 3:37–43, Fig. 1.
`Relying on the testimony of Dr. Jacob, Petitioner also contends
`“[t]hus, ‘means for interfacing a control device’ should be construed to
`require the function of ‘interfacing a control device’ performed by the
`structure of ‘a memory interface.’” Id. (citing Ex. 1003 ¶ 26). Dr. Jacob
`testifies that the “corresponding structure for performing the function
`‘interfacing a control device’ is the interface 150, depicted in the ’122
`[P]atent in Fig. 1.” Ex. 1003 ¶ 26.
`Patent Owner contends it does not dispute Petitioner’s identification,
`but instead disputes that Petitioner shows, with respect to claim 24, the prior
`art teaches the limitation as Petitioner has construed it. See PO Resp. 22.
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`In its Reply, Petitioner contends “Polaris misinterprets NVIDIA’s
`construction as requiring all signals (including RDQS2x) shown in FIG. 1 of
`the ’122 Patent.” Pet. Reply 14. Petitioner contends that it “identifies the
`structure of a memory interface, which does not include the intangible
`signals exchanged through that interface,” “the RDQS2x signal is not a
`‘structural element,’” and further that “the RDQS2x signal is not required to
`perform the corresponding function.” Id. at 15–16. Petitioner also contends
`that requiring “the RDQS2x signal would make dependent claim 25 entirely
`redundant.” Id. at 16. During the hearing, Petitioner argued that its
`proposed construction does “not necessarily limit[] [the structure] to
`memory interface 150.” Tr. 9:6–15.
`An element in a claim for a combination may be expressed as a
`means or step for performing a specified function without the
`recital of structure, material, or acts in support thereof, and such
`claim shall be construed to cover the corresponding structure,
`material, or acts described in the specification and equivalents
`thereof.
`35 U.S.C. § 112, ¶ 6 (emphasis added). The only structure described in the
`specification identified by Petitioner in the Petition is memory interface 150.
`Pet. 12–13. Petitioner’s single sentence referring to “the structure of ‘a
`memory interface’” (id. at 13 (citing Ex. 1003 ¶ 26)) does not identify with
`sufficient specificity structure in the ’122 Patent Specification. Petitioner
`cites to only Dr. Jacob’s testimony and Dr. Jacob testifies that the
`“corresponding structure for performing the function ‘interfacing a control
`device’ is the interface 150, depicted in the ’122 [P]atent in Fig. 1.” Ex.
`1003 ¶ 26. We need not make a determination regarding Petitioner’s
`assertion that the RDQS2x signal is intangible and not a structural element
`(Pet. Reply 14–16) because the ’122 Patent Specification describes structure
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`with respect to the memory interface 150 that is not accounted for by
`Petitioner. In particular, the ’122 Patent Specification describes that the off-
`chip driver (OCD) 126 transmits this data over a line to control device 102
`(see, e.g., Ex. 1001, 4:35–38, 5:33–36, Fig. 1). Although the ’122 Patent
`Specification refers to “single data bus line (DQ)” embodiments, the ’122
`Patent Specification does not indicate that these are illustrated in Figure 1 or
`that they are equivalent to interface 150 and, instead, describes these
`embodiments as more limited in that read and write operations cannot be
`performed simultaneously. Ex. 1001, 4:7–12.
`We agree with Petitioner’s identification of the recited function, i.e.,
`“interfacing a control device” and corresponding structure for performing
`the function, i.e., “memory interface 150,” which is depicted in FIG. 1
`“between the control device 102 and the memory device 110.” Pet. 13.
`Patent Owner does not dispute those contentions. PO Resp. 22. We,
`however, are not persuaded that the corresponding structure described in the
`’122 Patent Specification may be something other than memory interface
`150, as Petitioner has not identified that other structure with sufficient
`specificity in the Petition.
`Accordingly, we determine that the recited function of “means for
`interfacing a control device” is “interfacing a control device” and the
`corresponding structure for performing the function is “memory interface
`150,” which is depicted in FIG. 1 “between the control device 102 and the
`memory device 110.”
`
`Principles of Law (Anticipation and Obviousness)
`B.
`Anticipation, under 35 U.S.C. § 102, requires a lack of novelty.
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
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`2001). To establish anticipation, each and every element in a claim,
`arranged as is recited in the claim, must be found in a single prior art
`reference. Id.
`Additionally, a patent claim is unpatentable if the differences between
`the claimed subject matter and the prior art are such that the subject matter,
`as a whole, would have been obvious at the time the invention was made to a
`person having ordinary skill in the art to which said subject matter pertains.
`35 U.S.C. § 103(a). The question of obviousness is resolved on the basis of
`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of skill in the art; and (4) objective evidence of
`nonobviousness, i.e., secondary considerations. See Graham v. John Deere
`Co., 383 U.S. 1, 17–18 (1966). In that regard, an obviousness analysis
`“need not seek out precise teachings directed to the specific subject matter of
`the challenged claim, for a court can take account of the inferences and
`creative steps that a person of ordinary skill in the art would employ.” See
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
`
`Person of Ordinary Skill in the Art
`C.
`Petitioner proposes that a person of ordinary skill in the art would
`have had an undergraduate degree in Electrical Engineering or an equivalent
`subject and either (1) two or three years of post-graduate work designing
`computer memory systems, including one or two years designing double
`data rate DRAM memory systems or (2) a Master’s degree in Electrical
`Engineering (or equivalent subject) and one or two years of post-graduate
`experience designing computer memory systems, including double data rate
`DRAM memory systems. Ex. 1003 ¶¶ 27–28, cited, e.g., in Pet. 55, 58, 60.
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`Patent Owner does not dispute Petitioner’s proposal. See generally PO
`Resp. We adopt Petitioner’s definition.
`
`Anticipation by Lee (Claims 1, 5, 6, 8, 9, 13, 14, 16, 20, and 24)
`D.
`Petitioner contends each of claims 1, 5, 6, 8, 9, 13, 14, 16, 20, and 24
`is anticipated by Lee. Pet. 14–52.
`
`Overview of Lee
`1.
`Lee is directed to a semiconductor memory device that receives
`address and command signals in synchronization with a first clock signal
`and that inputs and outputs data in synchronization with a second clock
`signal. Ex. 1004, 3:43–52. Lee describes that the frequency of the first
`clock signal is lower than that of the second clock signal. Id. at 4:64–66.
`Figure 4 of Lee is reproduced below.
`
`Figure 4 of Lee, reproduced above, illustrates system board 400, which
`includes memory module 420 having memory chips 401 through 408. Id. at
`6:46–50. As shown in Figure 4 above, each of memory chips 401 through
`408 is connected to clock1 bus, clock2 bus, address bus, command bus, and
`data bus. Id. at 6:62–64.
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`Memory chip 401 within memory module 420 is illustrated in more
`detail in Figure 5, which is reproduced below.
`
`
`Figure 5 of Lee, reproduced above, illustrates a block diagram of memory
`chip 401 and its connections to bus lines. Id. at 4:62–67, 5:18–19.
`Memory chip 401, shown in Figure 5 above, includes address buffer
`520 and command buffer 530 that receive address signals and command
`signals, respectively. Id. at 7:2–6. Address buffer 520 and command buffer
`530 also receive the first clock signal (CLK1) and process address and
`command signals in synchronization with the first clock signal (CLK1). Id.
`at 7:4–12. Memory chip 401 also includes data buffer 540, which has a bi-
`directional connection to the data bus and receives the second clock signal
`(CLK2). Id. at 7:7–9. Lee describes that the first clock signal (CLK1) has a
`lower frequency than the second clock signal (CLK2). Id. at 7:12–14.
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`Discussion of Independent Claim 1
`2.
`We begin our analysis with independent claim 1. Claim 1 is directed
`to a method of transmitting signals comprising receiving at a memory device
`first and second clock signals, wherein the frequency of the first clock signal
`is less than the second clock signal, performing a data read operation and a
`data write operation using the second clock signal, and performing a
`command processing operation using the first clock signal. Ex. 1001, 7:55–
`67. Petitioner, for example, points to Figures 4 and 5 of Lee discussed in the
`summary above, as well as Figure 6 of Lee and related description, and
`relies on the testimony of Dr. Jacob. Pet. 14–22 (citing, e.g., Ex. 1004, (57),
`2:20–24, 2:47–50, 3:38–61, 4:62–67, 6:46–7:42, 8:7–14, 9:53–60, 11:31–
`12:12, Fig. 4–6; Ex. 1003 ¶¶ 102, 103, 105, 107, 135–147, 162–172, 179–
`182).
`We find that Lee’s disclosure is consistent with Petitioner’s
`contentions and Dr. Jacob’s testimony. Id. For instance, Lee describes
`memory chip 401 having address buffer 520 and command buffer 530 that
`receive and use the first clock signal (CLK1) and data buffer 540 that
`receives and uses the second clock signal (CLK2). See, e.g., Ex. 1004,
`3:38–61, 7:1–12, 11:31–12:12, Figs. 5, 6. Additionally, Lee describes that
`the first clock signal (CLK1) has a lower frequency than the second clock
`signal (CLK2). See, e.g., id. at 4:63–67, 7:12–14, 11:31–12:12, Fig. 6.
`Patent Owner asserts that Lee does not anticipate claim 1 because Lee
`does not disclose “getting data from a memory array” or “placing data in an
`address-specified location in a memory array,” and further “never uses the
`terms ‘read,’ ‘read operation,’ ‘write,’ or ‘write operation.’” PO Resp. 27–
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`29. Patent Owner’s assertion is premised on its proposed claim
`constructions. Id.
`As we discussed supra in Section II.A.2, we agree with Petitioner that
`Patent Owner’s proposed constructions are too narrow and determine that
`“read operation” and “write operation” mean “getting data from” and
`“placing data in,” respectively, a memory device. As we also discussed
`supra in Section II.A.2, for the patentability determinations before us, we
`can accept Patent Owner’s contention that the term “memory device” is a
`memory chip or an IC.
`Regarding the recitation of “memory device” in claim 1, we are
`persuaded by Petitioner’s contentions and we credit and give substantial
`weight to Dr. Jacob’s testimony (see, e.g., Pet. 14–22, 24–27, 38–44, 49
`(citing, e.g., Ex. 1003 ¶¶ 103, 136–139, 148–172)), because Lee discloses
`inputting and outputting data to and from memory chips, such as memory
`chip 401. Ex. 1004, 3:38–52, 4:62–67, 6:41–67, 7:27–35, 8:59–62, 11:31–
`12:12, Figs. 4, 5. Lee also, more specifically, discloses that “memory chip
`401” is a “dynamic random access memory (DRAM)” “semiconductor
`memory device.” Ex. 1004, 6:40–42, 7:1–2, 7:27–33. Lee’s “memory chip
`401” is a DRAM device, which is the same as the example disclosed in the
`’122 Patent, i.e., “[f]or example, in one embodiment, the memory device
`may be a volatile memory device such as a dynamic, random access memory
`(DRAM) device.” Ex. 1001, 3:50–59 (emphasis added).
`Regarding the claimed “read operation” and “write operation,” we are
`persuaded by Petitioner’s contentions and credit and give substantial weight
`to Dr. Jacob’s testimony regarding Lee’s disclosure of inputting and
`outputting data to and from the aforementioned chips. See, e.g., Pet. 14–22,
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`24–27, 38–44, 49 (citing, e.g., Ex. 1003 ¶¶ 103, 136–139, 148–172). For
`example, we are persuaded by Petitioner’s contentions and credit and give
`substantial weight to Dr. Jacob’s testimony (id.) that Lee’s data output
`corresponds to the claimed read operation (“getting data from”) and Lee’s
`data input corresponds to the claimed write operation (“placing data in”)
`because the contentions and testimony are consistent with the evidence cited
`therein. For instance, Lee describes
`According to yet another aspect of the present invention, a
`semiconductor memory system includes a memory controller
`which generates a first clock signal, a second clock signal having
`a frequency which is greater than that of the first clock signal, an
`address signal, a command signal and data; and a memory
`module having a plurality of semiconductor memory devices
`connected to the memory controller through bus