JEDEC
`STANDARD
`
`Low Power Double Data Rate (LPDDR)
`SDRAM Standard
`
`JESD209B
`
`(Revision of JESD209A, February 2009)
`
`FEBRUARY 2010
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`SPECIAL DISCLAIMER: JEDEC has received
`information that certain patents or patent applications
`may be essential to this standard. However, as of the
`publication date of this standard, no statements
`regarding an assurance or refusal to license such
`patents or patent applications have been provided.
`Contact JEDEC for further information.
`
`JEDEC does not make any determination as to the
`validity or relevancy of such patents or patent
`applications. Anyone making use of the standard
`assumes all liability resulting from such use. JEDEC
`disclaims any representation or warranty, express or
`implied, relating to the standard and its use.
`
`IPR2017-00381
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`Polaris Ex. 2005
`
`

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`NOTICE
`
`JEDEC standards and publications contain material that has been prepared, reviewed, and approved
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`
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`or call (703) 907-7559
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`IPR2017-00381
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`Polaris Ex. 2005
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`Special Disclaimer
`
`JEDEC has received information that certain patents or patent applications
`may be essential to this standard. However, as of the publication date of this
`standard, no statements regarding an assurance or refusal to license such
`patents or patent applications have been provided. Contact JEDEC for further
`information.
`
`JEDEC does not make any determination as to the validity or relevancy of such
`patents or patent applications. Anyone making use of the standard assumes all
`liability resulting from such use. JEDEC disclaims any representation or
`warranty, express or implied, relating to the standard and its use.
`
`IPR2017-00381
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`Polaris Ex. 2005
`
`

`

`JEDEC Standard No. 209B
`
`Contents
`1 Scope ........................................................................................................................................1
`
`2 Low-Power Double Data Rate (LPDDR) SDRAM Devices ...................................................2
`2.1 Features ..................................................................................................................................2
`2.2 General Description ...............................................................................................................2
`2.2.1 Packages..............................................................................................................................4
`2.3 Terminology and Definitions.................................................................................................9
`
`3 Functional Description............................................................................................................10
`3.1 Initialization ........................................................................................................................10
`3.1.0.1 TQ Signal Initialization .................................................................................................13
`3.2 Register Definition...............................................................................................................13
`3.2.1 Mode Register ..................................................................................................................13
`3.2.1.1 Burst Length ..................................................................................................................14
`3.2.1.2 Burst Type .....................................................................................................................16
`3.2.1.3 Read Latency .................................................................................................................16
`3.2.2 Extended Mode Register ..................................................................................................16
`3.2.2.1 Partial Array Self Refresh (Optional) ...........................................................................17
`3.2.2.2 Temperature Compensated Self Refresh (Optional) .....................................................17
`3.2.2.3 Output Drive Strength ...................................................................................................17
`3.2.3 Status Register Read (Optional)........................................................................................18
`3.2.4 Temperature Output Signal (optional) ..............................................................................20
`
`4 Commands ..............................................................................................................................21
`
`5 Operation.................................................................................................................................26
`5.1 Deselect ...............................................................................................................................26
`5.2 No Operation .......................................................................................................................26
`5.3 Mode Register Set ...............................................................................................................26
`5.4 Active ..................................................................................................................................27
`5.5 Read ....................................................................................................................................28
`5.5.1 Read to Read ....................................................................................................................30
`5.5.2 Read Burst Terminate ......................................................................................................30
`5.5.3 Read to Write ...................................................................................................................30
`5.5.4 Read to Precharge ............................................................................................................30
`5.5.5 Burst Terminate ................................................................................................................34
`5.6 Write ....................................................................................................................................34
`5.6.1 Write to Write ..................................................................................................................37
`5.6.2 Write to Read ...................................................................................................................37
`5.6.3 Write to Precharge: ..........................................................................................................37
`5.7 Precharge .............................................................................................................................41
`5.8 Auto Precharge ....................................................................................................................42
`5.9 Refresh Requirements .........................................................................................................42
`5.10 Auto Refresh .....................................................................................................................42
`5.11 Self Refresh ........................................................................................................................42
`
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`JEDEC Standard No. 209B
`
`Contents
`
`5.12 Power-Down .....................................................................................................................44
`5.13 Deep Power-Down ............................................................................................................45
`5.14 Clock Stop .........................................................................................................................46
`
`6 Absolute Maximum Ratings ...................................................................................................48
`
`7 AC & DC Operating Conditions.............................................................................................49
`7.1 Driver Characteristics .........................................................................................................60
`
` Annex A (informative) Differences between Document Revisions .........................................64
`
`Figures
`1 Pin Configuration of x16 LPDDR SDRAM IN BGA .............................................................4
`2 Pin Configuration of x32 LPDDR SDRAM IN BGA ............................................................5
`3 Simplified State Diagram ........................................................................................................8
`4 Initialization Flow Diagram ..................................................................................................12
`5 Initialization Waveform Sequence ........................................................................................13
`6 Mode Register Definition ......................................................................................................14
`7 Extended Mode Register Definition .....................................................................................17
`8 SRR Register (A[n:0] = 0) .....................................................................................................19
`9 Status Register Read Timing Diagram ...................................................................................20
`10 Basic Timing Parameters for Commands ...........................................................................22
`11 NOP Command ...................................................................................................................26
`12 Mode Register Set Command .............................................................................................27
`13 Mode Register Set Command Timing ................................................................................27
`14 Active Command .................................................................................................................28
`15 Bank Activation Command Cycle .......................................................................................28
`16 Read Command ....................................................................................................................29
`17 Basic Read Timing Parameters ............................................................................................29
`18 Read Burst Showing CAS Latency ......................................................................................30
`19 Consecutive Read Bursts .....................................................................................................31
`20 Non-Consecutive Read Bursts .............................................................................................31
`21 Random Read Bursts ............................................................................................................32
`22 Terminating a Read Burst ....................................................................................................32
`23 Read To Write ......................................................................................................................33
`24 Read To Precharge ..............................................................................................................34
`25 Burst Terminate Command ..................................................................................................34
`26 Write Command ..................................................................................................................35
`27 Basic Write Timing Parameters ..........................................................................................36
`28 Write Burst (min. and max. tDQSS) ...................................................................................37
`29 Concatenated Write Bursts ...................................................................................................38
`30 Non-Consecutive Write Bursts ............................................................................................38
`31 Random Write Cycles .........................................................................................................39
`32 Non-Interrupting Write to Read ..........................................................................................39
`
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`JEDEC Standard No. 209B
`
`Contents
`33 Interrupting Write to Read ...................................................................................................40
`34 Non-Interrupting Write to Precharge ..................................................................................40
`35 Interrupting Write to Precharge ..........................................................................................41
`36 Precharge command .............................................................................................................41
`37 Auto Refresh Command ......................................................................................................42
`38 Self Refresh command ........................................................................................................43
`39 Auto Refresh Cycles Back-to-Back ....................................................................................43
`40 Self Refresh Entry and Exit ................................................................................................44
`41 Power-Down Entry and Exit ................................................................................................45
`42 Deep Power-Down Entry and Exit ......................................................................................46
`43 Clock Stop Mode Entry and Exit .........................................................................................47
`44 AC Overshoot and Undershoot Definition ..........................................................................59
`45 I-V Curves For Full Drive Strength ....................................................................................62
`46 I-V Curves For Three-Quarters Drive Strength ..................................................................62
`47 I-V Curves For Half Drive Strength ...................................................................................63
`Tables
`1 LPDDR Ballots ........................................................................................................................1
`2 LPDDR SDRAM Addressing Table ........................................................................................3
`3 Pin Descriptions .......................................................................................................................6
`4 Burst Definition .....................................................................................................................14
`5 Truth Table - Commands .......................................................................................................21
`6 Truth Table - DM Operations ................................................................................................21
`7 Truth Table - CKE ................................................................................................................22
`8 Truth Table - Current State Bank n - Command to Bank n ...................................................23
`9 Truth Table - Current State Bank n - Command to Bank m ..................................................24
`10 Operating Conditions ...........................................................................................................49
`11 Input/Output Capacitance ....................................................................................................49
`12 Electrical Characteristics and AC/DC Operating Conditions ..............................................50
`13 IDD Specification Parameters and Test Conditions ............................................................51
`14 AC Timings ..........................................................................................................................53
`15 Output Slew Rate Characteristics ........................................................................................59
`16 AC Overshoot/Undershoot Specification .............................................................................59
`17 I-V Curves For Full Drive Strength and Half Drive Strength ..............................................60
`18 I-V Curves For Three-Quarters Drive Strength ...................................................................61
`
`-iii-
`
`IPR2017-00381
`Nvidia v. Polaris
`Polaris Ex. 2005
`
`

`

`|PR2017-00381
`Nvidia v. Polaris
`Polaris Ex. 2005
`
`IPR2017-00381
`Nvidia v. Polaris
`Polaris Ex. 2005
`
`

`

`Low Power Double Data Rate (LPDDR) SDRAM
`
`JEDEC Standard No. 209B
`Page 1
`
`(From JEDEC Board Ballot JCB-05-109B, formulated under the cognizance of the JC-42.3C
`Subcommittee on Parametrics.)
`
`1 Scope
`
`This document defines the Low Power Double Data Rate (LPDDR) SDRAM specification, including features,
`functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to
`also include other higher density devices.
`The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 64 Mb through
`2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects
`of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices.
`This specification was created based on the DDR-I specification (JESD79) and some aspects of the DDR2
`specification (JESD79-2) where shared technology suggested commonality provided benefits. Each aspect of the
`changes for low power operation were considered and balloted. The accumulation of these ballots were then
`incorporated to prepare this LPDDR SDRAM specification, replacing whole sections and incorporating the changes
`into Functional Description and Operation. The applicable ballots are summarized in Table 1.
`
`Table 1 — LPDDR Ballots
`Subject
`Ballot Number
`LPDDR IO levels
`JC-42.3-03-183
`LPDDR addressing table x16
`JC-42.3-03-114
`LPDDR IDD test condition
`JC-42.3-03-184
`AC timing parameters
`JC-42.3-03-258
`Pin capacitance
`JC-42.3-03-259
`LPDDR clock stop mode
`JC-42.3-04-035
`JC-42.3-04-026 Modification of IDD6 definition
`JC-42.3-04-188
`LPDDR addressing table x32
`JC-42.3-04-147
`tREFI for x32 LPDDR
`JC-42.3-04-118
`LPDDR MRS and EMRS definition
`JC-42.3-04-111
`LPDDR SDRAM x16 in FBGA-60
`JC-42.3-04-181
`LPDDR SDRAM x32 in FBGA-90
`JC-42.3-04-037
`LPDDR initialization
`JC-42.3-04-038
`LPDDR Deep Power Down mode
`JC-42.3-04-150A LPDDR IV Curve
`JC-42.3-04-392
`LPDDR over/undershoot
`JC-42.6-07-357
`LPDDR400 SDRAM AC Parameters
`
` Item #
`1418.02
`1418.04
`1418.05
`1418.07
`1418.08
`1418.09
`1418.10
`1418.11
`1418.12
`1452.01
`1452.02
`1452.03
`1563.00
`1563.01
`1604.01
`1625.03
`1718.05
`
`1718.08
`
`JC-42.6-07-358
`
`LPDDR400 SDRAM TQ Pad Proposal
`
`1718.13
`
`JC-42.6-07-264
`
`1718.14
`
`JC-42.6-07-265
`
`1718.15
`
`JC-42-6.07-359
`
`1718.16
`
`JC-42.6-07-360
`
`1723.02
`
`JC-42.6-08-255
`
`1718.18
`
`JC-42.6-08-331
`
`LPDDR SDRAM 60-, 90-Ball BGA
`Ballouts with A13 ball
`LPDDR SDRAM 60-, 90-Ball BGA
`Ballouts with additional CS#, CKE
`LPDDR SDRAM Output Driver
`Characteristics
`LPDDR SDRAM address tables
`LPDDR SDRAM 1.2V Output
`Characteristics
`LPDDR tRC & tRFC definition
`
`Spec Coverage
`Table 12 and notes
`part of Table 2 except tREFI
`Table 13 and notes except IDD6
`Table 14 and notes
`Table 11 and notes
`Clock stop, pp 46, Figure 43
`Table 13
`part of Table 2, x32, except tREFI
`part of Table 2, x32, tREFI only
`Figure 6 and Figure 7
`Figure 1
`Figure 2
`pp 10; Figure 4 and Figure 5
`pp 45 and Figure 42
`Table 17, Figure 45 and Figure 47
`Table 16 and Figure 44
`Table 14
`Table 3, Figure 5, description page 20,
`Table 14
`
`Figure 2
`
`Figure 1 and Figure 2
`
`Figure 7, Table 15, Table 17, Table 18,
`and Figure 46.
`Table 2
`
`LPDDR SDRAM 1.2V I/O Addendum
`
`Table 14
`
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`JEDEC Standard No. 209B
`Page 2
`
`2
`
`Low-Power Double Data Rate (LPDDR) SDRAM Devices
`
`64M = 4M x 16 (1M x 16 x 4 banks), 2M x 32 (512K x 32 x 4 banks)
`128M = 8M x 16 (2M x 16 x 4 banks), 4M x 32 (1M x 32 x 4 banks)
`256M = 16M x 16 (4M x 16 x 4 banks), 8M x 32 (2M x 32 x 4 banks)
`512M = 32M x 16 (8M x 16 x 4 banks), 16M x 32 (4M x 32 x 4 banks)
`1G = 64M x 16 (16M x 16 x 4 banks), 32M x 32 (8M x 32 x 4 banks)
`2G = 128M x 16 (32M x 16 x 4 banks), 64M x 32 (16M x 32 x 4 banks)
`
`2.1 Features
`• Double-data rate architecture; two data transfers per clock cycle
`• Bidirectional, data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver
`• Differential clock inputs (CK and CK)
`• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
`• Four internal banks for concurrent operation
`• Data mask (DM) for write data
`• Burst Length: 2, 4 or 8 (16 is optional)
`• Burst Type: Sequential or Interleave
`• CAS latency: 3 (2 & 4 are optional)
`• Clock Stop capability during idle periods
`• Auto Precharge option for each burst access
`• Configurable Drive Strength
`• Auto Refresh and Self Refresh Modes
`• Optional Partial Array Self Refresh and Temperature Compensated Self Refresh
`• Deep Power Down Mode
`• LV-CMOS compatible inputs
`• VDD and VDDQ: 1.8 +/- 0.1 V
`2.2 General Description
`The LPDDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured as a quad-bank
`DRAM. These devices contain the following number of bits:
`64 Mb has 67,108,864 bits
`128 Mb has 134,217,728 bits
`256 Mb has 268,435,456 bits
`512 Mb has 536,870,912 bits
`1 Gb has 1,073,741,824 bits
`2 Gb has 2,147,483,648 bits
`The LPDDR SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate
`architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
`cycle at the I/O pins. A single read or write access for the LPDDR SDRAM effectively consists of a single 2n-bit
`wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-
`cycle data transfers at the I/O pins.
`A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
`DQS is a strobe transmitted by the LPDDR SDRAM during READs and by the memory controller during WRITEs.
`DQS is edge-aligned with data for READs and center aligned with data for WRITEs.
`The LPDDR SDRAM operates from a differential clock (CK and CK: the crossing of the CK going high and CK
`going low will be referred to as the positive edge of CK). Commands (address and control signals) are registered at
`every positive edge of CK. Input data is registered at both edges of DQS, and output data is referenced to both edges
`of DQS, as well as to both edges of CK.
`
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`JEDEC Standard No. 209B
`Page 3
`
`2 Low-Power Double Data Rate (LPDDR) SDRAM Devices (cont’d)
`2.2 General Description (cont’d)
`
`Read and write accesses to the LPDDR SDRAM are burst oriented; accesses start at a selected location and continue
`for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an
`ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident
`with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered
`coincident with the READ or WRITE command are used to select the bank and the starting column location for the
`burst access.
`The LPDDR SDRAM provides for programmable read or write bursts of 2, 4 or 8 locations. Some vendors may offer
`an optional burst length of 16. An Auto Precharge function may be enabled to provide a self-timed row precharge that
`is initiated at the end of the burst access.
`As with standard SDRAMs, the pipelined, multibank architecture of LPDDR SDRAMs allows for concurrent
`operation, thereby providing high effective bandwidth by hiding row precharge and activation times.
`An Auto Refresh mode is provided, along with a power saving Power-down mode. Self Refresh mode may have
`Temperature Compensated Self Refresh (TCSR) and Partial Array Self Refresh (PASR) options, which allow users to
`achieve additional power saving. The TCSR and PASR options can be programmed via the extended mode register.
`All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8 V (nominal).
`This datasheet includes all features and functionality required for JEDEC LPDDR SDRAM devices. Certain vendors
`may elect to offer a superset of this specification by offering improved timings and/or including optional features.
`Users benefit from knowing that any system design based on the required aspects of the specification are supported
`by all LPDDR SDRAM vendors; conversely users seeking to use any superset specifications bear the responsibility to
`verify support with individual vendors.
`
`Item
`Number of banks
`Bank Address Pins
`Autoprecharge Pin
`Row Addresses
`Column Addresses
`tREFI (μs)
`Row Addresses
`Column Addresses
`tREFI (μs)
`
` x16
`
` x32
`
`Table 2 — LPDDR SDRAM Addressing Table
`64 Mb
`128 Mb
`256 Mb
`512 Mb
`4
`4
`4
`4
`BA0, BA1
`BA0, BA1
`BA0, BA1
`BA0, BA1
`A10/AP
`A10/AP
`A10/AP
`A10/AP
`A0-A11
`A0-A11
`A0-A12
`A0-A12
`A0-A7
`A0-A8
`A0-A8
`A0-A9
`15.6
`15.6
`7.8
`7.8
`A0-A10
`A0-A11
`A0-A11
`A0-A12
`A0-A7
`A0-A7
`A0-A8
`A0-A8
`15.6
`15.6
`15.6
`7.8
`
`1 Gb
`4
`BA0, BA1
`A10/AP
`A0-A13
`A0-A9
`7.8
`A0-A12 A0-A13
`A0-A9 A0-A8
`7.8
`
`2 Gb
`4
`BA0, BA1
`A10/AP
`A0-A13
`A0-A9, A11
`7.8
`A0-A13
`A0-A9
`7.8
`
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`JEDEC Standard No. 209B
`Page 4
`2 Low-Power Double Data Rate (LPDDR) SDRAM Devices (cont’d)
`2.2 General Description (cont’d)
`
`2.2.1 Packages
`Single-die, one CS# and one CKE:
`In the 60-ball x16 package,a maximum SDRAM density of 2Gb can be achieved only with 2-KByte page
`size and most significant address bit A13.
`In the 90-ball x32 package, a maximum SDRAM density of 2Gb can be achieved either with 2-KByte page
`size and most significant address bit A13, or with 4-KByte page size and most significant address bit A12.
`Dual-die, two CS# and two CKE:
`In the 60-ball x16 package, a maximum SDRAM density of 1Gb can be achieved with most significant
`address bit A12.
`In the 90-ball x32 package, a maximum SDRAM density of 2Gb can be achieved with most significant
`address bit A12.
`
`Top View
`(Balls seen through the package)
`4
`7
`9
`3
`6
`5
`1
`2
`8
`
`60-Ball (6x10) CSP
`9
`8
`3
`7
`2
`1
`A
`VDD
`DQ0
`VSSQ
`VDDQ
`VSS DQ15
`B VDDQ DQ13
`DQ2 VSSQ
`DQ14
`DQ1
`C VSSQ DQ11
`DQ4 VDDQ
`DQ12
`DQ3
`D VDDQ DQ9
`DQ6 VSSQ
`DQ10
`DQ5
`E VSSQ UDQS
`LDQS VDDQ
`DQ8
`DQ7
`F
`VSS UDM NC,CKE1 A13,NC,CS1 LDM VDD
`G CKE0
`CK
`CK
`WE
`CAS
`RAS
`H
`A9
`A11
`A12,NC
`CS0
`BA0
`BA1
`J
`A6
`A7
`A8
`A10/AP
`A0
`A1
`K
`VSS
`A4
`A5
`A2
`A3
`VDD
`
`Figure 1 — Pin Configuration of x16 LPDDR SDRAM IN BGA
`
`A
`
`FEDCB
`
`JHG
`
`K
`
`IPR2017-00381
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`Polaris Ex. 2005
`
`

`

`2 Low-Power Double Data Rate (LPDDR) SDRAM Devices (cont’d)
`2.2 General Description (cont’d)
`
`JEDEC Standard No. 209B
`Page 5
`
`90-Ball (6x15) CSP
`9
`8
`3
`7
`2
`1
`A
`DQ16 VDD
`VSSQ
`VDDQ
`VSS DQ31
`B VDDQ DQ29
`DQ18 VSSQ
`DQ30
`DQ17
`C VSSQ DQ27
`DQ20 VDDQ
`DQ28
`DQ19
`D VDDQ DQ25
`DQ22 VSSQ
`DQ26
`DQ21
`E VSSQ DQS3
`DQS2 VDDQ
`DQ24
`DQ23
`F
`VDD DM3 NC,CKE1 A13,NC,CS1 DM2
`VSS
`G CKE0
`CK
`CK
`WE
`CAS
`RAS
`H
`A9
`A11
`A12,NC
`CS0
`BA0
`BA1
`J
`A6
`A7
`A8
`A10/AP
`A0
`A1
`K
`A4
`DM1
`A5
`A2
`DM0
`A3
`L
`VSSQ DQS1
`DQ8
`DQ7
`DQS0 VDDQ
`M VDDQ DQ9
`DQ10
`DQ5
`DQ6 VSSQ
`N VSSQ DQ11
`DQ12
`DQ3
`DQ4 VDDQ
`P VDDQ DQ13
`DQ14
`DQ1
`DQ2 VSSQ
`R
`VSS DQ15
`VSSQ
`VDDQ
`DQ0
`VDD
`
`Top View
`(Balls seen through the package)
`4
`7
`9
`3
`6
`5
`1
`2
`8
`
`A
`
`FEDCB
`
`JHG
`
`K
`L
`
`PNM
`
`R
`
`Figure 2 — Pin Configuration of x32 LPDDR SDRAM IN BGA
`
`IPR2017-00381
`Nvidia v. Polaris
`Polaris Ex. 2005
`
`

`

`JEDEC Standard No. 209B
`Page 6
`2 Low-Power Double Data Rate (LPDDR) SDRAM Devices (cont’d)
`2.2 General Description (cont’d)
`
`Symbol
`
`CK, CK
`
`Type
`
`Input
`
`CKE
`
`Input
`
`CS
`
`RAS, CAS,
`WE
`
`DM
`for x16:
`LDM, UDM
`for x32:
`DM0-DM3
`
`Input
`
`Input
`
`Input
`
`BA0, BA1
`
`Input
`
`A [n : 0]
`
`Input
`
`Table 3 — Pin Descriptions
`Description
`Clock: CK and CK are differential clock inputs. All address and control input signals are
`sampled on the crossing of the positive edge of CK and negative edge of CK. Input and
`output data is referenced to the crossing of CK and CK (both directions of crossing).
`Internal clock signals are derived from CK/CK.
`Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
`device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
`POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-
`DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for SELF
`REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CK, CK and
`CKE, are disabled during power-down and self refresh mode which are contrived for low
`standby power consumption.
`Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command
`decoder. All commands are masked when CS is registered HIGH. CS provides for
`external bank selection on systems with multiple banks. CS is considered part of the
`command code.
`Command Inputs: RAS, CAS and WE (along with CS) define the command being
`entered.
`Input Data Mask: DM is an input mask signal for write data. Input data is masked when
`DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
`on both edges of DQS. Although DM pins are input-only, the DM loading matches the DQ
`and DQS loading.
`For x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the
`data on DQ8-DQ15.
`For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the
`data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds
`to the data on DQ24-DQ31.
`Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
`PRECHARGE command is being applied.
`Address Inputs: provide the row address for ACTIVE commands, and the column address
`and AUTO PRECHARGE bit for READ / WRITE commands, to select on