`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________________________
`
`
`NVIDIA CORPORATION,
`Petitioner
`
`
`v.
`
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner
`
`________________________________
`
`
`
`Case No. IPR2017-00381
`Patent No. 7,866,122
`
`
`________________________________
`
`
`
`PATENT OWNER’S RESPONSE
`TO PETITION FOR INTER PARTES REVIEW
`
`

`

`TABLE OF CONTENTS
`
`TABLE OF AUTHORITIES .................................................................................. iv
`
`I.
`
`II.
`
`INTRODUCTION ......................................................................................... 1
`
`BACKGROUND ........................................................................................... 4
`
`A.
`
`B.
`
`The ’122 Patent ................................................................................... 4
`
`References Cited in the Petition .......................................................... 6
`
`1.
`
`2.
`
`Lee ............................................................................................. 6
`
`Yoo, Kyung, and Gould .......................................................... 13
`
`III.
`
`INTERPRETATION OF THE ’122 PATENT CLAIMS ........................... 14
`
`A.
`
`B.
`
`C.
`
`“Memory Device” Means a Memory Integrated Circuit. ................. 14
`
`“Means for Interfacing a Control Device” ........................................ 21
`
`“Read Operation” and “Write Operation” Refer to Getting Data
`From and Placing Data in, Respectively, a Memory Array. ............. 22
`
`1.
`
`2.
`
`3.
`
`The claims themselves support this interpretation. ................. 22
`
`The ’122 Patent specification supports this interpretation. .... 23
`
`This interpretation is consistent with the understanding of
`those skilled in the memory art. .............................................. 25
`
`IV. TRIAL SHOULD BE TERMINATED IN POLARIS’S FAVOR
`BECAUSE THE IPR SYSTEM IS UNCONSTITUTIONAL. ................... 27
`
`V. ALL CHALLENGES FAIL WITH RESPECT TO ALL CLAIMS. .......... 27
`
`A.
`
`B.
`
`Lee Does Not Explicitly Disclose “Read Operations” and
`“Write Operations.” ........................................................................... 27
`
`The Petition Fails to Establish Inherent Disclosure of “Read
`Operations” and “Write Operations” in Lee. .................................... 30
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`VI. ALL CHALLENGES FAIL WITH RESPECT TO CLAIMS 16-19
`BECAUSE THE PETITION FAILS TO POINT OUT A “MEMORY
`ARRAY” IN LEE’S “MEMORY DEVICE.” ............................................. 31
`
`A.
`
`B.
`
`C.
`
`D.
`
`The Petition’s Position ...................................................................... 31
`
`Attributing Positions to the Petitioner Different From Those
`Advanced in the Petition is Improper. ............................................... 34
`
`The Board Cannot Rely on Expert Testimony That was Not
`Argued in the Petition. ...................................................................... 36
`
`The Petition Fails to Establish a “Memory Device” in Lee or a
`“Memory Array” in Lee’s Alleged “Memory Device.” .................... 40
`
`VII. ALL CHALLENGES FAIL WITH RESPECT TO MEAN-PLUS-
`FUNCTION CLAIMS 24-27 BECAUSE LEE LACKS A “MEANS
`FOR INTERFACING A CONTROL DEVICE.” ....................................... 41
`
`VIII. CHALLENGES 3 AND 4 FAIL. ................................................................ 42
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`F.
`
`The Nature of Challenges 3 and 4 ..................................................... 42
`
`Invalidity of Claims 2, 10, 17, 21, 25, and 28 Cannot be Based
`on the STROBE Signal in Lee’s First Embodiment. ........................ 45
`
`The Board Should Not Permit the Petitioner to Shift its
`Contentions Now to Argue that Lee Discloses a STROBE
`Signal in the Second Embodiment. ................................................... 49
`
`If Lee Discloses a STROBE Signal in the Second Embodiment,
`it is Not in Conjunction With the Two External Clock Signals
`CLK1 and CLK2. .............................................................................. 51
`
`Ambiguity in Lee Must be Resolved in Polaris’s Favor. .................. 56
`
`Neither Yoo Nor Kyung Cures the Fundamental Flaw in Lee. ........ 56
`
`IX. CHALLENGE 3 ALSO FAILS FOR ADDITIONAL REASONS. ........... 58
`
`A.
`
`The Petition Does Not Present a Proper Rationale to Combine
`Lee and Yoo. ..................................................................................... 58
`
`B.
`
`Yoo Does Not Teach How to Generate Lee’s STROBE Signal. ...... 63
`
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`X.
`
`CHALLENGE 4 ALSO FAILS FOR ADDITIONAL REASONS. ........... 64
`
`A.
`
`B.
`
`The Petition Does Not Present a Proper Rationale to Combine
`Lee and Kyung. ................................................................................. 64
`
`Kyung Does Not Teach How to Generate Lee’s STROBE
`Signal. ................................................................................................ 65
`
`XI. CONCLUSION ............................................................................................ 66
`
`
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`IPR2017-00381
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`TABLE OF AUTHORITIES
`
`Cases
`2Wire, Inc. v. TQ Delta LLC,
`IPR2015-00239, Paper 18 (PTAB May 29, 2015) .......................................... 36
`
`Artic Cat, Inc. v. Polaris Indus. Inc.,
`IPR2017-00433, Paper 15 (PTAB June 22, 2017) .......................................... 39
`
`Axon Enter., Inc. v. Digital Ally, Inc.,
`IPR2017-00375, Paper 9 (PTAB June 6, 2017) .............................................. 38
`
`Belden Inc. v. Berk-Tek LLC,
`805 F.3d 1064 (Fed. Cir. 2015) ................................................................. 36, 63
`
`Cisco Sys., Inc. v. C-Cation Techs., LLC,
`IPR2014-00454, Paper 12 (PTAB Aug. 29, 2014) .................................... 36, 37
`
`Conopco, Inc. v. Procter & Gamble Co.,
`IPR2013-00510, Paper 9 (PTAB Feb. 12, 2014) ............................................ 37
`
`Covidien LP v. Univ. of Fla. Research Found. Inc.,
`IPR2016-01274, Paper 21 (PTAB Jan. 25, 2017) ........................................... 36
`
`Dell, Inc. v. Elecs. & Telecommn’cs Research Inst.,
`IPR2014-00152, Paper 12 (PTAB May 16, 2014) .......................................... 60
`
`Dynamic Drinkware, LLC v. Nat’l Graphics, Inc.,
`800 F.3d 1375 (Fed. Cir. 2015) ........................................................... 29, 41, 56
`
`In re Fine,
`837 F.3d 1071 (Fed. Cir. 1988) ....................................................................... 41
`
`Finnigan Corp. v. Int’l Trade Comm’n,
`180 F.3d 1354 (Fed. Cir. 1999) ....................................................................... 51
`
`In re Geisler,
`116 F.3d 1465 (Fed. Cir. 1997) ....................................................................... 62
`
`Gubelmann v. Gang,
`408 F.2d 758 (CCPA 1969) ............................................................................. 30
`
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`Homeland Housewares, LLC v. Whirlpool Corp.,
`No. 2016-1511 (Fed. Cir. Aug. 4, 2017) ......................................................... 14
`
`Icon Health & Fitness, Inc. v. Strava, Inc.,
`849 F.3d 1034 (Fed. Cir. 2017) ....................................................................... 62
`
`Intelligent Bio-Systems, Inc. v. Illumina Cambridge Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) ................................................................. 51, 65
`
`Lam Research Corp. v. Flamm,
`IPR2016-00466, Paper 7 (PTAB July 19, 2016) ............................................. 60
`
`In re Magnum Oil Tools Int’l, Ltd.,
`829 F.3d 1364 (Fed. Cir. 2016) ................................................................ passim
`
`MEHL/Biophile Int’l Corp. v. Milgraum,
`192 F.3d 1365 (Fed. Cir. 1999) ....................................................................... 30
`
`Monsanto Co. v. Pioneer Hi-Bred Int’l, Inc.,
`IPR2013-00023, Paper 32 (PTAB Apr. 11, 2013) .......................................... 60
`
`In re Morris,
`127 F.3d 1048 (Fed. Cir. 1997) ....................................................................... 20
`
`Net MoneyIN, Inc. v. Verisign, Inc.,
`545 F.3d 1359 (Fed. Cir. 2008) ....................................................................... 48
`
`Norman Noble, Inc. v. Nutech Ventures,
`IPR2013-00101, Paper 14 (PTAB June 20, 2013) .......................................... 62
`
`In re Nuvasive,
`841 F.3d 966 (Fed. Cir. 2016) ......................................................................... 51
`
`Oakley, Inc. v. Sunglass Hut Int’l,
`316 F.3d 1331 (Fed. Cir. 2003) ....................................................................... 60
`
`In re Oelrich,
`666 F.2d 578 (CCPA 1981) ............................................................................. 30
`
`Oil States Energy Services LLC v. Greene’s Energy Group, LLC,
`No. 16-712 (cert. granted June 12, 2017) ........................................................ 27
`
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`Perfect Surgical Techniques, Inc. v. Olympus Am., Inc.,
`841 F. 3d 1004 (Fed. Cir. 2016) ...................................................................... 37
`
`Personal Web Techs., LLC v. Apple, Inc.,
`848 F.3d 987 (Fed. Cir. 2017) ......................................................................... 63
`
`Pi-Net Int’l, Inc. v. JPMorgan Chase & Co.,
`600 F. App’x 774 (Fed. Cir. 2015) (non-precedential) ................................... 39
`
`SAS Inst., Inc. v. ComplementSoft, LLC,
`825 F.3d 1341 (Fed. Cir. 2016) ....................................................................... 35
`
`Slimfold Mfg. Co. v. Kinkead Indus., Inc.,
`810 F.2d 1113 (Fed. Cir. 1987) ....................................................................... 23
`
`In re Smith Int’l, Inc.,
`No. 2016-2303 (Fed. Cir. Sept. 26, 2017) ....................................................... 20
`
`Symantec Corp. v. Rpost Commc’ns Ltd.,
`IPR2014-00353, Paper 15 (PTAB July 15, 2014) ........................................... 37
`
`Taiwan Semiconductor Mfg. Co. v. Ziptronix, Inc.,
`IPR2013-00154, Paper 19 (PTAB Nov. 6, 2013) ............................................ 62
`
`Trintec Indus., Inc. v. Top-U.S.A. Corp.,
`295 F.3d 1292 (Fed. Cir. 2002) ....................................................................... 30
`
`Wasica Fin. GmbH v. Cont’l Auto. Sys., Inc.,
`853 F.3d 1272 (Fed. Cir. 2017) ....................................................................... 56
`
`
`
`Statutes
`
`35 U.S.C. § 102 ........................................................................................................48
`
`35 U.S.C. § 313 .......................................................................................................... 1
`
`35 U.S.C. § 316(e) ...................................................................................... 29, 41, 56
`
`
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`Rules
`
`37 C.F.R. § 42.24 .....................................................................................................37
`
`37 C.F.R. § 42.24(a)(1)(i) ........................................................................................37
`
`37 C.F.R. § 42.107 ..................................................................................................... 1
`
`
`
`Other Authorities
`
`MPEP § 2143.03 ......................................................................................................41
`
`
`
`
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`IPR2017-00381
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`Page vii
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`I.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. § 316(a)(8) and 37 C.F.R. § 42.120, the Patent Owner
`
`Polaris Innovations Limited (“Polaris”) hereby responds to the petition for inter
`
`partes review filed December 7, 2016 (Paper 1, herein “petition” or “Pet.”). A
`
`joint stipulation filed August 10, 2017 (Paper 13) set September 29, 2017 as the
`
`deadline for this response, which is timely filed. No fee is due with this response,
`
`but if the Board believes that any additional fee is due, it is authorized to charge
`
`deposit account No. 50-5836.
`
`An institution decision dated June 22, 2017 (Paper 9, herein “Inst. Dec’n”)
`
`instituted trial to determine whether the petition has met its burden to show that the
`
`claims of U.S. Patent No. 7,866,122 (Ex. 1001, herein “the ’122 Patent”) are
`
`unpatentable on the following four grounds:
`
` Challenge 1: Whether claims 1, 5, 6, 8, 9, 13, 14, 16, 20, and 24 are
`
`anticipated by Lee (Ex. 1004).
`
` Challenge 3: Whether claims 2-4, 10-12, 17-19, 21-23, and 25-28 are
`
`obvious over Lee in view of Yoo (Ex. 1006).
`
` Challenge 4: Whether claims 2, 3, 10, 11, 17, 18, 21, 22, 25, and 26 are
`
`obvious over Lee in view of Kyung (Ex. 1005).
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` Challenge 5: Whether claims 7 and 15 are obvious over Lee in view of
`
`Gould (Ex. 1007).
`
`The Board did not institute trial on Challenge 2 – whether the same claims at issue
`
`in Challenge 3 are obvious over Lee alone.
`
`As explained herein and in the accompanying declaration of Dr. Steven A.
`
`Przybylski (Ex. 2003, herein “Przybylski Decl.”), the petition fails to show by a
`
`preponderance of the evidence that any of the challenges prevails.
`
`First, all challenges fail because Lee, the primary reference, fails to
`
`explicitly disclose “read operations” or “write operations,” and the petition does
`
`not even attempt to show inherent disclosure of those operations. Those phrases
`
`should be interpreted to require getting data from or placing data in a memory
`
`array, respectively. However, Lee does not explicitly disclose a memory array and
`
`fails to mention any data transactions other that putting data from a bus into a
`
`buffer or vice versa. And, the petition fails to set forth a case for inherent
`
`disclosure. As a result, the petitioner cannot carry its burden of proof.
`
`Second, Challenges 3 and 4 are based on a misunderstanding of Lee.
`
`Challenges 3 and 4 to certain dependent claims rely on Lee’s STROBE signal,
`
`contending that it is the “read clock” recited in claims 2, 10, 17, 21, 25, and 28, and
`
`that each of Yoo and Kyung teach various ways to generate that STROBE signal
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`from the externally supplied clock signal CLK2. However, there is no
`
`embodiment in Lee having the both a STROBE signal and two external clock
`
`signals. Lee’s first embodiment, illustrated in Figure 3, has a STROBE signal but
`
`not an external second clock signal CLK2. To the extent that Lee’s second
`
`embodiment, illustrated in Figures 4 and 5, might include a STROBE signal, it
`
`would be in place of CLK2 not in addition to CLK2. Thus, Challenges 3 and 4 are
`
`premised on a misunderstanding of Lee, which neither Yoo nor Kyung can rectify.
`
`Furthermore, Challenges 3 and 4 fail because the petition does not present a
`
`proper rationale to combine Lee with either Yoo or Kyung. The evidence
`
`presented
`
`to support
`
`the rationales lacks a substantiated, non-conclusory
`
`explanation why one skilled in the art would have made the proposed
`
`combinations. All other asserted rationales are either attorney argument,
`
`conclusory expert assertions, or merely statements that one skilled in the art could
`
`have combined the references’ teachings, not an explanation why one skilled in the
`
`art would have made the combinations. Moreover, each of Yoo and Kyung differ
`
`from Lee in ways that make them unsuitable to teach one skilled in the art how to
`
`generate Lee’s STROBE signal.
`
`Third, the challenges to claims 16-19, as framed in the petition, are deficient
`
`because the petition fails to point out a “memory array” in Lee’s “memory device.”
`
`The petition very clearly contends that the “memory device” in Lee is a memory
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`module and the “memory array” is a set of memory chips. However, that is
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`contrary to the proper interpretation of the phrase “memory device.” The
`
`institution decision improperly reformulated those challenges to find a different
`
`memory array in a different memory device, based on some testimony from the
`
`petitioner’s expert, Dr. Jacob. However, the petition never adopted that testimony,
`
`which cannot be incorporated by reference into the petition, not even by the Board
`
`itself.
`
`Fourth, the challenges to means-plus-function claims 24-27 are deficient
`
`because the petition has failed to show that part of the corresponding structure for
`
`the “means for interfacing” limitation is in Lee. The missing part is the read signal
`
`“RDQS2x.” The petition fails to show that it or its equivalent is present in Lee.
`
`Finally, this trial should be terminated because the IPR system is
`
`unconstitutional.
`
`II. BACKGROUND
`
`A. The ’122 Patent
`
`The ’122 Patent describes a way to reduce power consumption in a memory
`
`device by sending two clocks from a control device to the memory device – a
`
`faster clock for data access operation and a slower clock for commands and
`
`addresses. The claims refer to a “first clock signal” and a “second clock signal.”
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`All independent claims state that “a frequency of the first clock signal is less than a
`
`frequency of the second clock signal.” Figure 1 (reproduced in next paragraph) of
`
`the ’122 Patent illustrates both clock signals transferred from the control device
`
`102 to the memory device 110, as follows, where the clock signal labeled
`
`“CLK1x”
`
`is
`
`the slower,
`
`first clock signal. The clock signal
`
`labeled
`
`“WDQX_RCLK2x” is the faster, second clock signal.
`
`Dependent claims 2, 10, 17, 21, and 25, as well as independent claim 28
`
`further refer to “a read clock signal generated from the second clock signal.” In
`
`Figure 1 above, the signal labeled “RDQS2x” is a read clock signal transmitted
`
`from the memory device 110 to the control device 102, and the signal labeled
`
`“Int_RCLK” is an internal read clock signal within the memory device 110. These
`
`signals are shown in green in the version of Figure 1 below:
`
`Id. (color annotations added); Przybylski Decl. ¶ 40.
`
`
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`B. References Cited in the Petition
`
`1.
`
`Lee
`
`All challenges depend at least in part on Lee. Lee discloses a memory
`
`controller connected to a plurality of memory chips on a memory module. Lee
`
`teaches two principal embodiments: (1) a “first embodiment” having a single
`
`clock provided to the memory chips along with an optional strobe signal and (2) a
`
`“second embodiment” in which the memory controller provides two clocks to the
`
`memory chips without any strobe signal. See Przybylski Decl. ¶¶ 59-61.
`
`The first embodiment is illustrated in Figure 3, reproduced below, where the
`
`external clock signal CLK is highlighted in red, and the STROBE signal is
`
`highlighted in green:
`
`Id. ¶ 59. Lee describes this first embodiment from column 5, line 43 to column 6,
`
`line 45. Lee’s first embodiment appears to be based primarily on DDR (double
`
`
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`data rate) DRAM, which utilizes a STROBE signal and a single external clock like
`
`CLK shown in Figure 3. See id.; Lee at 6:37-45.
`
`While Figure 3 shows two clock signals, a slower CLK1 and a faster CLK2,
`
`those clock signals are generated internally within the memory device 101 and
`
`therefore clearly do not correspond to the claimed “first clock signal” and “second
`
`clock signal” “provide[d]” to or “receiv[ed]” at the “memory device,” as variously
`
`recited in all independent claims of the ’122 Patent.
`
`Lee’s second embodiment is illustrated in Figures 4 (reproduced below with
`
`red highlighting to illustrate the two external clocks) and 5 and described from
`
`column 6, line 46 to column 7, line 17. Lee’s second embodiment is distinct from
`
`and significantly different from his first embodiment.
`
`
`
`Przybylski Decl. ¶ 62.
`
`As illustrated above, Lee’s second embodiment does not utilize a STROBE
`
`signal; instead it utilizes two external clock signals. Indeed, neither Figure 4 nor 5
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`depicts a STROBE signal like Figure 3. The STROBE single in the first
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`embodiment is used to control the latching of the data and to cause input and
`
`output of data from the data buffer 340. See id. at 6:37-40 (“[T]he data buffer 340
`
`inputs/outputs data DATA in response to an edge of the strobe signal STROBE.”),
`
`Fig. 3 (STROBE going into the data buffer 340). In the second embodiment that
`
`functionality is performed by CLK2. See id. at 7:7-10 (“The data buffer 540
`
`receives the second clock signal CLK2 and the data signal DATA.”), Fig. 5 (CLK2
`
`going into the data buffer 540). Figure 3 is the only block diagram in Lee that
`
`illustrates a strobe signal. The absence of a STROBE signal in Figure 5 is clear
`
`looking at Figures 3 and 5 side by side, as follows:
`
`LEE’S FIGURE 3
`FIRST EMBODIMENT
`
`LEE’S FIGURE 5
`SECOND EMBODIMENT
`
`
`
`
`
`Id. at Figs. 3, 5 (coloring added).
`
`Lee discloses additional embodiments three through eight, which have two
`
`external clocks like the second embodiment, but with different placements of the
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`register 710, 910, or 1110 and/or the PLL (phase-locked loop) 920 or 1120, as
`
`illustrated in Figures 7-12.
`
`Lee also includes a single timing diagram (Figure 6) that illustrates the
`
`timing of signals in both the first and second embodiments together on the same
`
`diagram. See Lee at 5:20-21 (“FIG. 6 is an operational timing diagram of the
`
`semiconductor memory devices shown in FIG. 3 and 5.” (emphases added)); see
`
`also id. at 7:18-19 (“An operational timing diagram of the memory chips of the
`
`first and second embodiments is shown in Figure 6.” (emphasis added)”). Lee’s
`
`Figure 6 is reproduced below:
`
`
`
`Id. at Fig. 6.
`
`
`
`Lee describes Figure 6 in two paragraphs at column 7, lines 18-41, which
`
`read as follows:
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`An operational timing diagram of the memory
`chips of the first and second embodiments is shown in
`FIG. 6. Generally, the period of the first internal clock
`signal CLK1 is preferably an integer multiple of a period
`of the external clock signal CLK. In this example, the
`frequency of the first internal clock signal CLK1 is half
`that of the external clock signal CLK (or the second
`internal clock signal CLK2). The address signal ADDR
`and the command signal CMD include setup and hold
`time margins relative to the rising edge of the first
`internal clock signal CLKl. In the case of a single data
`rate (SDR) DRAM semiconductor memory device, the
`data is output through a data terminal DQ at every rising
`or falling edge of the second internal clock signal CLK2
`(which has the same frequency as the external clock
`signal CLK). In the case of a double data rate (DDR)
`DRAM semiconductor memory device, the data is output
`through a data terminal DQ at both the rising and falling
`edges of the second internal clock signal CLK2.
`
`In the case where the data buffer included in the
`memory chip of the first or second embodiment is
`connected to receive a data strobe signal STROBE, the
`data is input/output at both the rising and falling edges of
`the data strobe signal STROBE as shown in FIG. 6. This
`operation generally corresponds to that of the DDR
`DRAM.
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`IPR2015-00381
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`Id. at 7:18-41. The first paragraph describes the CLK signal of Figure 6 as the
`
`external clock signal. This corresponds to the CLK signal of the first embodiment.
`
`See id. at 5:49-50, 6:3; Przybylski Decl. ¶ 65. It also describes CLK1 and CLK2
`
`signals as internal clock signals, which again corresponds to the description of the
`
`first embodiment. See id. at 5:51-52; Przybylski Decl. ¶ 65.
`
`The second paragraph in this passage discusses the possibility of a strobe
`
`signal STROBE being connected to the data buffers of the first embodiment or,
`
`perhaps, the second embodiment, and that in these cases, the data is input (i.e.,
`
`write data) and output (i.e., read data) at each rising and falling edge of the
`
`STROBE signal. With regard to the first embodiment, that possibility was
`
`previously disclosed in Figure 3 and the passage at 6:37-40, and this paragraph
`
`(7:36-41) adds nothing new to the disclosure.
`
`With regard to the possible use a STROBE signal connected to the memory
`
`device of the second embodiment, Figure 5 illustrates that the only possible signal
`
`path available to connect a STROBE signal to the data buffer 540 is the one shown
`
`there communicating CLK2. This paragraph (7:36-41) is therefore suggesting the
`
`substitution of the CLK2 signal in both Figures 4 and 5 with a STROBE signal.
`
`See Przybylski Decl. ¶¶ 68-69. In that case, each semiconductor memory device
`
`401-408 is supplied with one clock and one strobe. This is the same combination
`
`that is disclosed in the first embodiment (illustrated in Figure 3 and described at
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`IPR2015-00381
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`5:49-51 and 6:37-40). This paragraph neither suggests combining the first and
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`second embodiments nor suggests changing either embodiment to accommodate
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`the STROBE signal in addition to the signals already present and illustrated in the
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`drawings. Id. Further, Figures 4 and 5 of Lee specifically do not show a STROBE
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`signal being supplied to the memory devices in place of or in addition to CLK2.
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`This paragraph is therefore clearly not about the second embodiment as depicted in
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`Figures 4 and 5.
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`Lee denotes the first trace signal in Figure 6 with “CLK(=CLK2)” indicating
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`that the external CLK signal of the first embodiment (Figure 3) has the same
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`temporal relationship to data as does the internal CLK2 signal. See id. at 6:19-26;
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`Przybylski Decl. ¶ 65. Further, Lee discloses that the second clock signal CLK2
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`of the second embodiment is substantially the same as the external clock signal
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`CLK of the first embodiment. See id. at 6:55-58; Przybylski Decl. ¶ 65. This
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`similarity facilitates using one figure to illustrate the timing of both embodiments.
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`Thus, in light of the other figures and the text of the specification, one skilled in
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`the art would understand that Figure 6 illustrates the similar timing of two different
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`embodiments in one diagram. See Przybylski Decl. ¶ 65.
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`In total, Lee describes three or four scenarios across two embodiments. In
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`the first embodiment, illustrated in Figure 3, a single external clock is called CLK.
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`The STROBE signal is optional in this first embodiment, as this first embodiment
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`may or may not also utilize a STROBE signal connected directly to the data buffer
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`340. See Przybylski Decl. ¶¶ 60, 71. Lee’s second embodiment, illustrated in
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`Figures 4 and 5, primarily utilizes two external clocks (CLK1 and CLK2).
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`However, to the extent Lee contemplates connecting the STROBE signal to the
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`second embodiment, the STROBE signal would connect in place of CLK2,
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`replacing CLK2 with STROBE. See Lee at 7:36-40; Przybylski Decl. ¶ 68-71. In
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`neither embodiment nor in any of the subsequent embodiments does Lee provide
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`both CLK1 and CLK2 to the memory chip and generate STROBE from a clock
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`signal. Instead, Lee discloses either (a) two external clocks (CLK1 and CLK2) or
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`(b) a single external clock (CLK) and a STROBE. See Przybylski Decl. ¶ 72.
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`2.
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`Yoo, Kyung, and Gould
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`The anticipation challenge to the independent claims 1, 9, 16, 20, 24, and 28
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`(Challenge 1) contends that Lee’s CLK1 and CLK2 signals in Lee’s second
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`(embodiment corresponds to the claimed “first clock signal” and “second clock
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`signal,” respectively. See Pet. at 14-21 (claim 1), 29-35 (claim 9), 40-44 (claim
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`16), 47-49 (claim 20), 51 (claim 24), 68 (claim 28 under non-instituted Challenge
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`2), 84 (claim 28 under Challenge 3), 94 (claim 28 under Challenge 4).
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`The challenges to dependent claims 2-4, 10-12, 17-19, 21-23, and 25-28
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`(Challenges 3 and 4) contend that Lee’s STROBE signal corresponds to the
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`claimed “read clock signal generated from the second clock signal.” The petition
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`cites Yoo and Kyung as each allegedly teaching ways to generate Lee’s STROBE
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`signal from a clock signal.
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`The petition relies on Gould in Challenge 5 as allegedly teaching a low-
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`power DDR (LP-DDR) interface, as recited in dependent claims 7 and 15.
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`III.
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`INTERPRETATION OF THE ’122 PATENT CLAIMS
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`A.
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`“Memory Device” Means a Memory Integrated Circuit.
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`Every independent claim in the ’122 Patent refers to a “memory device.”
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`Polaris’s preliminary response pointed out that this phrase means a memory
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`integrated circuit, but the institution decision chose not to interpret the phrase
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`because it found that the petition showed a reasonable likelihood of prevailing
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`even under Polaris’s interpretation. Inst. Dec’n at 7. However, the phrase must
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`now be interpreted to address the arguments set forth in § VI infra. See Homeland
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`Housewares, LLC v. Whirlpool Corp., No. 2016-1511, slip op. at 5-6 (Fed. Cir.
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`Aug. 4, 2017) (Board must resolve actual disputes regarding claim scope). Polaris
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`therefore reiterates its arguments in support of its interpretation.
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`The petition offers no explicit interpretation of this phrase but implicitly
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`assumes a broad interpretation, asserting that a circuit board containing multiple
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`memory chips is a “memory device.” See Pet. at 37-38, 50. In particular, the
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`petition seems to decompose this phrase into its constituent terms, to apply a plain
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`meaning to each term in isolation, and to glue together those individual meanings
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`to arrive at an implicit interpretation for the phrase as any device that contains
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`memory. In this way, the petition is able to assert that a memory module is a
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`“memory device.”
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`However, the phrase “memory device” is not a generic adjective-noun pair
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`as used in the memory art; instead, it is a compound noun with a particular
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`meaning that is not the same as the literal decomposition of the individual terms
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`might suggest. Specifically, the phrase “memory device” in the memory art is a
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`memory integrated circuit (IC), which is typically mounted on a circuit board or
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`module. Such an integrated circuit is sometimes colloquially referred to in the art
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`as a “chip.” Thus, a “memory device” is not any device that contains memory or
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`performs a memory function. For example, one skilled in the art would not call a
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`computer a “memory device” even though memory is an indispensable part of
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`every computer. Nor would one skilled in the art use the term “memory device” to
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`refer to a myriad of devices that predominantly contain memory, devices such as a
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`disk drive or a memory module. Instead, those skilled in the art understand a
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`“memory device” to be a memory integrated circuit. The references cited in the
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`petition and Dr. Jacob’s testimony and writings confirm this understanding, as does
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`the ’122 Patent.
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