Paper 10
`Trials@uspto.gov
`571-272-7822 Entered: June 23, 2017
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`____________
`
`Case IPR2017-00382
`Patent 7,124,325 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`WILLIAM M. FINK, Administrative Patent Judges.
`
`PARVIS, Administrative Patent Judge.
`
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: June 23, 2017
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`____________
`
`Case IPR2017-00382
`Patent 7,124,325 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`WILLIAM M. FINK, Administrative Patent Judges.
`
`PARVIS, Administrative Patent Judge.
`
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`IPR2017-00382
`Patent 7,124,325 B2
`
`I. INTRODUCTION
`
`NVIDIA Corporation (“Petitioner”) filed a Petition for inter partes
`
`review of claims 1–20 (“the challenged claims”) of U.S. Patent No.
`
`7,124,325 B2 (Ex. 1001, “the ’325 Patent”). Paper 2 (“Pet.”). Polaris
`
`Innovations Limited (“Patent Owner”) filed a Preliminary Response. Paper
`
`7 (“Prelim. Resp.”).
`
`We apply the standard set forth in 35 U.S.C. § 314(a), which requires
`
`demonstration of “a reasonable likelihood that the petitioner would prevail
`
`with respect to at least 1 of the claims challenged in the petition.” Upon
`
`consideration of the Petition and Preliminary Response, we conclude the
`
`information presented does not show there is a reasonable likelihood that
`
`Petitioner would prevail in establishing the unpatentability of the challenged
`
`claims of the ’325 Patent. Accordingly, we do not institute an inter partes
`
`review.
`
`A.
`
`Related Matters
`
`The parties state that the ’325 Patent is the subject of a pending
`
`lawsuit that includes assertions against Petitioner. Pet. 93; Paper 4 (“Patent
`
`Owner’s Initial Mandatory Notices”), 2–3. Patent Owner identifies a lawsuit
`
`pending in the Northern District of California, i.e., Polaris Innovations Ltd.
`
`v. Dell Inc., Case No. 4:16–cv-07005 (N.D. Cal.).1 Patent Owner’s Initial
`
`Mandatory Notices, 2–3.
`
`
`
`1 This lawsuit is referred to herein as the “companion district court lawsuit.”
`The companion district court lawsuit was transferred from the United States
`District Court for the Western District of Texas on December 5, 2016. Id.
`That case was Polaris Innovations Ltd. v. Dell Inc., Case No. 5:16–cv-00451
`(W.D. Tex). Pet. 93; Patent Owner’s Initial Mandatory Notices, 2.
`
`2
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`IPR2017-00382
`Patent 7,124,325 B2
`
`B. The ’325 Patent
`
`The ʼ325 Patent is directed to trimming interface devices on
`
`semiconductor devices. Ex. 1001, 1:10-12. Figure 3 of the ’325 Patent is
`
`reproduced below.
`
`Figure 3 illustrates a schematic diagram of a configuration for
`trimming interface devices in a semiconductor device.
`
`As shown in Figure 3 above, semiconductor device 1 includes
`
`
`
`trimming unit 5 that is connected to interface devices 10a–10d in a driver
`
`device. Id. at 7:61–8:6. Trimming unit 5 is connected to test control unit 24
`
`3
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`IPR2017-00382
`Patent 7,124,325 B2
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`in test apparatus 2. Id. at 8:8–9. Control path 34 connects test apparatus 2 to
`
`trimming register 14. Id. at 8:10–11.
`
`C. Illustrative Claim
`
`Petitioner challenges claims 1–20 of the ’325 Patent. Pet. 1. Claims 1
`
`and 14 are independent claims. Claims 2–13 and 15–20 depend, directly or
`
`indirectly, from claims 1 or 14. Independent claim 1, reproduced below, is
`
`illustrative of the claimed subject matter:
`
`1. A method for trimming interface devices, which comprises:
`
`providing a semiconductor device having a plurality of interface
`devices and providing each one of the plurality of interface
`devices with a settable control element;
`
`providing a test apparatus having a current source;
`
`connecting the current source in the test apparatus to an interface
`connection on the semiconductor device, the interface
`connection being connected to one of the plurality of interface
`devices;
`
`controlling a measurement current produced by the current
`source and setting the control element of the one of the
`plurality of interface devices to an initial value;
`
`providing a trimming unit in the semiconductor device;
`
`using the trimming unit to acquire a measurement voltage
`produced by the measurement current in the one of the
`plurality of interface devices;
`
`using the trimming unit to compare the measurement voltage
`with a nominal voltage;
`
`based on a difference between the measurement voltage and the
`nominal voltage, setting the control element of the one of the
`plurality of interface devices to a trimming value at which the
`measurement voltage matches the nominal voltage; and
`
`acquiring the trimming value for the control element of the one
`of the plurality of interface devices.
`
`4
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`IPR2017-00382
`Patent 7,124,325 B2
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`Id. at 8:66–9:24.
`
`D. Asserted Grounds of Unpatentability
`
`Petitioner asserts that claims 1–20 are unpatentable, under 35
`
`U.S.C. § 103(a), based on the following grounds (Pet. 1):
`
`References
`
`Challenged Claims
`
`Tanaka2 and Ikehashi3
`Garrett4 and Hassoun5
`Garrett, Hassoun, and Ishikawa6
`
`1–20
`
`1, 8–14, 16, and 17
`
`2–7, 15, and 18–20
`
`As support, Petitioner proffers a Declaration of Dr. Nick Tredennick,
`
`who has been retained by Petitioner for the instant proceeding.
`
`Ex. 1002 ¶ 1–3.
`
`II. DISCUSSION
`
`A.
`
`Claim Construction
`
`Petitioner contends “[u]nder the broadest reasonable construction,
`
`Petitioner does not submit that any claim terms require a construction at this
`
`time.” Pet. 7. Patent Owner provides proposed constructions for “interface
`
`device,” “trimming,” “DRAM,” “DDRII,” and “settable control element.”
`
`Prelim. Resp. 11–23.
`
`
`
`2 U.S. Patent No. 7,000,160 B2, issued Feb. 14, 2006 (Ex. 1003) (“Tanaka”).
`3 U.S. Patent No. 6,643,180 B2, issued Nov. 4, 2003 (Ex. 1004)
`(“Ikehashi”).
`4 U.S. Patent No. 6,556,052 B2, issued Apr. 29, 2003 (Ex. 1005) (“Garrett”).
`5 U.S. Patent No. 5,844,913, issued Dec. 1, 1998, (Ex. 1006) (“Hassoun”).
`6 U.S. Patent No. 5,991,221, issued Nov. 23, 1999 (Ex. 1007) (“Ishikawa”).
`
`5
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`IPR2017-00382
`Patent 7,124,325 B2
`
`We address the Patent Owner’s contentions regarding the broadest
`
`reasonable interpretation of “interface device” below. For purposes of this
`
`Decision, we rely on Patent Owner’s representations that “DRAM” is an
`
`acronym for “dynamic random access memory” and “DDR” is an acronym
`
`for “double data rate.” Prelim. Resp. 20. We determine no other term
`
`requires express interpretation for purposes of this Decision. See Wellman,
`
`Inc. v. Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011) (“[C]laim
`
`terms need only be construed ‘to the extent necessary to resolve the
`
`controversy’”) (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
`
`F.3d 795, 803 (Fed. Cir. 1999)).
`
`1.
`
`Principles of Law
`
`In an inter partes review, we construe claim terms in an unexpired
`
`patent according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b).
`
`Consistent with the broadest reasonable construction, claim terms are
`
`presumed to have their ordinary and customary meaning as understood by a
`
`person of ordinary skill in the art in the context of the entire patent
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`2007).
`
`2.
`
`“interface device”
`
`We turn to the broadest reasonable interpretation of “interface
`
`device,” recited in independent claim 14 and “interface devices,” recited in
`
`independent claim 1. The disputes between the parties regarding the
`
`teachings of the asserted art pertain to the meaning of “interface” and
`
`whether “one of the plurality of interface devices,” recited in claim 1, and
`
`6
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`IPR2017-00382
`Patent 7,124,325 B2
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`“said interface device,” recited in claim 14, pertain to one of the interface
`
`devices. The disputes between the parties, however, do not hinge on the
`
`meaning of “device” or “devices.”
`
`With respect to the dispute pertaining to “interface,” Patent Owner
`
`characterizes the trimming identified by Petitioner in its element-by-element
`
`unpatentability analysis as being “deep within a memory device” (Prelim.
`
`Resp. 1), whereas “the ‘interface device’ is associated with an interface
`
`between the semiconductor device and something external to the
`
`semiconductor device” (id. at 14). With respect to whether “one of the
`
`plurality of interface devices,” recited in claim 1 and “said interface device,”
`
`recited in claim 14, pertain to one of the interface devices, Patent Owner
`
`contends a measurement identified by Petitioner is “between two alleged
`
`interface devices,” rather than “on the identified interface device,” as recited,
`
`for example, in claim 14. Id. at 55.
`
`We turn to Patent Owner’s contentions regarding “interface.” Id. at
`
`11–20. Patent Owner argues, with supporting evidence, that a person having
`
`ordinary skill in the art at the time of the invention would have understood
`
`that “the relevant ‘interface’ is between the semiconductor device, on one
`
`hand, and another device external to the semiconductor device, on the other
`
`hand.” Id. at 17 (citing Ex. 2001 (defining “interface” as “electronic
`
`circuitry used to connect two or more devices”); Ex. 2002 (defining
`
`“interface” as a “connection between two hardware devices”); Ex. 2003
`
`(defining “interface as “[a] device or software program that connects two
`
`separate entities.”)). Patent Owner also argues that the ’325 Patent
`
`Specification describes “interface devices” consistent with this ordinary
`
`meaning, for example, by depicting interface devices 10a–10d at the
`
`7
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`IPR2017-00382
`Patent 7,124,325 B2
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`external boundary of semiconductor device 1 and describing output drivers
`
`and terminations as examples of interface devices. Id. at 15–17 (citing Ex.
`
`1001, [54], [57], 1:36–62, 3:18–21, 5:24–27, 6:27–34, 6:66–7:12, Figs. 1–3).
`
`Petitioner contends that no claim terms require express construction at
`
`this time. Pet. 7. However, in its overview of the ’325 Patent, Petitioner
`
`acknowledges that output drivers and terminations are exemplary “interface
`
`devices” contending “[i]nterface devices, like output drivers and
`
`terminations [ ], have parameters that affect reading and writing from a data
`
`bus.” Id. at 3 (citing Ex. 1001, 1:36–41, 3:18–21). Additionally, Dr.
`
`Tredennick testifies that “interface devices include output drivers and
`
`terminations.” Ex. 1002 ¶ 16.
`
`Consistent with Patent Owner’s contentions (Prelim. Resp. 15–17),
`
`the ’325 Patent describes that “[i]t is accordingly an object of the invention
`
`to provide a semiconductor device and a method for trimming interface
`
`devices of the semiconductor device, which overcome the above-mentioned
`
`disadvantages of the prior art” (id. at 3:13–16) and describes as background
`
`“[f]or ordinary DDRII memory systems, it is normally not possible to trim
`
`the interface parameters” (id. at 2:18–19). Also, the ’325 Patent is entitled
`
`“METHOD AND APPARATUS FOR INTERNALLY TRIMMING
`
`OUTPUT DRIVERS AND TERMINATIONS IN SEMICONDUCTOR
`
`DEVICES.” Id. at [54] (emphasis added). Additionally, as acknowledged
`
`by Petitioner (Pet. 3; Ex. 1002 ¶ 16), the ’325 Patent Specification describes
`
`“[t]wo of the interface devices are output driver devices 10a, 10b” and “[t]he
`
`two other interface devices are termination devices 10c, 10d.” Ex. 1001,
`
`6:64–67. Furthermore, according to the ’325 Patent Specification, an
`
`interface device is connected to an interface connection (id. at 3:37–38, Figs.
`
`8
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`IPR2017-00382
`Patent 7,124,325 B2
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`1–3), which is in the form of a contact area (id. at 7:48–49) and interface
`
`devices are illustrated at the external boundary of the semiconductor device
`
`(see, e.g., id. at Fig. 3). Given the specification’s consistent usage of the
`
`term “interface device,” we are persuaded by Patent Owner’s contentions
`
`regarding “interface.”
`
`We now turn to Patent Owner’s contention regarding whether “one of
`
`the plurality of interface devices,” recited in claim 1, and “said interface
`
`device,” recited in claim 14, pertain to one of the interface devices. Prelim.
`
`Resp. 55. Claim 1 recites acquiring “a measurement voltage produced by
`
`the measurement current in the one of the plurality of interface devices,”
`
`which is used to set a trimming value. Ex. 1001, 9:13–22. Claim 14 recites
`
`“writing to said trimming register based on a measured variable detected on
`
`said interface device.” Id. at 10:30–32. Patent Owner’s contention (Prelim.
`
`Resp. 55) is consistent with the portions of the ’325 Patent Specification
`
`discussed above because performing the measurement with respect to one
`
`interface device is a prerequisite for trimming that interface device.
`
`Additionally, Patent Owner’s contention is consistent with other
`
`descriptions in the ’325 Patent Specification. For example, the ’325 Patent
`
`Specification describes that “trimming unit 5 is switchably connected to
`
`each driver device which is to be trimmed” (Ex. 1001, 7:64–65) and “[o]ne
`
`of the interface devices 10a–10d is now trimmed by taking the measurement
`
`voltage” (id. at 8:12–13). In addition to not providing proposed
`
`constructions for any claim terms, Petitioner does not offer guidance,
`
`explicitly or implicitly, as to how these phrases should be interpreted, other
`
`than to identify the specific examples set forth above.
`
`9
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`IPR2017-00382
`Patent 7,124,325 B2
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`On this record, we are persuaded by Patent Owner’s contentions that
`
`the broadest reasonable interpretation of “interface” in the context of the
`
`’325 Patent Specification is “between the semiconductor device” and
`
`“another device external to the semiconductor device” (Prelim. Resp. 17)
`
`and “interface device” is “associated with an interface” (id. at 14). We
`
`further are persuaded that “one of the plurality of interface devices,” recited
`
`in claim 1, and “said interface device,” recited in claim 14, pertain to one of
`
`the interface devices. Patent Owner proffers alternate interpretations of the
`
`term “interface devices.” Prelim. Resp. 18–20. As the aforementioned
`
`determinations are sufficient to resolve the disputes between the parties, we
`
`need not construe expressly other terms for purposes of this Decision.
`
`B.
`
`Principles of Law (Obviousness)
`
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`
`differences between the claimed subject matter and the prior art are such that
`
`the subject matter, as a whole, would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`(2007). The question of obviousness is resolved on the basis of underlying
`
`factual determinations, including: (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of skill in the art; and (4) objective evidence of nonobviousness,
`
`i.e., secondary considerations. Graham v. John Deere Co., 383 U.S. 1, 17–
`
`18 (1966).
`
`10
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`IPR2017-00382
`Patent 7,124,325 B2
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`C.
`
`Person of Ordinary Skill in the Art
`
`Petitioner proposes that a person of ordinary skill in the art would
`
`have had a Bachelor’s degree in Electrical Engineering and at least 2 years
`
`of experience working in the field of semiconductor logic design. Ex.
`
`1002 ¶ 13. Patent Owner does not dispute Petitioner’s proposal. See
`
`generally Prelim. Resp. For purposes of this Decision, we adopt Petitioner’s
`
`assessment of the level of ordinary skill in the art.
`
`D. Obviousness over Tanaka and Ikehashi (Claims 1–20)
`
`Petitioner contends each of claims 1–20 is unpatentable, under 35
`
`U.S.C. § 103(a), over the combined teachings of Tanaka and Ikehashi.
`
`1.
`
`Overview of Tanaka
`
`Tanaka is directed to trimming techniques for semiconductor
`
`integrated circuits. Ex. 1003, 1:5–8. Tanaka teaches a circuit configuration
`
`for voltage trimming (id. at 10:51–52) as well as a modified configuration
`
`for circuit trimming (id. at 12:57–60).
`
`2.
`
`Overview of Ikehashi
`
`Ikehashi is directed to a method of testing a semiconductor memory.
`
`Ex. 1004, [57]. Ikehashi teaches trimming voltages generated by an internal
`
`voltage generator circuit. Id. at 11:7–10. More specifically, Ikehashi
`
`teaches trimming a reference voltage Vref, an internal fall voltage Vdd, and
`
`a non-selected cell work line voltage Vread. Id. at 11:7–12.
`
`11
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`IPR2017-00382
`Patent 7,124,325 B2
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`3.
`
`Discussion of Claim 1
`
`We begin our analysis with independent claim 1. Claim 1 is directed
`
`to a method for trimming interface devices of a semiconductor device
`
`comprising nine steps. Ex. 1001, 8:66–9:12. The method of claim 1
`
`requires connecting a current source in a test apparatus to one of the
`
`interface devices, controlling a measurement current produced by the current
`
`source, and setting a control element of the interface device to an initial
`
`value. Id. at 9:4–11. The method of claim 1 additionally requires using a
`
`trimming unit in the semiconductor device to acquire a measurement
`
`voltage, performing a comparison with that measurement voltage, and, based
`
`on that comparison, setting the control element of the interface device to a
`
`trimming value. Id. at 9:12–22. Petitioner’s contentions are deficient for
`
`two reasons: (1) the Petition does not show sufficiently how or why a
`
`person having ordinary skill in the art would have combined or modified the
`
`teachings identified in Tanaka and Ikehashi in the manner recited in claim 1;
`
`and (2) the Petition does not show sufficiently that the combination of
`
`Tanaka and Ikehashi teaches “interface devices,” as recited in claim 1.
`
`Turning to the first deficiency, claim 1 recites nine method steps. For
`
`three of these steps, Petitioner points to Tanaka’s teachings relating to
`
`current trimming. Pet. 31–33 (citing Ex. 1003, 13:2–5, 13:6–17, 19:6–9,
`
`Fig. 12). For the remaining method steps recited in claim 1, Petitioner
`
`points to Tanaka’s or, alternatively, Ikehashi’s teachings relating to voltage
`
`trimming. Pet. 37–43 (citing Ex. 1003, 10:58–11:12, 11:27–57, Fig. 4; Ex.
`
`1004, 16:11–24, 15:47–50, 16:11–20, Fig. 16).
`
`Petitioner provides insufficient explanation as to how or why a person
`
`having ordinary skill in the art would have combined or modified the
`
`12
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`IPR2017-00382
`Patent 7,124,325 B2
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`teachings relating to current trimming and those relating to voltage
`
`trimming. Although Petitioner relies on teachings of Tanaka for both
`
`current trimming and voltage trimming, these teachings relate to two
`
`separate, alternative embodiments. More specifically, Tanaka teaches that
`
`Figure 4 “shows an example of a circuit configuration for voltage
`
`trimming,” (Ex. 1003, 10:51–52), whereas Figure 12 shows “another
`
`modification of the arrangement shown in FIG. 4” for “current trimming”
`
`(id. at 12:57–60).
`
`Petitioner’s explanation regarding the combination of Tanaka’s
`
`current and voltage trimming embodiments is set forth below.
`
`Although Figure 12 relates to an embodiment showing
`“circuit trimming” rather than voltage trimming, Tanaka states
`that “[t]he same trimming procedure as that in the case of the
`arrangement shown in Fig. 4 [for voltage trimming] is used to
`obtain the same effect.” Ex. 1003, 12:57–13:19; see also id.,
`19:6–9. Thus, to the extent Patent Owner argues that Figures 4
`and 12 (and related disclosures) are directed to different
`embodiments within Tanaka, Petitioner submits that Fig. 12
`integrates and thus discloses this aspect of Fig. 4, and Petitioner
`alternatively submits that it would have been obvious to a
`POSITA to combine this aspect of Fig. 4 into Fig. 12, given the
`referenced equivalence. Ex. 1002 ¶¶ 61–62.
`
`Pet. 33, n. 4 (emphasis added).
`
`Petitioner’s reliance on Tanaka’s statement that “[t]he same trimming
`
`procedure as that in the case of the arrangement shown in Fig. 4” (id.) is
`
`misplaced because it pertains to teachings not relied on by Petitioner. More
`
`specifically, Petitioner points to Tanaka’s Figure 4 teachings for using the
`
`trimming unit to arrive at a trimming value. See, e.g., Pet. 37–43 (citing Ex.
`
`1003, 10:58–11:12, 11:27–57). Tanaka’s statement that “[t]he same
`
`trimming procedure as that in the case of the arrangement shown in Fig. 4 is
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`13
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`used to obtain the same effect” (Ex. 1003, 13:17–19) pertains to CPU
`
`functions performed after the trimming value is obtained (id. at 11:16–21).
`
`Regarding Petitioner’s contention that “Fig. 12 integrates and thus
`
`discloses this aspect of Fig. 4, and Petitioner alternatively submits that it
`
`would have been obvious to a POSITA to combine this aspect of Fig. 4 into
`
`Fig. 12,” and to the extent that Petitioner contends something other than the
`
`CPU procedure is integrated, the Petition is too vague as to what aspect of
`
`Figure 4 Petitioner contends is integrated with Figure 12. We, therefore, are
`
`not persuaded that Tanaka discloses the steps recited in claim 1, in the
`
`manner claimed. Petitioner’s alternative submission that the integration
`
`would have been obvious relies on the same statement of Tanaka discussed
`
`above and is not persuasive for the same reasons. We, therefore, are not
`
`persuaded by Petitioner that Tanaka teaches or suggests the elements recited
`
`in claim 1 and, because Petitioner does not offer further persuasive
`
`explanation regarding why or how these embodiments would have been
`
`combined or modified by a person of ordinary skill in the art, we also are not
`
`persuaded by Petitioner’s obviousness contention.
`
`Regarding Petitioner’s remaining contentions, including those relating
`
`to Ikehashi, we agree with Patent Owner’s contention that “Challenge 1 is
`
`two anticipation challenges improperly paired together and presented as a
`
`single obviousness challenge.” Prelim. Resp. 1. For instance, Petitioner’s
`
`identification of teachings relating to Tanaka’s Figure 4 and, alternatively,
`
`Ikehashi’s Figure 16 with respect to method steps pertaining to using the
`
`trimming unit to arrive at a trimming value, are presented as two alternative
`
`grounds, one based on Tanaka and the other based on Ikehashi. Petitioner,
`
`however, points to only Tanaka’s teachings relating to Figure 12 for the
`
`14
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`method steps of connecting a current source in a test apparatus to one of the
`
`interface devices and controlling a measurement current produced by the
`
`current source, recited in claim 1. Pet. 31–33 (citing Ex. 1003, 13:2–5,
`
`13:6–17, 19:6–9, Fig. 12). Petitioner does not provide sufficient explanation
`
`as to how or why a person having ordinary skill in the art would have
`
`combined or modified Tanaka’s teachings relating to current trimming with
`
`any of the teachings relating to voltage trimming.
`
`“An invention is not obvious just ‘because all of the elements that
`
`comprise the invention were known in the prior art;’ rather, a finding of
`
`obviousness at the time of invention requires a plausible rational[e] as to
`
`why the prior art references would have worked together.” Broadcom Corp.
`
`v. Emulex Corp., 732 F.3d 1325, 1335 (Fed. Cir. 2013) (emphasis added).
`
`Citing to two embodiments in the same reference does not explain how or
`
`why a person having ordinary skill in the art would have combined the
`
`teachings relating to those two embodiments. See, e.g., Jacket Int’l Ltd. v.
`
`Admar Int’l Ltd., Case IPR2015-00979 (PTAB May 20, 2016) (Paper 21).
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`We now turn to the second deficiency, i.e., the Petition does not show
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`sufficiently that the combination of Tanaka and Ikehashi teaches “interface
`
`devices,” as recited in claim 1. Petitioner contends Tanaka and Ikehashi
`
`disclose alternative interface devices. Pet. 11–16, 31.
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`Regarding Tanaka, Petitioner contends “[t]he disclosed interface
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`device comprises timing controller 50 and boosting circuit 6 (items 60–66 in
`
`Fig. 4).” Id. at 12. Petitioner also contends that flash memory chip 5A
`
`contains timing controller 50 that generates operating voltages such as write
`
`voltage and erase voltage. Id. at 11 (citing Ex. 1003, 17:23–36).
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`15
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`Patent 7,124,325 B2
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`Alternatively, Petitioner contends “Ikehashi discloses that the
`
`semiconductor has a plurality of interface devices, for example, Figure 1
`
`shows control logic that manages buffers and registers in order to read from
`
`and write to memory.” Pet. 13–14 (citing Ex. 1004, 8:60–10:18, Fig. 1).
`
`Petitioner also contends “[t]he interface device also includes part of voltage
`
`generator circuit 20, which ‘generates a variety of voltages for use in
`
`chips.’” Id. at 14 (citing Ex. 1004, 9:51–56).
`
`The components identified by Petitioner (id. at 11–14) in both Tanaka
`
`and Ikehashi are involved in timing and voltage boosting or generation for
`
`reading from and writing to internal memory. See, e.g., Ex. 1003, 17:14–17
`
`(“The flash memory chip 5A has a boosting circuit 6A and a trimming
`
`circuit 7A. The boosting circuit 6A generates a high voltage Vpp necessary
`
`for write and erase and supplies the high voltage Vpp to a timing controller
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`(TCNT) 50.”); Ex. 1004, 9:51–62 (“An internal voltage generator circuit 20
`
`generates a variety for voltages for use in chips . . . A timer circuit 22
`
`generates a variety of timing pulses used when a variety of voltages are
`
`generated.”). However, we determine that the Petition lacks a requisite
`
`showing that these components are associated with an interface under the
`
`broadest reasonable interpretation of that term, which as discussed above is
`
`“between the semiconductor device and another device external to the
`
`semiconductor device.”
`
`Accordingly, we determine that Petitioner has not shown sufficiently
`
`that either Tanaka or Ikehashi teaches the interface devices recited in claim
`
`1. Petitioner also does not propose a combination of Tanaka and Ikehashi
`
`teachings with respect to “a plurality of interface devices,” recited in claim
`
`1.
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`16
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`IPR2017-00382
`Patent 7,124,325 B2
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`For the reasons given, we determine that Petitioner has not shown
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`sufficient basis for instituting trial on the ground that claim 1 is
`
`unpatentable, under 35 U.S.C. § 103(a), over Tanaka and Ikehashi.
`
`4.
`
`Discussion of Independent Claim 14
`
`Independent claim 14 is similar to claim 1 in that it recites a
`
`semiconductor device comprising at least one interface device and a
`
`trimming unit, connected to the interface device, for writing to a trimming
`
`register based on a variable detected on the interface device. Ex. 1001,
`
`10:26–34. In its contentions for “interface devices” recited in claim 1,
`
`Petitioner references back to its contentions for claim 14. Pet. 31 (citing Pet.
`
`11–16).
`
`As discussed above, the Petition does not show sufficiently that the
`
`combination of Tanaka and Ikehashi teaches “interface devices,” as recited
`
`in claim 1. For the same reasons, the Petitioner does not show sufficiently
`
`that the combination of Tanaka and Ikehashi teaches “interface device,” as
`
`recited in claim 14. The Petition does not include further contentions for
`
`claim 14 that remedy the deficiencies noted above.
`
`For the reasons given, we determine that Petitioner has not shown
`
`sufficient basis for instituting trial on the ground that claim 14 is
`
`unpatentable, under 35 U.S.C. § 103(a), over Tanaka and Ikehashi.
`
`5.
`
`Discussion of Dependent Claims 2–13 and 15–20
`
`Each of claims 2–13 and 15–20 depends, directly or indirectly, from
`
`claim 1 or claim 14. Petitioner does not provide for these claims any
`
`argument or evidence overcoming the deficiency we note above for claims 1
`
`and 14. Pet. 28–30, 44–56. For the reasons given, we determine that
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`17
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`IPR2017-00382
`Patent 7,124,325 B2
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`Petitioner has not shown sufficient basis for instituting trial on the ground
`
`that claims 2–13 and 15–20 are unpatentable, under 35 U.S.C. § 103(a), over
`
`Tanaka and Ikehashi.
`
`6.
`
`Conclusion
`
`Having reviewed the Petition and Preliminary Response, and the
`
`evidence cited therein, we are not persuaded that Petitioner has established a
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`reasonable likelihood that it would prevail in showing that claims 1–20 are
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`unpatentable, under 35 U.S.C. § 103(a), over Tanaka and Ikehashi.
`
`E. Obviousness over Garrett and Hassoun
`(Claims 1, 8–14, 16, and 17)
`
`Petitioner contends claims 1, 8–14, 16, and 17 are unpatentable, under
`
`35 U.S.C. § 103(a), as obvious over the combined teachings of Garrett and
`
`Hassoun. Pet. 1.
`
`1. Overview of Garrett
`
`Garrett is directed to a semiconductor controller device to control the
`
`operation of a semiconductor memory device. Ex. 1005, [57]. Garrett
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`teaches a current control technique for interfacing with DRAMs. Id. at
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`2:61–64.
`
`2.
`
`Overview of Hassoun
`
`Hassoun is directed to a test device for an integrated circuit. Ex. 1006,
`
`[57]. Hassoun teaches a variable current source with a control input that
`
`provides a test signal. Id. at 4:34–37.
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`18
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`IPR2017-00382
`Patent 7,124,325 B2
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`3.
`
`Discussion of Claim 1
`
`We begin our analysis with claim 1. Petitioner’s contentions are
`
`deficient for two reasons: (1) the Petition does not show sufficiently how or
`
`why a person having ordinary skill in the art would have combined or
`
`modified the teachings identified in Garrett and Hassoun; and (2) the
`
`Petition does not show sufficiently that the combination of Garrett and
`
`Hassoun teaches “using the trimming unit to acquire a measurement voltage
`
`produced by the measurement current in the one of the plurality of interface
`
`devices,” as recited in claim 1.
`
`Turning to the first deficiency, as discussed above, claim 1 is directed
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`to a method for trimming interface devices of a semiconductor device
`
`comprising nine steps, including steps requiring controlling a measurement
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`current produced by a current source in a test apparatus to set initial
`
`parameters and steps of using a trimming unit to arrive at a trimming value.
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`Ex. 1001, 8:66–9:12. Petitioner relies on only Garrett’s teachings for most
`
`of the limitations of claim 1, except for steps involving the test apparatus
`
`having a current source. Pet. 67–77. For the test apparatus having a current
`
`source, Petitioner points to teachings of Garrett and Hassoun. Id. at 68–72.
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`First as to Garrett, we are not persuaded that that claim 1 would have
`
`been obvious to one having ordinary skill in the art over the teachings of
`
`Garrett alone. For instance, we are not persuaded that Petitioner has shown
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`sufficiently that Garrett teaches a test apparatus having a current source.
`
`Petitioner contends “Garrett discloses a test apparatus having a current
`
`source” because “[a] POSITA would have understood that disclosure of a
`
`reference voltage from an external source, like a test apparatus, discloses a
`
`current source in the external test apparatus, because a current source is
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`19
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`IPR2017-00382
`Patent 7,124,325 B2
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`commonly used in forming reference voltages for test purposes.” Pet. 68
`
`(citing Ex. 1005, 13:1–3, 14:27–29, 8:10–11; Ex. 1002 ¶¶ 110–11). In the
`
`portions of Garrett identified by Petitioner (id.), however, Garrett does not
`
`specifically refer to a test apparatus or a current source. Instead, Garrett
`
`teaches providing a reference voltage from an external source (Ex. 1005,
`
`13:1–3, 14:27–29), such as “a band-gap reference circuit, or a voltage
`
`divider or another voltage supply” (id. at 8:10–13). Dr. Tredennick testifies
`
`that such a test apparatus having a current source would have been “well-
`
`known in the art,” but does not provide sufficient explanation or supporting
`
`evidence as to why Garrett alone teaches the test apparatus having a current
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`source. Ex. 1002 ¶¶ 110–11 (Ex. 1005, 13:1–3, 14:27–29, 8:10–11; Ex.
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`1006, 1:7–10, 4:34–37). Based on the record before us, we are not
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`persuaded that Dr. Tredennick’s testimony remedies the deficiency of the
`
`teachings of Garrett alone.
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`In contrast, consistent with Petitioner’s contentions (Pet. 68 (citing
`
`Ex. 1006, 4:34–37; Fig. 3)), Hassoun teaches that Figure 3 illustrates a
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`schematic “of an interface circuit for a test device” (Ex. 1006, 3:22–24)
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`having “variable current source 44” (id. at 34). The Petition, however,
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