United States Patent
`Gridley
`
`[19]
`
`[54] DISTRIBUTED PROCESSING ETHERNET
`SWITCH WITH ADAPTIVE CUT-THROUGH
`SWITCHING
`
`[75]
`
`Inventor: Curtis D. Gridley, Ayer, Mass.
`
`[73] Assignee: Amber Wave Systems, Inc., Acton,
`Mass.
`
`[21] Appl. No.: 304,769
`Sep. 12, 1994
`
`[22] Filed:
`Int. Cl.6
`............•........................................... H04J 3/22
`[51]
`[52] U.S. Cl . ............................. 370/58.2; 370/60; 370/61;
`370/94.1
`[58] Field of Search ........................... 370/60, 58.2, 58.3,
`370/61, 67, 68.1, 85.13, 92, 94.1, 124,
`13, 17
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,719,621
`5,165,021
`5,274,631
`5,307,345
`5,321,695
`
`111988 May .......................................... 370/61
`11/1992 Wu et al .............................. 370/85.13
`12/1993 Bhardwaj .................................. 370/60
`4/1994 Lozowick et al ......................... 370/61
`6/1994 Faulk, Jr. . ................................. 370/60
`
`OTHER PUBLICATIONS
`
`Kwok et al., "Cut-Through Bridging for CSMNCD Local
`Area Networks", IEEE Transactions on Comm., vol. 38, No.
`7, Jul. 1990, pp. 938-942.
`
`1111111111111111111111111111111111111 IIIII 111111111111111111111 11111111 1111
`US005521913A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,521,913
`May 28, 1996
`
`Primary Examiner-Alpus H. Hsu
`Assistant Examiner-Ricky Ngo
`Attorney, Agent, or Firm-Hamilton, Brook, Smith & Rey(cid:173)
`nolds
`
`[57]
`
`ABSTRACT
`
`A packet switching system includes at least two network
`cards each receiving data packets via a plurality of associ(cid:173)
`ated ports, a system card, and an interconnect for connecting
`the system card to the network cards. Each one of the
`network cards comprises a plurality of port controllers for
`sending and receiving packets to and from a corresponding
`port and a packet processor for buffering packets received by
`the port controllers. The packet processor then sends desti(cid:173)
`nation addresses to the system card via the interconnect and
`receives forwarding information from the system card. The
`processor then forwards the packet in response to the
`forwarding information. The processor begins forwarding
`the packet in response to the forwarding information before
`the packet has been entirely received and checks the integ(cid:173)
`rity of the packet by reference to check sum information
`contained in the packet as in cut-through switching. Future
`packets from the source port have their validity checked
`prior to forwarding in response to receiving an invalid
`packet from the source port as in store and forward switch(cid:173)
`ing.
`
`13 Claims, 4 Drawing Sheets
`
`Port #I
`
`Port #8
`
`Activity, Coli is ion
`and Link LEOs
`
`•
`•
`•
`LAN Controller Bus
`
`135
`
`Packet
`RAM
`
`Hardware
`Packet
`Processor
`
`\
`125
`
`100
`
`HIGH SPEED BACKPLANE
`
`20
`
`NETAPP ET AL. EXHIBIT 1004
`Page 1 of 10
`
`

`
`U.S. Patent
`
`May 28, 1996
`
`Sheet 1 of 4
`
`5,521,913
`
`Pl-PS Pl-P8 Pl--P8 Pl--P8
`I II I l I l I
`I I I II II 1
`Ill Ill 11
`llllll r 1
`LAN
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`Card
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`20
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`Card
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`
`NETAPP ET AL. EXHIBIT 1004
`Page 2 of 10
`
`

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`ond Link LEOs
`Activity, Coli is ion
`
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`
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`Pocket
`
`135......._____
`
`f
`#8
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`LAN
`I
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`
`LAN Controller Bus
`•
`
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`IIOf
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`Port #8
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`Port #I
`
`NETAPP ET AL. EXHIBIT 1004
`Page 3 of 10
`
`

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`~ w
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`
`FIG. 3
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`HIGH SPEED BACKPLANE
`
`215
`
`v
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`I FIFO
`~/
`
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`
`f ~
`
`7
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`Arbitration
`210------., Backplane
`
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`
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`Address
`
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`
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`and LEOs
`Serial Port
`
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`
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`
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`~
`
`A
`
`Processor
`Management
`
`NETAPP ET AL. EXHIBIT 1004
`Page 4 of 10
`
`

`
`U.S. Patent
`
`May 28, 1996
`
`Sheet 4 of 4
`
`5,521,913
`
`--..
`
`Accumulate
`Packet
`
`v 405
`
`Send Packet
`Header to
`System Card
`
`v 410
`
`Begin
`Forwarding to
`Destination Card
`
`v
`
`415
`
`'
`Determine
`Validity
`of Packet
`
`~ 420
`
`1
`
`425
`
`Vol id Pocket?
`
`No
`
`Accumulate v 430
`Next Packet
`
`lr
`Check Vol id ity v 435
`ot Pocket
`
`Forward if Valid/ v
`Drop if Invalid
`
`440
`
`Yes
`
`~
`
`No
`
`~ 445
`n Con-
`ve Valid -
`
`Poe kets ?
`
`FIG. 4
`
`NETAPP ET AL. EXHIBIT 1004
`Page 5 of 10
`
`

`
`5,521,913
`
`2
`SUMMARY OF THE INVENTION
`
`1
`DISTRIBUTED PROCESSING ETHERNET
`SWITCH WITH ADAPTIVE CUT-THROUGH
`SWITCHING
`
`BACKGROUND OF THE INVENTION
`
`5
`
`The present invention is directed to a distributed process(cid:173)
`ing archecture which yields most of the simplicity of the
`shared memory configuration while attaining the advantages
`and faster operation of multiprocessing configuration. In
`general, this is achieved by a packet switching system that
`includes at least two network cards each receiving data
`packets via a plurality of associated ports, a system card, and
`an interconnect for connecting the system card to the net(cid:173)
`work cards. Each one of the network cards comprises a
`plurality of port controllers for sending and receiving pack(cid:173)
`ets to and from a corresponding port and a packet processor
`for buffering packets received by the port controllers. The
`packet processor then sends destination addresses to the
`system card via the interconnect and receives forwarding
`information from the system card. The processor then for(cid:173)
`wards the packet in response to the forwarding information.
`In specific embodiments, the system card comprises an
`address look-up table correlating destination addresses with
`the ports of the system. Also, the packet is forwarded to a
`different one of the network cards indicated by the forward(cid:173)
`ing information via the interconnect.
`The packet processor can be a hardware processor or even
`a programmable gate array.
`In yet another embodiment, the processor begins forward(cid:173)
`ing the packet in response to the forwarding information
`before the packet has been entirely received and checks the
`validity of the packet by reference to check sum information
`30 contained in the packet. Future packets from the source port
`have their validity checked prior to forwarding in response
`to receiving an invalid packet from the source port.
`In general, according to another aspect, the invention
`features an adaptive cut-through switching method for a
`packet switching system receiving and sending data from
`and to a network via a plurality of ports. This method
`comprises forwarding received packets to destination ports
`before the packet has been entirely received as in standard
`cut-through switching. The validity of the packets is, how(cid:173)
`ever, checked after the fact. If it turns out that the packet was
`invalid, future packets from the port are stored and their
`validity checked prior to forwarding, a store and forward
`configuration.
`In specific embodiments, the integrity of the packets is
`checked by reference to check sum information contained in
`the packets.
`In other embodiments, only packets, having source
`addresses from which invalid packets have been previously
`received, are placed into a store and forward mode. Alter(cid:173)
`natively, every packet from a port can be placed on store and
`forward in response to receiving an invalid packet from that
`port, regardless of its source address.
`The above and other features of the invention including
`various novel details of construction and combinations of
`parts, and other advantages, will now be more particularly
`described with reference to the accompanying drawings and
`pointed out in the claims. It will be understood that the
`particular method and device embodying the invention is
`shown by way of illustration and not as a limitation of the
`invention. The principles and features of this invention may
`be employed and various and numerous embodiments with(cid:173)
`out the departing from the scope of the invention.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`20
`
`10
`
`15
`
`Ethernet switch architecture can be generally divided into
`two classes: shared memory and multiprocessor systems. In
`the shared memory architecture, packets, including a header
`with a source and destination addresses, a data payload, and
`a check sum portion at the end of the packet, are received at
`the ports and then forwarded to a system card via a back(cid:173)
`plane. Here, the packets are buffered in the same central
`memory, which is accessed by a single central controller.
`This controller looks at the destination address of the packet,
`and possibly other information such as source port and
`destination port, and then, via an address and other look-up
`tables, determines what should be done with the packet, such
`as forward, discard, translate or multicast. This forwarding
`decision is usually an identification of a LAN Card and a
`port of that LAN Card in the Ethernet switch that connects
`to the destination address. The address look-up table tells to
`which port of the Ethernet switch the packet must be sent to
`reach the addressed device. The packet is then forwarded to 25
`that LAN card. The designated LAN card receives the
`packet and routes it to the destination port where an Ethernet
`controller chip sends the packet out on the LAN to the
`addressed device.
`The multiprocessing architecture differs in that a local
`processor is placed on each one of the cards and each one of
`these processors accesses and maintains its own address
`table. As a result, when a multiprocessor-type LAN card
`receives a packet through one of its ports, it first looks at the
`destination address and then determines to which one of the 35
`other ports on one of the other cards it must be sent and then
`sends the packet to that card via the backplane connecting
`the cards. If the port address of the packet happens to be on
`the same LAN card it was received on, the processor simply
`sends the packet to that local port address and the packet is 40
`never transferred on the backplane. This architecture has
`certain advantages in that since functionality is replicated
`between the cards, if any one of the cards should fail the
`Ethernet switch can still function although this also
`increases cost. One problem is, however, that a substantial 45
`amount of processing and software is devoted to ensuring
`the address tables on each one of the LAN cards are exact
`duplicates of each other.
`Regarding the handling of the packet within the Ethernet
`switch, two basic methods are conventional. The first is 50
`called store and forward switching. In this switching
`scheme, a particular LAN card will wait until it has received
`the entire packet before forwarding it to either another LAN
`card or the central controller card. This allows the LAN card
`to confirm the packet is valid and uncorrupted by reference 55
`to the check sum information contained at the end of the
`packet. A new approach has been proposed which is called
`cut-through switching, a purpose of which is to decrease
`packet latency. Here, not yet fully received packets are
`forwarded to the destination port and begun to be sent out or 60
`broadcasted from the switch before the entire packet has
`been received. This both decreases packet latency and also
`decreases the amount of buffering RAM required by each
`LAN card. The problem with this approach, however, is that
`if the packet turns out to be invalid or corrupted there is no 65
`way to drop the packet since it is already been started to its
`destination.
`
`In the accompanying drawings, like reference numerals
`refer to the same parts throughout the different views. The
`
`NETAPP ET AL. EXHIBIT 1004
`Page 6 of 10
`
`

`
`5,521,913
`
`3
`drawings are not necessarily to scale and this has instead
`been placed upon illustrating the principles of the invention.
`Of the drawings:
`FIG. 1 is a block diagram illustrating tbe general layout of
`the Ethernet switch of the present invention;
`FIG. 2 is a block diagram showing the architecture of a
`LAN card of the present invention;
`FIG. 3 is a block diagram illustrating the architecture of
`a system card of the present invention; and
`FIG. 4 is a flow diagram showing the process steps of
`adaptive cut-through switching of the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`25
`
`4
`ernet packets with a LAN card and port address of the
`Ethernet switch. In other words, the look-up tables in the
`address RAM 225 indicates to which port P1-P8 of which
`LAN card lOOA-lOOD a particular packet must be for-
`5 warded to reach the device indicated by the destination
`address contained in that packet's header.
`The forwarding decision indicating the internal LAN card
`and port address obtained from the address look-up table in
`the address RAM 225 by the address processor 220 is sent
`10 via the address processor bus 235 through the processor(cid:173)
`backplane FIFO 215 and backplane 20 to the requesting
`LAN card 100.
`Additionally, the system card 200 also contains a system
`controller which monitors the operation of each one of the
`15 LAN cards 100A-100D via the backplane 20 and the status
`of the address look-up table contained in the address RAM
`225 via the address processor bus 235 through the manage(cid:173)
`ment-address FIFO 240. Generally, the system controller
`230 monitors the health of the Ethernet switch in general,
`20 such as the crashing or improper operation of any one of the
`LAN cards. It also keeps system statistics regarding
`throughput and packets destinations and sources along with
`any security considerations. Although, not explicitly shown,
`a backup system card can be included to increase switch
`reliability by adding central control redundancy.
`Returning to FIG. 2, the forwarding decision is received
`by the hardware packet processor 130 via the backplane 20
`through the packet-backplane FIFO 140 and the packet bus
`125. If the port destination of the packet happens to be local
`to the particular card, then the packet is transferred to the
`LAN controller bus 105 via the controller-packet FIFO 120
`to one of the LAN controllers 110A-110H for the designated
`port. If, however, the port destination lies on a different LAN
`card 100A-100D, then the packet is transferred via the
`backplane 20 to the designated LAN card where the hard-
`ware packet processor 130 of that LAN card transfers the
`packet to the proper LAN controller 110 on that card.
`The present invention generally obtains the advantages
`associated with the multiprocessing architecture while main(cid:173)
`taining the simplicity associated with the shared memory
`architecture. One of the problems associated with the shared
`memory architecture is that the entire packet including the
`data payload must traverse the backplane twice. The packet
`traverses the backplane when it is first sent from the receiv(cid:173)
`ing LAN card to the control card and then when it leaves the
`control card to go to the particular LAN card which has the
`address port. In the multiprocessing architecture, the packet
`is only transferred across the backplane when it must be sent
`to a different LAN card. Consequently, in some cases, the
`packet may never enter the backplane in situations in which
`the source and destination ports are located in the same LAN
`card. The present distributed processing architecture
`achieves much of the advantages in this realm as th€
`55 multiprocessing architecture since the packet's data payload
`is only transferred across the backplane at most once. It
`should be noted, however, that the multiprocessing systems
`do not have to transfer the header across the backplane to
`obtain a forwarding decision. But, the multiprocessing con-
`figuration requires significant intercard traffic to synchronize
`the information look-up tables, which is not necessary in the
`present invention.
`One advantage of the shared memory architecture has
`over the multiprocessing architecture is one of simplicity. In
`the multiprocessing architecture, substantial intelligence
`must be incorporated into each LAN card to maintain and
`update the local address look-up table in addition to coor-
`
`Turning now to the figures, the internal architecture of an
`Ethernet switch constructed according to the principles of
`the present invention is generally illustrated in FIG. 1. Here,
`four LAN cards 100A-100D each have eight Ethernet ports
`P1-P8 for sending and receiving Ethernet packets. Although
`four LAN cards are shown specifically, it is generally
`understood that the number of LAN cards is expandable
`depending upon system requirements and capabilities. Each
`of these LAN cards 100A-100D are connected to each other
`and a system card 200 via a highspeed backplane 20.
`Although a backplane interconnect 20 is shown, other inter(cid:173)
`connects are possible such as crossbar or hierarchial types.
`Referring to FIG. 2, a block diagram illustrating the
`internal architecture of the LAN cards is shown. Each LAN 30
`controller 110A-110H sends and receives packets to and
`from the eight ports, port P1-P8. Data received into any one
`of the ports, P1-P8, is sent out onto the LAN controller bus
`105 to a controller-packet bus bidirectional FIFO (first in,
`first out) buffer 120. A 'port controller 115 coordinates the 35
`reading and writing by each of the LAN controllers
`110A-110H and the FIFO 120 to ensure that no data
`collisions occur on the LAN controller bus 105 and to drive
`LED indicators on the card to show port activity. The
`bi-directional FIFO 120 transfers the data from the LAN 40
`controller bus 105 to the packet bus 125 where a hardware
`packet processor 130, preferably a programmable gate array
`or specialty hardware processor, reconstructs the packets in
`a high speed packet RAM 135. The packet RAM 135 serves
`as a packet buffer which stores the packets received in 45
`through each of the ports P1-P8 while the packet processor
`130 obtains forwarding decisions, such as discard, translate,
`multicast, or forward to a destination LAN card and port,
`from the system card 200. More specifically, the hardware
`packet processor 130 sends the packet header, which 50
`includes source and destination addresses of the received
`packets now stored in the packet RAM 135, to the system
`card 200 on the backplane 20 via the packet-backplane FIFO
`140.
`Referring to FIG. 3, the system card 200 receives packet
`source and destination addresses from each of the LAN
`cards 100A-100D via the backplane 20. A backplane arbiter
`and controller 210 controls access to the backplane 20 by
`each of the LAN cards to avoid data collisions on the
`backplane 20. Packet source and destination information is
`received from the backplane 20 into the system card 200 via
`a processor-backplane FIFO 215. Generally, an address
`processor 220, such as a TMS320 signal processor, updates
`and accesses an address RAM 225 which contains an
`address look-up table and other forwarding related decision
`tables including port states. Generally, the address look-up
`table correlates destination addresses contained in the Eth-
`
`60
`
`65
`
`NETAPP ET AL. EXHIBIT 1004
`Page 7 of 10
`
`

`
`5,521,913
`
`10
`
`5
`dinating between the LAN cards to ensure that the look-up
`tables are all identical. Here, the intelligence located on each
`LAN card is only that needed to buffer the packet when it is
`received, strip off the header and send it to the system card,
`then receive back the LAN card destination and port, and 5
`then send the packet to that LAN card or perform other
`forwarding decision related processing. As a result, the
`present invention achieves most of the efficiency of the
`multiprocessing schemes with cost effectiveness associated
`with the shared memory architecture.
`Adaptive Cut-Through Switching
`Turning now to FIG. 4, an adaptive cut-through switching
`process is described with reference to the hardware archi(cid:173)
`tecture shown in FIGS. 1-3. Packets received in through the
`ports P1-P8 of a LAN card 100 are accumulated in the 15
`packet RAM 135 under control of the packet processor 130
`in step 405. As soon as the header of a particular packet has
`been completely received, the packet processor 130 sends
`the header information via the backplane to the address
`processor 220 contained on the system card 200 step 410. 20
`The address processor 220 returns the forwarding decision
`to the packet processor 130. The packet processor 130 then
`begins forwarding the not yet fully received packet con(cid:173)
`tained in the packet RAM 135 to the packet processor of the
`destination LAN card in step 415 where the packet is started 25
`to be sent out the destination port to the addressed device.
`This occurs before the packet is fully received at the source
`port. In this way, the present invention operates somewhat
`the same as convention cut-through switching structures.
`The packet processor, however, checks the validity of the 30
`packet once the check-sum information has been received in
`step 420 even though the packet is already on its way to its
`destination device. If it turns out that the packet was in fact
`valid, the particular port remains in a cut-through switching
`status in which the packets are forwarded as soon as the 35
`forwarding decision is received by returning to step 405. If,
`however, it turns out that the packet was invalid, then the
`entire port is placed in a probationary status of the store and
`forward mode in the preferred embodiment. Alternatively,
`only the packets of the particular source address that exhibit 40
`invalidity or corruption could be placed into a store and
`forward mode, rather than the entire port. This second
`approach is most applicable where a particular sending
`device, rather than the cabling, is the basis of the packet
`corruption.
`A port placed on probation is essentially converted to the
`store and forward switching. That is, as the packet is
`received through the LAN controller of the port, which has
`been placed on probation, the entire packet is accumulated
`in the packet RAM 135 in step 430 and its validity checked so
`by reference to the check sum in step 435 before it is
`forwarded to its destination card and port in step 440. If it
`turns out the packet is invalid then the packet processor 130
`simply discards that packet without forwarding it. Finally, in
`step 445, the packet processor determines whether ten 55
`consecutive valid packets have been received from a par(cid:173)
`ticular port. If ten consecutive valid packets have been
`received, the port is removed from probationary status and
`returned to a cut-through configuration.
`The present invention essentially yields the advantages 60
`associated with both cut-through switching and store and
`forward switching. That is, in a properly operating local area
`network, most of the packets will in fact be valid and the
`latency associated with the check sum checking is unnec(cid:173)
`essary. In most cases, the present invention entirely avoids 65
`this latency by essentially defaulting to cut-through switch(cid:173)
`ing as long as the transmission rate of the destination port is
`
`45
`
`6
`less than or equal to the rate of the source port. For a
`particular port receiving garbage either through the improper
`operation of a device attached to that port or some corruption
`in the cabling in that port, the present invention insulates the
`rest of the LAN by placing that port, or in some situations
`only packets with a particular source address, in a store and
`forward mode so that invalid packets will be dropped before
`they are forwarded or broadcasted through the LAN. Certain
`types of packets such as broadcast packets are always placed
`in a store and forward mode, however, since they involve
`every port. This helps to avoid broadcast storms.
`Equivalents
`Those skilled in the art will recognize, or be able to
`ascertain using no more than routine experimentation, many
`equivalents to specific embodiments of the invention
`described specifically herein. Such equivalents are intended
`to be encompassed in the scope of the following claims.
`I claim:
`1. A packet switching system including at least two
`network cards each receiving data packets via a plurality of
`associated ports, a system card, and an interconnect for
`connecting the system card to the network cards, wherein
`each one of the network cards comprises:
`a plurality of port controllers for sending and receiving
`packets to and from a corresponding port;
`a packet processor for buffering packets received by the
`port controllers and sending destination addresses of
`the received packets to the system card via the inter(cid:173)
`connect, for receiving forwarding information from the
`system card, and for forwarding the packets in response
`to the forwarding information;
`a controller bus connecting the port controllers to the
`packet processor; and
`a bus controller coordinating communications between
`the packet processor and the port controllers over the
`controller bus.
`2. The system of claim 1, wherein the system card
`comprises an address look-up table correlating destination
`addresses with the ports of the system.
`3. The system of claim 1, wherein the packet is forwarded
`to a different one of the network cards indicated by the
`forwarding information via the interconnect.
`4. The system of claim 1, wherein the packet processor is
`a hardware processor.
`5. The system of claim 1, wherein the packet processor is
`a programmable gate array.
`6. The system of claim 1, wherein the packet processor
`begins forwarding the packet in response to the forwarding
`information before the packet has been entirely received,
`checks a validity of the packet in response to check sum
`information contained in the packet, and stores future pack(cid:173)
`ets from the source port and checks the packets validity prior
`to forwarding in response to receiving an invalid packet
`from the source port.
`7. An adaptive cut-through switching method for a packet
`switching system receiving and sending packets from and to
`a network via a plurality of ports, the method comprising:
`receiving packets in the packet switching system; gener(cid:173)
`ating forwarding
`information in response to the
`received packets; forwarding the received packets to
`destination ports in response to the forwarding infor-
`mation before the packets have been entirely received;
`checking the validity of the packets by reference to check
`sum information contained in the received packets;
`storing future packets from a port and checking the
`validity of the future packets prior to forwarding in
`
`NETAPP ET AL. EXHIBIT 1004
`Page 8 of 10
`
`

`
`5,521,913
`
`7
`response to receiving an invalid packet from the port as
`determined in the checking step.
`8. The method of claim 7, further comprising storing and
`checking validity prior to forwarding only for packets hav(cid:173)
`ing source addresses from which invalid packets have been 5
`received.
`9. The method of claim 7, further comprising storing and
`checking validity prior to forwarding every packet from a
`port in response to receiving an invalid packet from that
`port.
`10. A packet switching method for a packet switching
`system that receives packets from source devices via ports
`and transmits the packets from the ports connecting to
`destination devices, the method comprising:
`receiving packets from ports connected to source devices,
`the packets being addressed to destination devices
`connected to different ports;
`moving the packets within the system and then transmit(cid:173)
`ting the packets to the destination devices via the ports
`even though the packets have not been entirely received
`through the ports from the source devices;
`
`20
`
`8
`checking the validity of the packets after the packets have
`at least begun to be transmitted from the system to the
`destination devices via the ports; and
`converting to store-and-forward switching in response to
`determining that one of the packets was invalid to
`confirm the validity of the packets before transmitting
`the packets from the system to the destination devices.
`11. A method as described in claim 10, further comprising
`10 store-and-forward switching all packets received from a port
`in response to receiving an invalid packet from the port.
`12. A method as described in claim 10, further comprising
`store-and-forward switching only packets from a particular
`source device in response to receiving invalid packets from
`that source device.
`13. A method as described in claim 10, further comprising
`converting back to transmitting packets to destination
`devices before the packets have been entirely received in
`response to receiving valid packets.
`
`15
`
`* * * * *
`
`NETAPP ET AL. EXHIBIT 1004
`Page 9 of 10
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`5,521,913
`May 28, 1996
`Curtis D. Gridley
`
`PATENT NO.
`
`DATED
`INVENTOR(S) :
`
`It is certified that error appears in the above-indentified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`Delete the second paragraph in Claim 7, Column 6, lines
`58-62, and replace it with the following:
`
`---receiving packets in the packet switching
`system;
`generating forwarding information in response to
`the received packets;
`
`forwarding the received packets to destination
`ports in response to the forwarding information before
`the packets have been entirely received;---
`
`Signed and Sealed this
`
`Sixth Day of August, 1996
`
`Attest:
`
`Attesting Officer
`
`Commissioner of Patents and Trademarks
`
`BRUCE LEHMAN
`
`NETAPP ET AL. EXHIBIT 1004
`Page 10 of 10