UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`______________________
`
`NetApp, Inc., and Lenovo (United States), Inc.
`
`Petitioners
`
`
`
`v.
`
`
`
`Intellectual Ventures II, LLC
`
`Patent Owner
`
`______________________
`
`
`U.S. PATENT NO. 6,516,442
`______________________
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`
`
`DECLARATION OF MR. IAN JESTICE
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` 1
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`NETAPP ET AL. EXHIBIT 1006
`Page 1 of 52
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`______________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`______________________
`
`NetApp, Inc., and Lenovo (United States), Inc.
`
`Petitioners
`
`
`
`v.
`
`
`
`Intellectual Ventures II, LLC
`
`Patent Owner
`
`______________________
`
`
`U.S. PATENT NO. 6,516,442
`______________________
`
`
`
`DECLARATION OF MR. IAN JESTICE
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`
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` 1
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`NETAPP ET AL. EXHIBIT 1006
`Page 1 of 52
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`I, Ian Jestice, do hereby declare and say:
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`1.
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`I am over the age of twenty-one (21) and competent to make this
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`declaration. I am also qualified to give testimony under oath. The facts and
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`opinions listed below are within my personal knowledge.
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`2.
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`I am being compensated for my time in this proceeding at my standard
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`consulting rate of $325/hr. My compensation in no way depends on the
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`outcome of this proceeding or the content of my opinions. I am not employed
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`by, nor receiving grant support from, Petitioners in this matter. I am receiving
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`compensation from Petitioners solely for my involvement in this matter and
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`based only on my standard hourly consulting fees.
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`3.
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`I have been asked to review certain documents, including U.S. Patent No.
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`6,516,442 (which I refer to as the ’442 Patent) (Ex. 1001), and to provide my
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`opinions on what those documents disclose. I was also asked to review and
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`provide opinions regarding U.S. Patent Nos. 6,968,459 and 6,633,945, which I
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`understand is involved in litigation alongside the ’442 Patent. I have provided
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`an opinion specific to that patent in a separate declaration.
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`4.
`
`I have reviewed and am familiar with the following documents:
`
`a.
`
`U.S. Patent No. 4,845,722 to Kent et al. (Ex. 1002)
`
`b.
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`Excerpts from a book titled “Computer Networks” by
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`Andrew Tanenbaum (Ex. 1003)
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`c.
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`U.S. Patent No. 5,311,114 to Sambamurthy et al. (Ex. 1005)
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`d.
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`U.S. Patent No. 5,521,913 to Gridley (Ex. 1004)
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`e.
`
`f.
`
`Terry Ritter, “The Great CRC Mystery” (Ex. 1013)
`
`Ross Williams, “A Painless Guide to CRC Error Detection
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`Algorithms” (Ex. 1014)
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`g. W. Peterson and D. Brown, “Cyclic Codes for Error
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`Detection” (Ex. 1015)
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`5.
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`I provide my conclusions regarding the disclosures of the documents I
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`reviewed as applied to the ’442 Patent below. I am not offering any conclusions
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`as to the ultimate determinations I understand the Patent Trial and Appeal Board
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`will make in this proceeding. Specifically, I am not offering opinions on
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`ultimate issues of validity or claim construction. I am simply providing my
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`opinions on the technical aspects of the documents as compared to the claims of
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`the ’442 Patent as a factual matter and on the combinability of the concepts
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`disclosed in those documents from a technical perspective.
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`BACKGROUND
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`6.
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`I hold the equivalent of an undergraduate degree in Telecommunications
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`and Computer Science from the City and Guilds Institute of London, which I
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`obtained in 1971.
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`7.
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`As described in more detail in my curriculum vitae (Ex. 1007) I have
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`more than 40 years of industry experience with storage devices, embedded
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`software systems for industry and consumer products, and other systems
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`including Flash Memory (Solid State Disks, memory cards, flash drives),
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`Optical Storage (CD, DVD, WORM, Magneto-Optical), Magnetic Storage
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`(Hard Disk, Floppy Disk, Tape), RAID/Disk Arrays and jukeboxes; USB, SCSI,
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`iSCSI, IDE/ATA/ATAPI/SATA, Fibre Channel, PCMCIA, game programming,
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`home appliances and telecommunications.
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`8.
`
`As part of my experience, I have worked as a design and systems
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`engineer at Amdahl Corporation, IBM and Fujitsu, designing, building, testing
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`and supporting Multi-Processor hardware and software.
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`9.
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`I have been familiar with the field of multiprocessing systems,
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`specifically symmetric multiprocessing systems, over at least the past 30 years.
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`For these reasons and because of my technical experience and training as
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`outlined in my curriculum vitae (Ex. 1007), I believe I am capable of offering
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`technical opinions regarding the ’442 Patent and the other documents I
`
`reviewed as part of my work in this matter. I believe I am capable of opining
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`about the state of the art in these areas at various points in time from the early
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`1970s to the present.
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`LEVEL OF SKILL IN THE ART
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`10.
`
`I understand that one of the relevant factors in this proceeding is the level
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`of skill in the pertinent art. I understand that the pertinent date for this
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`determination is date of alleged invention. For purposes of this declaration, I
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`have been asked to assume that the date of invention for the ’442 Patent is
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`December 7, 1997.
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`11.
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`In my opinion, a person of ordinary skill in the art as of December 7,
`
`1997 would have had a bachelor’s degree in computer science, computer
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`engineering, or the equivalent, and would have had at least four years of
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`experience designing, testing or implementing with multi-processing computer
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`systems.
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`12. The multi-processor systems field was a relatively specialized field as it
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`would have required understanding of both conventional hardware and software
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`techniques at the time. Individuals focused on writing operating systems in
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`1999 for example, would not have had the requisite understanding of the
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`hardware requirements. Further, individuals developing the physical computer
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`systems would not have been familiar with the software considerations
`
`associated with cache consistency.
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`13. Accordingly, a person of ordinary skill would understand how multi-
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`processor systems could be built, would recognize potential pitfalls in various
`
`design choices of both hardware and software solutions, and would understand
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`how to research the state of the industry as well as academic research in the
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`area.
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`14.
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`I believe I am qualified as a person of skill in the art in December 7, 1997
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`because I had the requisite understanding of both the hardware and software
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`issues present in a system described in the ’442 Patent. Furthermore, I believe
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`that I can opine today about what those of skill in the art would have known and
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`understood as of December 7, 1997.
`
`The ’442 Patent
`
`15. The ’442 Patent was filed on March 30, 1999 and issued on February 4,
`
`2003. Ex. 1001 at cover. The ’442 Patent describes a multiprocessor system
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`that includes a switched fabric or switch matrix for data transfers between
`
`processors and shared memory. Ex. 1001 at Abstract.
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`16. The ’442 Patent states that the “traditional approach” to multiprocessor
`
`systems is to provide uniform access to memory over a shared system bus. Ex.
`
`1001 at 1:17-22. The ’442 Patent states that serial availability of the shared bus
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`limited the scalability of the multiprocessor system. Ex. 1001 at 1:30-40. The
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`’442 Patent states that the preferred embodiment of the alleged invention is a
`
`multiprocessor system which includes a switch fabric (switch matrix) with
`
`multiple concurrent buses between processors and shared memory. Ex. 1001 at
`
`1:49-53.
`
`17. Figure 2 of the ’442 Patent shows an overview of the multiprocessor
`
`system. The system includes a central Flow-Control Unit (FCU) 220 that
`
`implements a switched fabric data path architecture. Ex. 1001 at 2:44-52. The
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`system also contains eight processors 120. Id. at 2:47-49.
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`18. Point-to-point interconnects 112, 113, and 114 and associated protocol
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`define dedicated communication channels for all FCU input and output. Ex.
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`1001 at 2:52-54. In Figure 2, eight channels are used to connect CPU Channel
`
`Units (CCUs, also known as Channel Interface Units or CIUs); two channels are
`
`used to connect Bus Bridge Units (BBUs) 240; and four channels are used to
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`connect Memory Control Units (MCUs) 230. Ex. 1001 at 2:54-3:5; 3:17-20.
`
`19. Figure 3 of the ’442 Patent provides a detailed view of the switched
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`fabric data path architecture within the FCU. Ex. 1001 at 5:25-27. The
`
`components of the FCU include a transaction controller, an address and control
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`bus, and a data switch composed of vertical buses, horizontal buses, and node
`
`switches. Ex. 1001 at 5:27-37. The FCU also includes several types of
`
`interfaces: Initiator Interfaces, a Memory Interface, and Channel Interface
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`Blocks at the periphery of the Initiator Interfaces and the Memory Interface. Ex.
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`1001 at 5:38-41.
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`20. The Channel Interface Blocks (CIBs) provide a logical interface to a
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`interconnect channels 112, 113, and 114. Ex. 1001 at 6:49-52. Packets are
`
`transported over the channels and exchanged between CIBs. Ex. 1001 at 6:52-
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`55; 7:38-47.
`
`21. Packets contain 8 bits of ECC, which stands for Error Correction Code.
`
`Ex. 1001 at 6:60. The ’442 Patent states that the ECC provides error detection
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`coverage over the full packet. Ex. 1001 at 16:51-56. The ’442 Patent states that
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`“[a]lthough the error detection code actually does provide information for single
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`bit error correction, this is not used for Channel data. Instead the data transfer is
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`retried using the transport retry protocol.” Id.
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`22. The receive side of the CIB logic receives data from the Channel,
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`transmits it to core logic, and checks the ECC field. Ex. 1001 at 19:39-45. If an
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`ECC error is detected, the CIB notifies core logic that the data is not valid, and
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`the CIB logic is put into “error retry” mode. Id. at 19:47-56.
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`23. Once an error has been received by a CIB, its transport protocol receiving
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`state machine will throw away the packet that indicated an error. Ex. 1001 at
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`21:57-59. Once the receive FIFO has more than 8 empty slots, the transport
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`protocol will send a TC_SYNC to the originating CIB (the CIB that transmitted
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`the packet in error). Id. at 21:66-22:1. Upon receiving the TC_SYNC, the
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`originating CIB retries the transmission. Id. at 13:52-59.
`
`Kent (US Pat. No. 4,845,722)
`
`24.
`
`I reviewed U.S. Patent No. 4,845,722 listing Allan R. Kent and others as
`
`inventors (“Kent,” Ex. 1002) which issued on July 4, 1989. The Kent patent
`
`describes a computer interconnect coupler that employs crossbar switching.
`
`Kent at Title and Abstract. The coupler serves to link various conventional
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`computer systems and memory devices together as shown in Figure 1.
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`25. A conventional computer system includes a memory, an input-output
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`device, and a data processor. Kent at 1:15-26. In the conventional “small
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`computer system,” these various components and a power supply are mounted
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`within a cabinet. Kent at 1:27-45. These various components are interconnected
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`by a “back plane” which contains a number of parallel connectors or buses. Id.
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`The buses convey addresses, data, control signals, status signals, and power. Id.
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`Multiple processors may be used in a conventional computer system and housed
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`in a single computer cabinet. Kent at 1:46-56.
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`26. The computer system typically included at least one port for mass
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`memory such as floppy disc drive, tape drive, or a hard disc drive. Kent at 1:41-
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`45. In addition, external memory devices may also be used and were typically
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`controlled by a “server.” Kent at 1:56-61.
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`27. Kent states that in “recent years,” i.e. circa 1987, a need arose for
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`computation and data storage capabilities that exceeded those provided by a few
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`data processors. Kent at 1:62-64. To address that need, Kent states that it was
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`possible to construct computer networks where a number of conventional
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`computers and mass memory devices located at different locations were
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`interconnected to communicate with each other. Kent at 1:64-2:8.
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`28. Kent states that there were numerous information transfer schemes which
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`could be used for communications among data processing devices in a network
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`and specifically mentions the Ethernet communication standard as especially
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`useful. Kent at 2:9-55. Ethernet is a packet based networking protocol.
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`29. Kent states that reliable data transmission is especially important in
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`computer networks having a shared data base. Kent at 3:9-16. Collisions of data
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`packets or other transmission errors are detected by an error detecting code such
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`as cyclic redundancy check. Kent, 3:28-30.
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`30. Kent states that if a data processing device correctly receives a data
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`packet, the data processing device immediately acknowledges receipt of that
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`packet by sending a positive acknowledgement code (ACK). Kent at 3:31-36. If
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`the packet was received but could not be processed, i.e. an error occurred in
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`processing the packet, then the processing device returns a negative
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`acknowledgement code (NAK). Kent at 3:36-42. Kent states that one reason to
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`send a NAK would be the unavailability of a buffer. Kent at 3:38-42. As
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`discussed below, another reason to send a NAK is a failed CRC check. If a data
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`processing device fails to receive an ACK immediately after transmission of a
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`data packet or receives a NAK, the data processing device will attempt to
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`retransmit the data packet for a number of times. Kent at 3:51-52.
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`31. Kent states that prior art data couplers that interconnected data processing
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`devices lacked bandwidth and flexibility in adding additional channels. Kent at
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`4:13-38. Therefore, the goal of the invention in the Kent Patent was to provide
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`an improved computer interconnect coupler which provided increased
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`connectivity and bandwidth but did not require substantial modification to
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`existing computer equipment. Kent at 4:41-45.
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`32. Figure 1 shows the coupler, actually two identical couplers 51 and 52 for
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`enhanced reliability, linking together numerous data processing devices, such as
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`individual computers with CPUs (labelled 54, 55, 56, 57, and 58) and servers
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`(labelled 59 and 60) for mass storage devices. Kent at 7:53-8:2. The coupler
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`permits any one data processing unit (i.e. CPUs or mass storage servers) to send
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`an addressed data packet to any other processing unit in the system. Kent at
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`8:11-14.
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`33. Kent describes the coupler as a “two-stage electronic crossbar switch”
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`that is capable of “interconnecting at least 64 channels.” Kent at 8:30-38. The
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`channel is a communication path, e.g. a communication path defined by
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`communication cable 81, from the coupler to a data processing device (i.e.
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`CPUs or mass storage servers). Kent at 8:45-51. The communication cable
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`could either be a pair of coaxial cables or a pair of fiber optic lines. Kent at
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`12:11-17. Figure 1 of Kent shows 7 channels: 2 channels connecting mass
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`storage servers 59 and 60 and 5 channels connecting CPUs 54, 55, 56, 57, and
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`58, connected to coupler 51 (and another 7 channels connecting the duplicate
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`coupler 52.)
`
`34. Figure 2 of Kent shows two generic channels: X and Y, that is, Figure 2
`
`applies to any two channels of the coupler. Figure 2 illustrates the channels at
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`the coupler end of the channel with communication cables 81 and 85 connected
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`to channel interface circuits 82 and 83 of the coupler. Kent at 8:45-51. One of
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`skill in the art would understand that a corresponding setup would exist at the
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`data processing device end of these channels. That is, the data processing device
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`(i.e. CPUs or mass storage servers) will also have channel interface circuits to
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`connect the communication cables.
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`35. Figure 2 of Kent also illustrates the routing of a message from source
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`channel X to destination channel Y through the coupler. The message takes the
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`form of a packet shown in Figure 12. This message (data packet) includes
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`header sequences for synchronization, a byte indicating whether the packet is a
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`data message or an acknowledgement, a byte indicating the length of the
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`message, destination channel, source channel, data, a cyclic redundancy check
`
`(CRC), and a trailer. Kent at 21:59-22:5. The message (data packet) is
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`preferably transmitted as a serial bit stream using Manchester encoding. Kent at
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`12:26-30.
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`36. Referring to Figures 2 and 4 of Kent, a message (data packet) is received
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`by interface circuits 82 and then passed to receiver logic circuits 84, e.g. fed into
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`a first-in-first-out buffer 143 to provide temporary storage during routing of the
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`message. Kent at 8:52-62; 12:38-40. The receiver logic obtains the destination
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`address from the packet and determines if the message header conforms to a
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`predetermined format. Kent at 12:40-44. The receiver logic then sends a service
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`request to the central switch logic to route the message. Kent at 12:44-46.
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`37. Routing the message involves assigning a junctor and closing switches in
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`switch matrices. Kent at 8:62-9:12. The crossbar switch architecture of the
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`coupler illustrated in Figure 2 contains two switch matrices 87 and 90. (Figure 2
`
`also illustrates a diagnostic switch matrix 99 which is not relevant to the IPR
`
`petition.) Figure 2 also illustrates two junctors that interconnect switches in the
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`switch matrices with the top junctor 88 interconnecting switches 89, 96, 95, and
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`91. In the preferred embodiment, the coupler has eight independent junctors.
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`Kent at 8:33-34. As shown in Figure 2, in the process of routing the data packet
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`from channel X to channel Y, junctor 88 is assigned and switches 89 and 91 are
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`closed. Kent at 8:68-9:12.
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`38. After the junctor is assigned, the packet is clocked out of FIFO buffer 143
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`and the packet is transmitted in serial form to the destination processing device.
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`Kent at 13:36-55; 9:15-19. When the destination processing device receives the
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`data packet, it returns an acknowledgement. Kent at 9:20-22. One of ordinary
`
`skill in the art would understand that this acknowledgement can either be a
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`positive acknowledgement (ACK) or a negative acknowledgement (NAK). Kent
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`at 3:31-42. The acknowledgement is received by the coupler, routed through the
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`reversed junctor, and transmitted via channel X to the processing device that
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`sent the data packet. Kent at 13:61-65; 9:20-37.
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`Computer Networks Textbook
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`39.
`
`I have reviewed select pages of a book titled “Computer Network” (3rd
`
`edition) by Andrew Tanenbaum published in 1996. Computer Networks is
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`undergraduate level textbook on computer networks.
`
`40. Chapter 3 of Tanenbaum textbook concerns the data link layer and “deals
`
`with algorithms for achieving reliable, efficient communication between two
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`adjacent machines.” Tanenbaum at 175. As taught by Tanenbaum, transmission
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`of a bit stream over a communication channel does not guarantee that the bit
`
`stream is error free. “It is up to the data link layer to detect, and if necessary,
`
`correct errors.” Tanenbaum at 179. Again from Tanenbaum:
`
`“The usual approach is for the data link layer to break the bit
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`stream up into discrete frames and compute the checksum for each
`
`frame. … When a frame arrives at the destination, the checksum is
`
`recomputed. If the newly computed checksum is different from the
`
`one contained in the frame, the data link layer knows that an error
`
`has occurred and takes steps to deal with it (e.g. discarding the bad
`
`frame and sending back an error report.)” Tanenbaum at 179.
`
`41. Tanenbaum teaches that a checksum in widespread use is the polynomial
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`code known as a cyclic redundancy code or CRC code. Tanenbaum at 187. As
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`discussed in Tanenbaum the CRC code is used to detect errors that occur in the
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`frame data. Tanenbaum at 187-190.
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`42. The “error report” comes in the form of positive or negative
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`acknowledgements:
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`“The usual way to ensure reliable delivery is to provide the sender
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`with some feedback about what is happening at the other end of the
`
`line. Typically the protocol calls for receiver to send back special
`
`control frames bearing positive or negative acknowledgements
`
`about the incoming frames. If the sender receives a positive
`
`acknowledgement about a frame, it knows the frame has arrived
`
`safely. On the other hand, a negative acknowledgement means that
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`something has gone wrong, and the frame must be transmitted
`
`again.” Tanenbaum at 182.
`
`43. On the use of negative acknowledgements or NAKs, Tanenbaum teaches
`
`a specific strategy called selective repeat. Tanenbaum at 215. In selective
`
`repeat, whenever the receiver has reason to suspect that an error has occurred, it
`
`sends a negative acknowledgement frame back to the sender, which operates as
`
`“a request for retransmission of the frame specified in the NAK.” Tanenbaum at
`
`215. One of ordinary skill in the art would understand that other protocols can
`
`be envisioned using NAKs. The basic concept is that NAKs are used to report to
`
`the sender that something went wrong in the transmission and that a frame or
`
`frames must be retransmitted.
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`Motivation to Combine Kent with Disclosures in the Computer Networks
`Textbook
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`44. While Kent states that the packets being routed through the coupler have
`
`a CRC code, Kent was mainly focused on the details of the coupler and does not
`
`discuss how the CRC code is used other than to state that “[c]ollisions of data
`
`packets or other transmission errors are detected by an error detecting code as a
`
`cyclic redundancy check [CRC].” Kent at 3:27-30. But Kent does state that
`
`reliable data transmission is especially important to a system. Kent at 3:9-10.
`
`45. To further understand how the CRC code works, one or ordinary skill in
`
`the art would have referred to one of many reference books or textbooks
`
`describing the cyclic redundancy check codes and how they are used to achieve
`
`reliable communications such as the Computer Networks textbook by Andrew
`
`Tanenbaum. The Kent patent describes a network to interconnect computers to
`
`shared memory devices and mentions that conventional communication network
`
`known as “Ethernet” may be used, the Kent patent does not get into the
`
`specifics on how a communication network such as Ethernet delivers reliable
`
`communications or how the ACKs and NAKs described in Kent are used in a
`
`communication protocol other than to state that CRC is used to detect errors and
`
`that if a packet could not be processed a NAK is returned. Kent at 2:49-55;
`
`3:27-38.
`
`46. The Tanenbaum textbook fills in the details missing from the Kent patent
`
`in describing the basic characteristics of a link layer in a network protocol that
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`would be familiar to one of ordinary skill in the art. Since the Kent patent
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`stresses the importance of reliable communications, but leaves it to one of
`
`ordinary skill in the art to supply the missing details on how reliable
`
`communications are achieved, one of ordinary skill in the art would have known
`
`to look to link layer protocols as taught by Tanenbaum to provide reliable
`
`communications. Kent at 3:9-10 and Tanenbaum at 175. Kent also discloses
`
`packets with a CRC code which the Tanenbaum reference teaches can be used
`
`detect errors in a scheme for reliable transmission. Kent at Figure 12 and
`
`Tanenbaum at 187-190. Finally, the Kent patent discloses the ability of the
`
`handle transmissions of ACKs and NAKs packets, which one of ordinary skill
`
`in the art would recognize can be used as part of the scheme of reliable
`
`transmissions. Kent at 14:47-54 and Tanenbaum at 182. Specifically, the NAKs
`
`could be used to report errors in packets and request retransmission. Tanenbaum
`
`at 182.
`
`Gridley (US Pat. No. 5,521,913)
`
`47.
`
`I reviewed U.S. Patent No. 5,521,913 listing Curtis D. Gridley as inventor
`
`(“Gridley,” Ex. 1004) which issued on May 28, 1996. The Gridley Patent
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`describes an improved packet switching system. Gridley at Abstract.
`
`48. Gridley describes two basic conventional methods for handling packets
`
`within an Ethernet switch: store-and-forward switching and cut-through
`
`switching. Gridley at 1:49-59. In store-and-forward switching the switch or the
`
`
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`17
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`LAN card in the switch will wait until receiving the entire packet before
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`forwarding the packet to either the destination LAN card or a central controller
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`card within the switch. Gridley at 1:51-54. This type of switching allows the
`
`receiving LAN card to confirm the packet is valid and uncorrupted by checking
`
`the packet check sum information at the end of the packet, i.e. the CRC code of
`
`an Ethernet packet. Gridley at 1:54-57. As Gridley suggests, store-and-forward
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`switching introduces latency since the packet must be completely received
`
`before being forwarded.
`
`49. To decrease packet latency, a “new” approach was proposed called cut-
`
`through switching. Gridley at 1:57-58. In cut-through switching, the packet
`
`information is forwarded to the destination port and transmitted before the
`
`packet has been fully received. Gridley at 1:59-62. This type of switching
`
`introduced very little latency because packet information is forwarded as soon
`
`as it is received, but since the CRC code is at the end of the packet, the packet’s
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`validity could not be checked before the packet had already started being
`
`transmitted to its destination. Gridley at 1:62-67. Therefore, as Gridley states,
`
`there was no way for the switch to drop the packet, i.e. no way for the switch to
`
`stop the transmission of an invalid packet to the destination device. Id.
`
`50. The Gridley Patent teaches a hybrid of cut-through and store-and-forward
`
`switching called adaptive cut-through switching. Gridley at 5:9-59. In adaptive
`
`cut-through switching, incoming packets are accumulated in memory. Gridley
`
`
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`at 5:14-17. In addition, the packet information is forwarded to destination port
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`and to the destination device before the packet is fully received, thus acting like
`
`a cut-through switch. Gridley at 5:22-29. But, unlike cut-through switching, the
`
`validity of the packet is checked once the check-sum information, i.e. CRC
`
`code, of the packet has been received. Gridley at 5:30-33.
`
`51.
`
`If the packet is valid, the port remains in cut-through switching mode.
`
`Gridley at 5:33-36. If the packet is invalid, the port is placed in store-and-
`
`forward mode which essentially converts the port to store-and-forward
`
`switching. Gridley at 5:36-47. In store-and-forward mode, the entire packet is
`
`accumulated in memory and its validity is checked before forwarding the packet
`
`to the destination port. Gridley at 5:47-52. Gridley teaches that if the packet is
`
`invalid in store-and-forward mode, the packet is discarded without forwarding.
`
`Id. at 5:52-54. The switch also monitors the port to determine if ten consecutive
`
`packets are received without error at which point the port is returned to cut-
`
`through switching.
`
`52. As Gridley states, adaptive cut-through switching yields the advantages
`
`associated with both cut-through and store-and-forward switching since most
`
`packets will be valid and will pass through the switch with minimal latency, but
`
`if a particular port is “receiving garbage” then adaptive cut-through switching
`
`allows the switch to drop invalid packets before they are forwarded onwards.
`
`Gridley at 5:60-6:11.
`
`
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`
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`Motivation to Combine Kent and the Computer Networks Textbook with
`Gridley
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`53. The coupler in Kent employs cut-through switching. See Kent at 12:64-
`
`13:10. For example, the coupler in Kent only stores the beginning of a message
`
`(packet) to obtain the destination address. Id. at 13:5-7. As discussed in Kent,
`
`the use of cut-through switching reduces latency so that the coupler “appears
`
`relatively transparent to the data processing devices.” Kent at 13:9-10.
`
`54. Although cut-through switching achieves low latency, one of ordinary
`
`skill in the art would have utilized the adaptive cut-through switching taught by
`
`Gridley as an improvement on the ordinary cut-through switching used in Kent.
`
`As Gridley states, adaptive cut-through switching yield advantages associated
`
`with both cut-through and store-and-forward switching. Gridley at 5:60-6:10.
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`Specifically, adaptive cut-through switching does not increase latency except
`
`for ports where invalid packets have been detected. Gridley at 5:63-65; ¶ 52
`
`above. But adaptive cut-through switching has the advantage of allowing the
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`switch to drop invalid packets instead of forwarding those invalid packets
`
`further.
`
`55. Of course, in implementing cut-through switching in the system of Kent,
`
`the invalid packets are not simply dropped at the switch, but rather, upon
`
`detecting an invalid packet, the switch will return a NAK to the transmitter of
`
`the packet to instruct the transmitter to resend the packet. See ¶¶ 40-42 above.
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`This procedure will save network bandwidth associated with transmitting an
`
`
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`invalid packet to the destination device and waiting for the destination device to
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`perform a CRC check and to send a NAK back to the switch. For example, the
`
`data flow through the coupler where an error occurs in transmitting a data
`
`packet from the source device to the coupler is as follows.
`
`Error
`
`Data packet
`
`NAK
`
`Same data packet
`
`Source
`
`Data packet
`
`NAK
`
`Same data packet
`
`Coupler
`
`
`Destination
`
`
`
`With the store-and-forward mode of cut-through switching, the coupler can
`
`eliminate the transmissions highlighted in red above by having the coupler
`
`perform the CRC check and send the NAK as illustrated below.
`
`Coupler
`
`
`Same data packet
`
`Destination
`
`Error
`
`Data packet
`
`NAK
`
`Same data packet
`
`Source
`
`
`
`56. One of ordinary skill in the art would have recognized the advantages to
`
`reducing wasted transmissions between the coupler and the destination device,
`
`when adaptive cut-through switching is implemented on the coupler disclosed in
`
`Kent. Further, adaptive cut-through switching is in line with the general goal of
`
`the Kent patent to provide a coupler with increased bandwidth since reducing
`
`wasted transmissions increases the bandwidth of that channel to handle other
`
`
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`non-wasteful transmissions. Kent at 4:41-45. Further, one of ordinary skill in
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`the art would have had an expectation of success in implementing the adaptive
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`cut-through switching taught by Gridley in the coupler of Kent. The switches
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`disclosed by Gridley and Kent have similar structures, both contain LAN cards
`
`or channel interface boards interconnected by high speed bus. See Figure 2 or
`
`Gridley and Figure 3 of Kent. Also, the circuitry for performing a CRC check to
`
`check for invalid packets is well known to one of ordinary skill in the art. See ¶
`
`91 below. To implement store-and-forward switching or adaptive cut-through
`
`switching on any packet network switch given the teaching in Gridley should be
`
`within the abilities of one of ordinary skill in the art.
`
`Sambamurthy (U.S. Pat. No. 5,311,114)
`
`57.
`
`I reviewed U.S. Patent No. 5,311,114 listing Namakkal S. Sambamurthy,
`
`Woo-Ping Lai, and John P. VanGilder as inventors (“Sambamurthy,” Ex. 1005)
`
`which issued on May 10, 1994. The Sambamurthy patent describes a method to
`
`achieve full-duplex Ethernet. Sambamurthy at Title and Abstract.
`
`58. Sambamurthy states the “currently,” i.e. at the time of filing the
`
`Sambamurthy patent circa 1992, Ethernet was a half-duplex protocol.
`
`Sambamurthy at 1:21-23. In the late 1980s, a new Ethernet media standard
`
`referred to as “10Base-T” was proposed and accepted.1 Id. at 1:38-39. The
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`10Base-T Ethernet standard employed two pairs of twisted-pair cables for its
`
`
`1 Sambamurthy states “late 1990s” which is likely a typographical error.
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`transmission medium, one pair for transmitting and one pair for receiving, but
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`was still effectively limited to a half-duplex communication channel. Id. at
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`1:46-65.
`
`59. Sambamurthy provides a method of achieving
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