Filed: September 2, 2016
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`EMC CORPORATION
`
`Petitioner,
`
`v.
`
`Filed on behalf of:
`Patent Owner Intellectual Ventures II LLC
`John R. King
`Ted M. Cannon
`Bridget A. Smith
`KNOBBE, MARTENS, OLSON & BEAR, LLP
`2040 Main Street, 14th Floor
`Irvine, CA 92614
`Tel.: (949) 760-0404
`Fax: (949) 760-9502
`Email: BoxPGL39@knobbe.com
`
`By:
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`INTELLECTUAL VENTURES II LLC,
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`Patent Owner
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`Case No. IPR2016-01106
`U.S. Patent No. 6,516,442
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`PATENT OWNER’S PRELIMINARY RESPONSE
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`NETAPP ET AL. EXHIBIT 1011
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`Page A
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`EMC CORPORATION
`
`Petitioner,
`
`v.
`
`Filed on behalf of:
`Patent Owner Intellectual Ventures II LLC
`John R. King
`Ted M. Cannon
`Bridget A. Smith
`KNOBBE, MARTENS, OLSON & BEAR, LLP
`2040 Main Street, 14th Floor
`Irvine, CA 92614
`Tel.: (949) 760-0404
`Fax: (949) 760-9502
`Email: BoxPGL39@knobbe.com
`
`By:
`
`
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`INTELLECTUAL VENTURES II LLC,
`
`Patent Owner
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`Case No. IPR2016-01106
`U.S. Patent No. 6,516,442
`
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`PATENT OWNER’S PRELIMINARY RESPONSE
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`NETAPP ET AL. EXHIBIT 1011
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`Page A
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`I.
`
`II.
`
`TABLE OF CONTENTS
`
`
`Page No.
`
`
`INTRODUCTION ........................................................................................... 1
`
`BACKGROUND OF THE PATENT .............................................................. 4
`
`A.
`
`B.
`
`C.
`
`The patent describes an innovative symmetric multiprocessing
`system architecture with a switch fabric to network multiple
`microprocessors and shared memory .................................................... 4
`
`The patented symmetric multiprocessing system is configured to
`perform error correction on the packetized data on both sides of
`the channels ........................................................................................... 9
`
`The prosecution history emphasizes that the error correction is
`of the data in the packets and that the error correction is
`performed in the interfaces ................................................................. 11
`
`III. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 13
`
`IV. CLAIM CONSTRUCTION .......................................................................... 13
`
`A.
`
`B.
`
`Legal standard ..................................................................................... 13
`
`IV’s proposed constructions ................................................................ 14
`
`1.
`
`“a switch fabric configured to switch packets containing
`data” (claim 1) and “exchanging the packets between
`the switch interfaces through a switch fabric” (claim 24) ........ 14
`
`a.
`
`b.
`
`switch fabric .................................................................... 15
`
`switch packets containing data ....................................... 17
`
`2.
`
`“channels” ................................................................................. 21
`
`C.
`
`IV’s proposed constructions in this proceeding are consistent with
`positions in the co-pending litigation .................................................. 23
`
`i
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`NETAPP ET AL. EXHIBIT 1011
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`Page i
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`
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`Page No.
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`
`
`TABLE OF CONTENTS
`(cont’d)
`
`V.
`
`TRIAL SHOULD NOT BE INSTITUTED ON ANY CLAIM .................... 25
`
`A.
`
`B.
`
`Legal Standards ................................................................................... 25
`
`The Petition does not show a reasonable likelihood of prevailing
`on Ground 1 ......................................................................................... 26
`
`1. Reschke does not have a switch fabric configured to switch
`packets containing data ............................................................. 27
`
`2. Reschke does not have channels configured to transfer
`packets ....................................................................................... 33
`
`3. Reschke does not have microprocessor interfaces that
`perform error correction of the data in the packets
`exchanged over the channels with the switch interfaces .......... 36
`
`4. Reschke does not have a memory interface that performs
`error correction of the data in packets exchanged over
`channels with the switch interfaces .......................................... 38
`
`C.
`
`The Petition does not show a reasonable likelihood of prevailing
`on Grounds 2–4 ................................................................................... 40
`
`D.
`
`Reservation of Rights .......................................................................... 43
`
`VI. THE BOARD SHOULD NOT INSTITUTE TRIAL ON ANY ......................
`
`REDUNDANT GROUNDS .......................................................................... 44
`
`A.
`
`B.
`
`The Board should not institute trial on both Grounds 1 and 2 ............ 45
`
`The Board should not institute trial on both Ground 4 and
`Ground 2 for claims 2 and 25 .............................................................. 46
`
`VII. CONCLUSION .............................................................................................. 48
`
`
`
`ii
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`NETAPP ET AL. EXHIBIT 1011
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`Page ii
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`
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`TABLE OF AUTHORITIES
`
`
`
`Garmin Int’l, Inc. v. Cuozzo Speed Techs. LLC,
`IPR2012-00001, Paper 15 (P.T.A.B. Jan. 9, 2013) ............................................ 23
`
`Page No(s).
`
`
`Graham v. John Deere Co.,
`383 U.S. 1 (1966) ................................................................................ 3, 40, 41, 42
`
`Honeywell Int’l, Inc. v. ITT Industries, Inc.,
`452 F.3d 1312 (Fed. Cir. 2006) .......................................................................... 22
`
`K/S HIMPP v. Hear-Wear Techs., LLC,
`751 F.3d 1362 (Fed. Cir. 2014) .................................................................... 42, 43
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 40
`
`Liberty Mut. Ins. Co. v. Progressive Cas. Ins. Co.,
`No. CBM2012-00003,
`2012 WL 9494791 (P.T.A.B. Oct. 25, 2012) ......................................... 44, 45, 46
`
`Luminara Worldwide, LLC v. Liown Elecs. Co.,
`814 F.3d 1343 (Fed. Cir. 2016) .......................................................................... 22
`
`In re Magnum Oil Tools Int’l, Ltd.,
`No. 2015-1300, 2016 WL 3974202 (Fed. Cir. July 25, 2016) ........................... 27
`
`Microsoft Corp. v. Proxyconn, Inc.,
`789 F.3d 1292 (Fed. Cir. 2015) .......................................................................... 13
`
`Oracle Corp. v. Clouding IP, LLC,
`IPR2013-00075, Paper 15 (P.T.A.B. June 13, 2013) ............................. 45, 47, 48
`
`Ex Parte Pfister,
`No. 2009-6577, 2009 WL 5503158 (B.P.A.I. Dec. 18, 2009) ........................... 20
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 14
`
`iii
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`NETAPP ET AL. EXHIBIT 1011
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`Page iii
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`Page No.
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`
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`TABLE OF AUTHORITIES
`(cont’d.)
`
`Rackspace Hosting, Inc. v. Rotatable Techs. LLC,
`IPR2013-00248, Paper 32 (P.T.A.B. Sept. 19, 2014) ......................................... 18
`
`SciMed Life Sys. Inc. v. Advanced Cardiovascular Sys., Inc.,
`242 F.3d 1337 (Fed. Cir. 2001) .......................................................................... 22
`
`Ex Parte Shelnut,
`No. 2009-0080, 2009 WL 1155595 (B.P.A.I. Apr. 29, 2009) ............................ 20
`
`In re Translogic Tech.,
`504 F.3d 1249 (Fed. Cir. 2007) .......................................................................... 13
`
`Travelocity.com L.P. v. Cronos Techs. LLC,
`CBM2014-00082, Paper 12 (P.T.A.B. Oct. 16, 2014) ................................. 41, 42
`
`TriVascular, Inc. v. Samuels,
`812 F.3d 1056 (Fed. Cir. 2016) .......................................................................... 16
`
`Unigene Labs. Inc. v. Apotex, Inc.,
`655 F.3d 1352 (Fed. Cir. 2011) .......................................................................... 41
`
`Unwired Planet, LLC. v. Apple Inc.,
`No. 2015-1725, 2016 WL 3947839 (Fed. Cir. July 22, 2016) ........................... 21
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999) ............................................................................ 14
`
`OTHER AUTHORITIES
`
`37 C.F.R. § 108 ........................................................................................................ 26
`
`37 C.F.R. § 208 ........................................................................................................ 26
`
`37 C.F.R. § 42.23 ..................................................................................................... 26
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`37 C.F.R. § 42.100 ................................................................................................... 13
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`37 C.F.R. § 42.108 ................................................................................................... 26
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`-iv-
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`NETAPP ET AL. EXHIBIT 1011
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`Page iv
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`Page No.
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`TABLE OF AUTHORITIES
`(cont’d.)
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`35 U.S.C. § 103 .................................................................................................. 40, 41
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`35 U.S.C. § 314 ........................................................................................................ 26
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`
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`NETAPP ET AL. EXHIBIT 1011
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`Page v
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`IPR2016-01106
`EMC v. Intellectual Ventures
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`TABLE OF EXHIBITS
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`Exhibit No.
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`Description
`
`2001
`
`2002
`
`2003
`
`2004
`
`2005
`
`2006
`
`2007
`
`2008
`
`2009
`
`Definition of SMP, Symmetric Multiprocessing,
`http://www.webopedia.com/TERM/S/SMP.html
`
`A. Charlesworth et al., “Gigaplane-XB: Extending the Ultra
`Enterprise Family,” Proc. Hot Interconnects Symp. V, 1997,
`http://HTTP.CS.Berkeley.EDU/~culler/hoti97/E10000.ps
`
`Hot Interconnects Symposium V 1997 Information,
`https://people.eecs.berkeley.edu/~culler/hoti97/
`
`JEDEC Standard No. 21–C, Release 7, pp. 4.6.1–1 through 4.6.1–8,
`June 1997
`
`JEDEC Standards & Documents Search: DIMM,
`http://www.jedec.org
`
`K. Hwang, Advanced Computer Architecture: Parallelism,
`Scalability, Programmability, pp. 75–96 (1993)
`
`Microsoft Press Computer Dictionary, pp. 136, 285–86 (1994)
`
`Plaintiffs Intellectual Ventures I LLC and Intellectual Ventures II
`LLC’s Reply Claim Construction Brief, Intellectual Ventures I LLC
`et al. v. HCC Insurance Holdings, Inc. et al., Civil Action No. 6:15-
`CV-660-JRG (E.D. Tex. May 25, 2016)
`
`Report and Recommendation of United States Magistrate Judge,
`Intellectual Ventures I LLC et al. v. HCC Insurance Holdings, Inc.
`et al., Civil Action No. 6:15-CV-660-JRG (E.D. Tex. Aug. 26,
`2016)
`
`2010
`
`Declaration of Bridget A. Smith
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`-vi-
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`NETAPP ET AL. EXHIBIT 1011
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`Page vi
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`IPR2016-01106
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`Patent Owner (“IV”) submits this Preliminary Response in opposition to the
`
`Petition (Paper 3, “Pet.”) to institute an inter partes review (IPR) of U.S. Patent No.
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`6,516,442 (“the ’442 patent”). The Petition challenges claims 1, 2, 5, 9, 10, 12, 24,
`
`25, 28, and 32–34 of the ’442 patent. This Preliminary Response addresses why the
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`Board should not institute review on the challenged claims.
`
`I.
`The ’442 patent describes and claims a unique structure for increasing
`
`INTRODUCTION
`
`bandwidth and processing speed in systems with multiple microprocessors and
`
`shared memory.
`
`The claimed inventions reject shared-bus architecture in favor of a switch
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`fabric that networks the multiple microprocessors and shared memory to
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`effectively give each transaction its own bus, allowing for multiple simultaneous
`
`transactions at high bandwidths. Data is switched through that switch fabric, not as
`
`a traditional data stream across a data bus, but as packets of data and control
`
`information “to reliably transfer data from one chip to another in the face of errors
`
`and limited buffering.” Ex. 1001, abstract. These packets are also exchanged
`
`through interfaces at the microprocessors, at the shared memory, and at the switch
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`fabric across bidirectional, full-duplex buses called channels. The claimed
`
`inventions perform error correction at each of these interfaces, on both sides of the
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`channels. This innovative error correction technique even further improves
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`processing speeds by allowing one side of a channel to transfer packets normally
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`while correcting an error on the other side.
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`The Board should not institute trial because the Petition does not
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`demonstrate a reasonable likelihood that at least one of the challenged claims is
`
`unpatentable. The Petition is unlikely to prevail on the alleged anticipation ground
`
`(Ground 1) because there is no evidence Reschke discloses the following
`
`limitations of the independent claims:
`
`
`
`“a switch fabric configured to switch packets containing data”
`
`(claim 1) and “exchanging the packets between the switch interfaces
`
`through a switch fabric” (claim 24);
`
`
`
`“a plurality of channels configured to transfer the packets” (claim 1)
`
`and “exchanging packets containing
`
`the data between
`
`the
`
`microprocessor interfaces and a plurality of switch interfaces over
`
`channels” and “exchanging the packets between the switch interfaces
`
`and a memory interface over the channels” (claim 24); and
`
`
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`“a plurality of microprocessor interfaces configured to … exchange
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`the packets with the switch interfaces over the channels, and perform
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`error correction of the data in the packets exchanged over the
`
`channels” and “a memory interface configured to … exchange the
`
`packets with the switch interfaces over the channels, and perform
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`error correction of the data in the packets exchanged over the
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`channels” (claim 1) and “in the interfaces, performing error correction
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`of the data in the packets exchanged over the channels” (claim 24).
`
`The Petition is also unlikely to prevail on the alleged obviousness ground for
`
`the independent claims (Ground 2). The Petition omits Graham factor 2 in the
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`analysis, rendering that alleged ground defective. Moreover, because the Petition
`
`does not establish the missing limitations above were known anywhere in the prior
`
`art, the Petition cannot show the claims as a whole would have been obvious.
`
`Therefore, the Petition does not establish a reasonable likelihood of prevailing on
`
`independent claims 1 and 24 or their challenged dependent claims.
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`Should the Board somehow decide to institute trial, it should not include the
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`redundant grounds. Grounds 1 and 2 are redundant: Ground 2 is merely an
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`undeveloped obviousness ground proposed as a fallback to Ground 1 in the event
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`the Board agrees Reschke does not disclose the claimed error correction structure.
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`Furthermore, Ground 4 is vertically redundant of Ground 2 for claims 2 and 25.
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`The Board should not institute trial on these redundant grounds.
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`-3-
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`Page 3
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`IPR2016-01106
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`II. BACKGROUND OF THE PATENT
`A. The patent describes an innovative symmetric multiprocessing system
`architecture with a switch fabric to network multiple microprocessors
`and shared memory
`
`
`The ’442 patent is about symmetric multiprocessing (SMP) system
`
`architecture. These systems “provide[] fast performance by making multiple
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`[microprocessors] available to complete individual processes simultaneously ….”
`
`Ex. 2001 at 1.
`
`At the time of the patent, SMP systems typically used a shared bus between
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`multiple microprocessors and a memory device. See Ex. 1001, fig. 1. These shared
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`buses process transactions serially. A bus starts one transaction and, after a delay,
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`starts a second transaction. Shared-bus architecture promotes cache coherency
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`because the “serial availability of the bus insures the transactions are performed in
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`a well-defined order.” Id., 1:32–33. But it inhibits scalability because, as more
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`microprocessors “are added, eventually system performance is limited by the
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`saturation of the shared system bus.” Id., 1:38–40.
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`The ’442 patent significantly improved this typical SMP architecture,
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`eschewing the shared-bus paradigm in favor of a switch fabric networking multiple
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`microprocessors and shared memory. The “switched fabric (switched matrix) for
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`data transfers … provides multiple concurrent buses that enable greatly increased
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`bandwidth between [micro]processors and shared memory.” Id., 1:50–53; see also
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`id., 5:34–35. The switch fabric effectively gives each transaction its own bus,
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`which allows for multiple simultaneous transactions. See id.
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`In particular, the ’442 patent describes an innovative system that transfers
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`data between the multiple microprocessors and shared memory by switching
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`packets containing the data through the switch fabric. Figure 3 of the patent is
`
`reproduced here with color annotations to facilitate discussion. In describing this
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`system, the specification uses acronyms extensively. Below, IV maps some key
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`acronyms in the specification to the Figure 3 components.
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`The SMP system transfers data between the multiple microprocessors and
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`
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`the shared memory.
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`The dark green blocks are the multiple microprocessors (120). Figure 3
`
`shows them as “CPU0” through “CPU7.” The specification similarly uses the
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`acronym CPU for the multiple microprocessors. CPU, as the Board is aware,
`
`stands for “central processing unit.” At the time of the patent (and even today), off-
`
`the-shelf microprocessors from Intel, AMD, Sun, and IBM used proprietary bus
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`protocols. See Ex. 2002 at 1, tbl. 1.
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`The dark blue blocks are the shared memory (1300–1303). Figure 3 shows a
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`memory device as “SDRAM,” which stands for synchronous dynamic random
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`access memory. The specification contemplates other types of memory. In any
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`event, the configuration is flexible and can include, for example, one or two
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`memory banks, with one to four dual in-line memory modules (DIMMs) per bank,
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`with non-interleaved or interleaved operation. Ex. 1001, 3:29–31. DIMMs use an
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`industry-standard (JEDEC) bus protocol. See generally Ex. 2004.
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`The light green blocks are microprocessor interfaces (210). Figure 3 calls
`
`each microprocessor interface a “Dual CPU/Cache Interface.” The specification
`
`calls it a “Dual CPU Interface Unit,” with the acronym DCIU. Ex. 1001, 2:64–65.
`
`The “Dual CPU Interface Unit (DCIU) 210 interfaces two CPUs [microprocessors]
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`with the FCU [flow control unit].” Id., 2:65–67. The Dual CPU Interface Unit
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`(DCIU) packages a pair of “CPU Channel Units,” which the specification
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`abbreviates as CCUs. Id., 2:63–65. Each CPU Channel Unit (CCU) interfaces with
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`one microprocessor. See id., 2:65–67. The light green microprocessor interfaces
`
`exchange data with the dark green microprocessors. The microprocessor interfaces
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`“act as a protocol converter,” converting between the microprocessors’ bus
`
`protocol and the packet-based channel protocol used in the switch fabric and
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`channels, discussed below. See id., 3:4–5.
`
`The light blue block is a memory interface (230). Figure 3 calls the memory
`
`interface a Memory Interface Control. The specification calls it a Memory Control
`
`Unit, with the acronym MCU. The light blue memory interface exchanges data
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`with the dark blue memory device. The memory interface also converts between
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`the memory device’s bus protocol and the rest of the SMP system’s packet-based
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`channel protocol.
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`The magenta blocks are channels (112 and 114). Both the top channels (112)
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`and the right channels (114) transfer the packets. The specification calls them
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`“Point-to-Point (PP) interconnects,” “Channels,” and “PP-Channels.” Id., 2:52–56;
`
`see also id., 6:40–45.
`
`The orange blocks are switch interfaces (3102 and 3108). The specification
`
`refers to the top switch interface (3102) as the “Initiator Interface” (IIF) and the
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`specification refers to the right interface (3108) as the “Memory Interface” (MIF).
`
`Both types of switch interfaces exchange the packets over the channels. The light
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`green microprocessor interfaces (210) exchange packets with the orange top switch
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`interface (3102) over the magenta top channels (112). The light blue memory
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`interface (230) exchanges packets with the orange right switch interface (3108)
`
`over the magenta right channels (114).
`
`The yellow block is the switch fabric that networks the multiple
`
`microprocessors and the shared memory by switching the packets. The patent
`
`specifically notes the switch fabric “is packet based.” Id., 4:37. The switch fabric
`
`“is composed of vertical buses 320, horizontal buses 340, node switches 380. The
`
`node switches selectively couple the vertical and horizontal buses ….” Id.,
`
`5:34–38. By closing a circuit between one horizontal bus and one vertical bus, the
`
`switch fabric effectively gives each transaction passing through the switch fabric
`
`its own bus. The orange top switch interface (3102) exchanges the packets with the
`
`yellow switch fabric from the microprocessor side. The orange right switch
`
`interface (3108) exchanges the packets with the yellow switch fabric from the
`
`memory side.
`
`In this way, the patented technology exchanges data from one component to
`
`another, either as data (between the microprocessors and the microprocessor
`
`interfaces and between the memory interface and the memory device) or as packets
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`containing the data (between the microprocessor interfaces and the switch
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`interfaces, between the switch interfaces and the switch fabric, and between the
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`switch interfaces and the memory interface). The switch fabric dramatically
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`improves bandwidth in systemic multiprocessor systems by effectively giving each
`
`transaction its own bus. Id., abstract.
`
`B.
`
`The patented symmetric multiprocessing system is configured to
`perform error correction on the packetized data on both sides of the
`channels
`
`
`The claimed embodiments reflect an innovative approach to performing
`
`error corrections on the packetized data. With reference again to the color-
`
`annotated Figure 3 above:
`
`
`
`The orange switch interfaces (3102 and 3108) are configured to
`
`perform error correction of the data in the packets exchanged over the
`
`magenta channels (112 and 114), that is, with the light green
`
`microprocessor interfaces (210) and the light blue memory interface
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`(230).
`
`
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`The light green microprocessor interfaces (210), in turn, are
`
`configured to perform error correction of the data in the packets
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`exchanged over the top magenta channels (112), that is, with the top
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`orange switch interfaces (3102).
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`
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`And the light blue memory interface (230) is similarly configured to
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`perform error correction of the data in the packets exchanged over the
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`right magenta channels (114), that is, with the right orange switch
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`interfaces (3108).
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`Put simply, the claimed interfaces are configured to perform error correction on the
`
`packetized data on both sides of the channels. See also Ex. 1010 at 17 (explaining
`
`during prosecution of the ’442 patent application that “the first switch interface and
`
`the microprocessor interface perform error correction of the data in the packet
`
`transferred over the first channel” and “the memory interface and the second
`
`switch interface perform error correction of the data in the packet transferred over
`
`the second channel,” emphases removed).
`
`The claimed configuration is an innovative approach that even further
`
`improves processing speed in a symmetric multiprocessing system. Because the
`
`interfaces are configured to handle errors “independently on both sides” of a
`
`channel (Ex. 1001, 22:58–60), that channel does not have to be shut down entirely
`
`when an error occurs. The inventors inventively realized (and excitedly
`
`emphasized in the specification) that channel “may still be transmitting correctly to
`
`the other side!” Id., 22:60–61. Thus, with the claimed solution the “reception error
`
`does not cause transmission to stop” and the side that received the error “is happily
`
`incrementing with each data packet it sends” while the other side sorts out the
`
`error. Id., 22:62–65; see also id., 21:15–17 (“[e]rror retries affect one direction of
`
`data transfer only …”). Only “[i]f errors occur simultaneously in both directions of
`
`travel,” will the system stop ordinary transfers over the channel while the errors are
`
`resolved. Id., 21:17–19.
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`Page 10
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`The patented symmetric multiprocessing system is configured to perform
`
`error correction on the packetized data on both sides of the channels, which
`
`improves processing speeds by allowing one side of a channel to process normally
`
`even if there is an error on the other side.
`
`C. The prosecution history emphasizes that the error correction is of the
`data in the packets and that the error correction is performed in the
`interfaces
`
`The prosecution history emphasizes “that the interfaces, including the switch
`
`interfaces, perform error correction for the data in the packets transferred over the
`
`channels.” Ex. 1010 at 17 (emphases original).
`
`The inventors distinguished one prior art reference (Van Doren) because
`
`only its processors and memories perform error correction:
`
`Van Doren does not teach any switch interfaces that perform error
`correction at the [switch]. Although Van Doren does mention the use
`of error correction codes, it appears that the [switch] passively
`transfer[s] the error correction codes between the processors and
`memories, so the processors and memories would perform the error
`correction. Van Doren does not teach error correction at the switch as
`required by the present invention.
`
`Id. at 17–18 (internal citation omitted). In the statement of reasons for allowance,
`
`the art unit examiner agreed Van Doren did not meet the claims because “Van
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`Doren achieves the error correction of data in the memory or in the processor.” Ex.
`
`1011 at 2.
`
`
`
`The inventors distinguished a second prior art reference (Baum) because
`
`error correction was performed for addresses and not for data:
`
`Baum does not teach interfaces at the switch that perform error
`correction for the data in the packets. Baum teaches a mechanism at
`the switch for performing error correction for the addresses in the
`packets, but this mechanism does not perform error correction for the
`data in the packets. Thus, like Van Doren, Baum teaches processors
`that perform error correction for the data in the packets, but does not
`teach switch interfaces that perform error correction for the data in the
`packets.
`
`Ex. 1010 at 18 (internal citation omitted, emphases in original). And in the
`
`statement of reasons for allowance, the examiner agreed the “prior arts … do not
`
`teach that the error correction of the data being transferred between the processor
`
`and switch and between the switch and memory takes place in the switching
`
`interface.” Ex. 1011 at 3.
`
`The prosecution history confirms that, in the inventive SMP system, all
`
`interfaces—the switch interfaces, the microprocessor interfaces, and the memory
`
`interface—perform error correction for the data in the packets transferred over the
`
`channels.
`
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`Page 12
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`III. LEVEL OF ORDINARY SKILL IN THE ART
`The Petition defines the level of ordinary skill in the art on page 4. Although
`
`IV believes the Petition’s definition is incorrect, this Preliminary Response applies
`
`the Petition’s definition in the interest of streamlining factual disputes at this stage
`
`of the proceeding. IV believes the Board can resolve this IPR at the preliminary
`
`stage also applying that definition. IV reserves the right to revisit the definition
`
`should the Board institute trial.
`
`IV. CLAIM CONSTRUCTION
`
`A. Legal standard
`In IPR, the Patent Office applies the broadest-reasonable-interpretation
`
`standard to construe claims. 37 C.F.R. § 42.100(b). The broadest reasonable
`
`interpretation does not mean the broadest possible interpretation. Microsoft Corp.
`
`v. Proxyconn, Inc., 789 F.3d 1292, 1298 (Fed. Cir. 2015). Rather, under this
`
`standard, a term has the ordinary and customary meaning given to the term by
`
`those of ordinary skill in the art at the time of the invention, unless such meaning is
`
`inconsistent with the specification. In re Translogic Tech., 504 F.3d 1249, 1257
`
`(Fed. Cir. 2007).
`
`The only exceptions to giving the words in a claim their ordinary and
`
`customary meaning in the art are 1) when the applicant acts as a lexicographer,
`
`clearly setting forth a special definition of a claim term in the specification that
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`differs from the ordinary and customary meaning it would otherwise possess;
`
`and 2) when the applicant disavows or disclaims the full scope of a claim term in
`
`the specification. In both of these cases, “the inventor’s intention, as expressed in
`
`the specification, is regarded as dispositive.” Phillips v. AWH Corp., 415 F.3d
`
`1303, 1316 (Fed. Cir. 2005) (en banc).
`
`B.
`
`IV’s proposed constructions
`
`Only those terms in controversy must be construed, and then only to the
`
`extent necessary to resolve the controversy. Vivid Techs., Inc. v. Am. Sci. & Eng’g,
`
`Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). IV disputes some of the Petition’s
`
`proposed constructions below.1
`
`1.
`
`“a switch fabric configured to switch packets containing data”
`(claim 1) and “exchanging the packets between the switch
`interfaces through a switch fabric” (claim 24)
`
`
`
`
`
`The correct construction of “a switch fabric configured to switch packets
`
`containing data” (claim 1) is “interconnected switches configured to switch
`
`formatted information units including at least data and control information.”
`
`Similarly, the correct construction of “exchanging the packets between the switch
`
`1 IV has not addressed all proposed constructions because IV does not
`
`believe it is necessary to construe all those terms to resolve the IPR at this time.
`
`Silence is not acquiescence. Therefore IV reserves the right to revisit those
`
`constructions and offer additional constructions should the Board institute trial.
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`interfaces through a switch fabric” (claim 24) is “exchanging the formatted
`
`information units including at least data and control information between the
`
`switch interfaces through interconnected switches.”
`
`EMC does not allege that the ’442 patent expressly defines these terms or
`
`the component terms “switch fabric” and “packet.” Pet. 11–14. These terms are
`
`entitled to their ordinary and customary meanings. IV identifies the correct
`
`constructions below.
`
`switch fabric
`
`a.
`The ordinary and customary meaning of the component term “switch fabric”
`
`is, as the words themselves suggest, “interconnected switches.” The specification is
`
`consistent with this ordinary and customary meaning. The specification uses the
`
`shorthand term “Data Switch” (with a capital “D” and a capital “S”) when
`
`discussing the full term “switched fabric data path.” Ex. 1001, 4:30–37. With
`
`reference to Figure 3, the specification explains that the “Data Switch is composed
`
`of vertical buses 320, horizontal buses 340, node switches 380. The node switches
`
`selectively couple the vertical and horizontal buses ….” Id., 5:34–36. In other
`
`words, the vertical and horizontal buses interconnect the switches, and this
`
`preferred embodiment follows the ordinary and customary meaning.
`
`The Petition’s construction (a communication subsystem that provides for
`
`parallel routing of packets between multiple sources and targets) is unreasonably
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`broad because it is broader than the ordinary and customary meaning. In fact, the
`
`construction is so broad that it covers network topologies far beyond switch
`
`fabrics. For example, a ring network is a communication subsystem that provides
`
`for parallel routing of packets between multiple sources and targets, satisfying the
`
`Petition’s construction. Ex. 2006 at 4, 8–9. But an ordinary artisan would have
`
`recognized that a ring netwo
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