Trials@uspto.gov
`571-272-7822
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` Paper 36
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` Entered: July 5, 2018
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00561
`Patent 8,001,434 B1
`____________
`
`
`Before BRYAN F. MOORE, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`MOORE, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. 318(a)
`
`
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`
`
`571-272-7822
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` Paper 36
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` Entered: July 5, 2018
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00561
`Patent 8,001,434 B1
`____________
`
`
`Before BRYAN F. MOORE, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`MOORE, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. 318(a)
`
`
`
`
`
`
`IPR2017-00561
`Patent 8,001,434 B1
`
`
`I.
`INTRODUCTION
`SK hynix Inc., SK hynix America Inc., and SK hynix memory
`solutions Inc., (collectively “Petitioner”) filed a Petition (Paper 1, “Pet.”)
`pursuant to 35 U.S.C. §§ 311–319 to institute an inter partes review of
`claims 1–7 (“the challenged claims”) of U.S. Patent No. 8,001,434 B1 (“the
`’434 Patent,” Ex. 1001). The Petition is supported by the Declaration of
`Pinaki Mazumder, Ph.D. (“Mazumder Declaration,” “Mazumder Dec.,” Ex.
`1003). Netlist, Inc. (“Patent Owner”) filed a Preliminary Response (“Prelim.
`Resp.,” Paper 6).
`On July 7, 2017, we instituted an inter partes review of claims 1–7 of
`the ’434 Patent, but did not institute on all grounds. Paper 7, 7, 33 (“Inst.
`Dec.”). Patent Owner filed a Response. Paper 14 (“PO Resp.”). The Patent
`Owner Response is supported by the Declaration of R. Jacob Baker, Ph.D.
`(“Baker Declaration,” “Baker Dec.,” Ex. 2010). Petitioner filed a Reply.
`Paper 18 (“Reply”).
`On February 28, 2018, Petitioner and Patent Owner filed motions to
`exclude. Paper 21 (“Pet. Mot. to Excl.”); Paper 23 (“PO Mot. to Excl.”).
`Petitioner and Patent Owner filed responses to their respective motions to
`exclude. Paper 25 (“Pet. Mot. to Excl. Resp.”); Paper 26 (“PO Mot. to Excl.
`Resp.”). Petitioner and Patent Owner filed replies to those respective
`responses. Paper 29 (“Pet. Mot. to Excl. Reply”); Paper 30 (“PO Mot. to
`Excl. Reply”).
`On March 13, 2018, we entered a sua sponte Order to Show Cause
`why the inter partes review should not be terminated as to claim 1 because it
`has been finally adjudicated as unpatentable. Paper 24 (“Show Cause
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`Order”). Petitioner and Patent Owner responded to the order. Paper 27
`(“Pet. Show Cause Resp.”); Paper 28 (“PO Show Cause Resp.”).
`An oral hearing was held on April 6, 2018. Paper 34 (“Tr.”).
`On April 24, 2018, the Supreme Court held that a decision on
`institution under 35 U.S.C. § 314 may not institute on less than all claims
`challenged in the petition. 138 S. Ct. 1348 (2018). We modified our
`Institution Decision to institute trial on all of the challenged claims and all of
`the grounds presented in the Petition. Paper 35 (“SAS Order”). We invited
`the parties to request briefing regarding the newly added grounds and no
`request was made. Id.
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
`follow, we determine that Petitioner has shown by a preponderance of the
`evidence that claims 2–7 are unpatentable. Based on collateral estoppel, we
`also terminate the trial pursuant to 37 C.F.R. § 42.72 as to claim 1.
`A. Related Proceedings
`Petitioner recites a list of District Court proceedings related to this
`inter partes review. Pet. 5. This inter partes review challenges the same
`patent at issue in the decision entered in IPR2014-00970 (the ’970 IPR). See
`Sandisk Corp. v. Netlist, Inc., Case IPR2014-00970 (PTAB Dec. 16, 2014)
`(Paper 12). In the ’970 IPR, as to the claims at issue here, claim 1 was held
`unpatentable as anticipated by Averbuj in a final written decision. Sandisk
`Corp. v. Netlist, Inc., Case IPR2014-00970 (PTAB Dec. 14, 2015) (Paper
`32). That decision was appealed to Federal Circuit, the decision was
`affirmed, and the mandate issued on December 21, 2017. See Exs. 1029,
`3
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`1034. In the ’970 IPR, claims 2–7 were also challenged as obvious over
`Averbuj and Tsern, but that challenge was not instituted. Sandisk, IPR2014-
`00970 (Paper 12).
`The ’434 Patent was also challenged in IPR2014-01372 (the ’1372
`IPR). In the 1372 IPR, as to the claims at issue here, claims 1–4 were held
`not unpatentable as anticipated by Averbuj (under a different theory of
`anticipation than the ’970 IPR) in a final written decision. Smart Modular
`Techs. Inc. v. Netlist, Inc., Case IPR2014-01372 (PTAB March 9, 2016)
`(Paper 45). The decision in the ’1372 IPR was not appealed to Federal
`Circuit.
`The ’434 Patent was also challenged in IPR2014-01373 (the ’1373
`IPR), in which institution was denied as to all challenges on the merits.
`Smart Modular Techs. Inc. v. Netlist, Inc., Case IPR2014-01373 (PTAB
`Mar. 13, 2015) (Paper 16). Neither Averbuj nor Tsern was asserted in the
`’1373 IPR.
`
`B. The ’434 Patent
`The ’434 Patent relates to self-testing electronic memory modules.
`Ex. 1001, 1:23–24. A block diagram of an exemplary self-testing memory
`module is shown in Figure 3 of the ’434 Patent, reproduced below.
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`As illustrated in Figure 3, above, “memory module 10 includes a
`printed circuit board 12 (PCB) configured to be operatively coupled to a
`memory controller 14 of a computer system 16.” Id. at 5:1–3. Memory
`module 10 includes a plurality of memory devices 18, each memory device
`20 of the plurality of memory devices 18 comprising data, address, and
`control ports. Id. at 5:3–7. Memory module 10 further includes control
`module 22 and data module 28 comprising a plurality of independently
`operable data handlers 30. Id. at 5:7–11. Control module 22 includes
`memory device controller 34, which receives address and control signals 38
`from system memory controller 14 and address and control signals 42 from
`test controller 36. Id. at 9:40–45. Similarly, data module 28 includes switch
`44, which selectively inputs to memory devices 18 either data signals 48
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`from memory controller 14 or data signals 50 from data handler logic
`element 46. Id. at 10:7–11.
`During test mode, memory device controller 34 sends address and
`control signals 38 from test controller 36 to register 40 for input to address
`and control ports of memory devices 18. Id. at 9:40–50. “[T]est controller
`36 updates each of [] data handlers 30 (e.g., with new data patterns, write
`signal characteristics, etc.)” Id. at 14:7–9. Data generation element 54 of
`data handler logic element 46 is configured to generate data signals and/or
`patterns of data signals based on the information received from test
`controller 36, for writing to memory devices 18. Id. at 10:28–37, 15:25–27.
`
`
`C. Illustrative Claim
`Of the challenged claims, claim 1 is independent. Claim 1,
`reproduced below, is illustrative of the claimed subject matter:
`1.
`A self-testing memory module, comprising:
`a printed circuit board configured to be operatively
`coupled to a memory controller of a computer system;
`a plurality of memory devices on the printed circuit board,
`each memory device of the plurality of memory devices
`comprising data, address, and control ports; and
`a circuit comprising:
`a control module configured to generate address and
`control signals for testing the memory devices; and
`a data module comprising a plurality of data handlers, each
`data handler operable independently from each of the other data
`handlers of the plurality of data handlers and operatively coupled
`to a corresponding plurality of the data ports of one or more of
`the memory devices and configured to generate data for writing
`to the corresponding plurality of data ports, wherein the circuit is
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`configured to test the memory devices using the address and
`control signals generated by the control module and the data
`generated by the plurality of data handlers.
`Ex. 1001, 16:32–53.
`
`
`D. Instituted Grounds of Unpatentability
`We instituted trial on the following ground (Inst. Dec. 34; SAS
`
`
`Order 2):
`Reference[s]
`Averbuj1
`
`Averbuj
`Averbuj and Tsern2
`
`
`
`Basis
`§ 102
`
`§ 103
`§ 103
`
`Claims Challenged
`1–7
`
`1–7
`1–7
`
`II. ANALYSIS
`A. Collateral Estoppel
`The parties raised an issue arising from challenges to the subject
`patent in related inter partes review proceedings brought by a different
`petitioner, namely the ’970 IPR. In the ’970 IPR, the Board held that claim
`1 is unpatentable over art that is the same as the art considered in this
`proceeding as against a different petitioner (Sandisk) than this proceeding.
`Sandisk Corp. v. Netlist, Inc., Case IPR2014-00970 (PTAB Dec. 14, 2015)
`(Paper 32). The Federal Circuit affirmed that decision. Netlist, Inc. v.
`
`
`1 U.S. Patent Application Publication No. 2005/0257109 (Ex. 1005,
`“Averbuj”)
`2 U.S. Patent Application Publication No. 2007/0070669 (Ex. 1006, “Tsern”)
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`SanDisk LLC, 702 F. App’x 986 (Fed. Cir. 2017). (per curiam).
`Accordingly, claim 1, which is involved in this proceeding, has been held
`unpatentable. This raises the issue of whether we should terminate the
`proceeding as to claim 1 based on collateral estoppel.
`“It is well established that collateral estoppel, also known as issue
`preclusion, applies in the administrative context.” MaxLinear, Inc. v. CF
`CRESPE LLC, 880 F.3d 1373, 1376 (Fed. Cir. 2018) (citations omitted);
`Webpower, Inc., Case IPR2016-01239, slip. op. at 26–28 (PTAB Dec. 26,
`2017) (Paper 21). A patentee is estopped from asserting the validity of a
`patent that has been declared invalid in a prior suit against a different
`defendant, unless patentee demonstrates that he did not have full and fair
`opportunity, procedurally, substantively, and evidentially, to litigate the
`validity of his patent in the prior suit. MaxLinear, Inc., 880 F.3d at 1377
`(citing Blonder-Tongue Labs., Inc. v. Univ. of Illinois Found., 402 U.S. 313,
`91 S. Ct. 1434, 28 L. Ed. 2d 788 (1971) (finding collateral estoppel applies
`to a patentee who had a full and fair opportunity to litigate the validity of a
`patent in a prior federal case.)) Thus, as to a different petitioner, when the
`prior decisions finding claims unpatentable have “subsequently been
`affirmed by [the Federal Circuit] those prior decisions, having been affirmed
`by [the Federal Circuit], are binding in this proceeding, as a matter of
`collateral estoppel.” Id. at 1376.
`In response to our Order to Show Cause why the proceeding should
`not be terminated as to claim 1, Patent Owner argued that “[t]his IPR should
`be terminated as to claim 1” to avoid wasting the resources of the Board.
`PO Show Cause Resp. 1. Petitioner argued “[c]ollateral estoppel only binds
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`Patent Owner, not Petitioners, and Petitioners, in addition to advancing the
`same mapping of Averbuj to claim 1 as did SanDisk in IPR2014-0970, also
`present alternative mappings as well.” Pet. Show Cause Br. 1. Petitioner
`further argues “[g]iven that the Board may need to consider whether
`Petitioners’ alternative mappings read on the limitations of claim 1 when
`addressing the patentability of claims 2–7, there may be little efficiency
`gained by terminating this IPR as to claim 1.” Id. at 2. We recognize that
`Petitioner presents alternative mappings as to claim 1. Nevertheless, as
`explained below, we find that claims 2–7 are unpatentable under the
`mappings used in the ’970 IPR. Thus, given that we find that collateral
`estoppel applies, judicial efficiency is advanced by declining to reassess the
`patentability of claim 1 under alternative mappings.
`Patent Owner asserts that this inter partes review relies on
`obviousness based on the combination of Averbuj and Tsern rather than the
`ground under which claim 1 was found unpatentable in the ’970 IPR, i.e.
`anticipation by Averbuj. Thus, according to Patent Owner, “Petitioners must
`also provide evidence of a reason why a POSITA would have
`modified/combined the limitations of claim 1 (as allegedly shown in
`Averbuj) with the limitations of dependent claims 2–7 (as allegedly shown
`in Tsern), to create the claimed inventions.” PO Show Cause Br. 1. We
`agree that Petitioner must show a motivation to combine Tsern with
`Averbuj, but this does not mean that Petitioner must prove again that
`Averbuj meets the limitations of claim 1; it means only that Petitioner need
`show a rationale for combining Tsern with those aspects of Averbuj that the
`Board has already determined meet the limitations of claim 1.
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`Patent Owner asserts that “collateral estoppel does not apply to the
`application of the claim 1 limitations in assessing dependent claims 2–7.”
`Id. at 2. Patent Owner further asserts “[a] party seeking to apply collateral
`estoppel based on a prior action must show that (1) the identical issue was
`actually litigated; (2) the issue was actually decided in a final decision on the
`merits; (3) the issue was necessary to the final decision; and (4) the party
`being estopped was adequately represented in the prior action [i.e. “the
`United Access test”].” Id. at 2 (citing United Access Techs., LLC v.
`CenturyTel Broadband Services LLC, 778 F.3d 1327, 1331 (Fed. Cir.
`2015)). We agree that this is the proper test to use to assess the applicability
`of collateral estoppel. Nevertheless, we note United Access applies
`collateral estoppel in a different context and suggests that issue preclusion
`can be applied in an obvoisness challenge, even if the final decision on the
`original issue was considered under an anticipation challenge. In particular,
`in United Access it was noted that “[i]ssue preclusion [traditionally called
`“collateral estoppel”3] applies to issues litigated in prior disputes . . . [and,
`thus, i]t thus makes no difference that the earlier no-damages-due-to-
`competition ruling arose in a case under the Truth in Negotiation Act and
`that this dispute arises under the False Claims Act and the common law.”
`United Access, 778 F.3d. at 726. The “issue” of whether Averbuj teaches
`the limitations of claim 1 is identical to the issue in and has been litigated in
`the ‘970 IPR which found that Averbuj anticipates the limitations of claim 1.
`
`
`3 Mother’s Rest., Inc. v. Mama’s Pizza, Inc., 723 F.2d 1566, 1569 (Fed. Cir.
`1983)
`
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`The question becomes how does the fact that the limitations of claim 1 rely
`on an obviousness combination with Tsern effect the analysis. To that point,
`we recognize that “though anticipation is the epitome of obviousness, [they]
`are separate and distinct concepts.” Jones v. Hardy, 727 F.2d 1524, 1529
`(Fed.Cir.1984). It is that difference that is important here.
`The Federal Circuit has noted, however, that obviousness is different
`because: more than one reference can be used in obviousness; secondary
`considerations must be analyzed in obviousness; inherency in anticipation is
`different than obviousness (Cohesive Techs., Inc. v. Waters Corp., 543 F.3d
`1351, 1364 (Fed. Cir. 2008)); and single reference obviousness requires a
`showing of motivation to modify a reference when a party argues that such a
`modification must be made to meet the limitations of a claim (Monsanto
`Tech. LLC v. E.I. DuPont de Nemours & Co., 878 F.3d 1336, 1346 (Fed.
`Cir. 2018). Here, however, Petitioner relies on Averbuj alone, not on the
`combination of Averbuj and Tsern (or any modification of Avebuj), to meet
`any limitation of claim 1, Petitioner (here and in the ’970 IPR) did not rely
`on inherency to show any limitations of claim 1, and Patent Owner has not
`argued secondary considerations. See generally, Pet.; PO Resp.; Ex. 1028
`(’970 IPR FWD).
`Thus, the relevant legal issue, in this essentially single reference
`obviousness situation as to claim 1, is the same as in anticipation, i.e. does
`the reference teach the limitations of the claim. In fact anticipation requires
`a higher level of teaching requiring that references teach limitations of a
`claim explicitly or inherently. Under obviousness, the reference need only
`render a limitation obvious to one of skill in the art at the time of the
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`invention. Thus, the adage “anticipation is the epitome of obviousness.”
`Jones, 727 F.2d at 1529. The Board is allowed to rely on findings regarding
`whether a reference anticipates a limitation in its obviousness analysis.4 See
`Wasica Fin. GmbH v. Cont’l Auto. Sys., Inc., 853 F.3d 1272, 1278 (Fed. Cir.
`2017) (stating approvingly in a footnote that the “Board noted that Oselin
`rendered [the challenged claims] obvious by virtue of its anticipation of
`them.”) (citing Connell v. Sears, Roebuck & Co., 722 F.2d 1542, 1548 (Fed.
`Cir. 1983)).
`Also, as to the remaining prongs of the United Access test, the issue of
`whether Averbuj teaches the limitations of claim 1 was actually decided in a
`final decision on the merits, the issue was necessary to the final decision
`because it went to the ultimate issue of patentability, and there is no
`allegation that Patent Owner was not adequately represented in the prior
`action. Thus, for the reasons above, claim 1 is anticipated by Averbuj under
`the doctrine of collateral estoppel and the issue of whether the limitations of
`claim 1 are met by Averbuj by obviousness over Averbuj and Tsern also is
`established under the doctrine of collateral estoppel. Thus, we terminate this
`proceeding as to claim 1.
`
`
`4 In fact, the Board relied on this principle in the Decision to Institute. Dec.
`to Inst. 8 (“[W]e determine that claim 1 is anticipated by Averbuj. Inasmuch
`as ‘anticipation is the epitome of obviousness’ (In re McDaniel, 293 F.3d
`1379, 1385 (Fed. Cir. 2002)), we determine that Petitioner has established a
`reasonable likelihood of prevailing in its assertion that claim 1 would have
`been obvious over Averbuj alone.”).
`
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`Our reviewing court has recently ordered the Board, on remand, to
`assess whether claims depending from a claim that has been finally
`adjudicated as unpatentable should not also be found unpatentable for the
`same reasons as the independent claim. MaxLinear, Inc., 880 F.3d at 1377–
`1378. We apply this analysis to claims 2–7. Claims 2–7 have not been
`finally adjudicated as unpatentable in any previous case. Because the
`differences between the unadjudicated patent claims 2–7 and the adjudicated
`patent claim 1 materially alter the question of unpatentability, collateral
`estoppel does not apply. Cf. In re Arunachalam, 709 F. App’x 699, 702
`(Fed. Cir. 2017) (unpublished) (finding collateral estoppel applies to an
`adjudicated claim that is not “materially different” than the adjudicated
`claims); accord MaxLinear, Inc., 880 F.3d at 1377–1378. In this case, there
`are material differences between claims 2–7 and claim 1. For example,
`claim 2, from which claims 3–7 depend, recites a PCB and that the “data
`handlers” of claim 1 are separate components. It is still true, however, as
`Petitioner asserts, “Patent Owner is precluded from relitigating here whether
`Averbuj discloses all the limitations of claim 1, as arranged in the claim,
`including for purposes of determining the patentability of claims 2–7.” Pet.
`Show Cause Resp. 3. Thus, we do not terminate as to claims 2–7 under
`collateral estoppel.
`
`B. Relevant Law
`
`1. Obviousness Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`
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`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which said subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and, (4) where in evidence, so-called secondary
`considerations, including commercial success, long-felt but unsolved needs,
`failure of others, and unexpected results.5 Graham v. John Deere Co.,
`383 U.S. 1, 1718 (1966) (“the Graham factors”).
`2. Level of Skill Law
`The level of ordinary skill in the art usually is evidenced by the
`references themselves. See Okajima v. Bourdeau, 261 F.3d 1350, 1355
`(Fed. Cir. 2001); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In
`re Oelrich, 579 F.2d 86, 91 (CCPA 1978). For an obviousness analysis,
`prior art references must be “considered together with the knowledge of one
`of ordinary skill in the pertinent art.” In re Paulsen, 30 F.3d 1475, 1480
`(Fed. Cir. 1994) (quoting In re Samour, 571 F.2d 559, 562 (CCPA 1978)).
`Moreover, “it is proper to take into account not only specific teachings of the
`reference but also the inferences which one skilled in the art would
`reasonably be expected to draw therefrom.” In re Preda, 401 F.2d 825, 826
`(CCPA 1968). That is because an obviousness analysis “need not seek out
`
`
`5 Patent Owner does not put forth evidence it alleges tend to show secondary
`considerations of non-obviousness in its Response.
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`precise teachings directed to the specific subject matter of the challenged
`claim, for a court can take account of the inferences and creative steps that a
`person of ordinary skill in the art would employ.” KSR, 550 U.S. at 418; see
`also In re Translogic Tech., Inc., 504 F.3d at 1259.
`3. Claim Interpretation Law
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. 37 C.F.R. § 42.100(b). Under this standard, we
`interpret claim terms using “the broadest reasonable meaning of the words in
`their ordinary usage as they would be understood by one of ordinary skill in
`the art, taking into account whatever enlightenment by way of definitions or
`otherwise that may be afforded by the written description contained in the
`applicant’s specification.” In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
`1997).
`We presume that claim terms have their ordinary and customary
`meaning. See Trivascular, Inc. v. Samuels, 812 F.3d 1056, 1062 (Fed. Cir.
`2016) (“Under a broadest reasonable interpretation, words of the claim must
`be given their plain meaning, unless such meaning is inconsistent with the
`specification and prosecution history.”); In re Translogic Tech., Inc., 504
`F.3d 1249, 1257 (Fed. Cir. 2007) (“The ordinary and customary meaning is
`the meaning that the term would have to a person of ordinary skill in the art
`in question.” (internal citation and quotation marks omitted)). A patentee,
`however, may rebut this presumption by acting as his or her own
`lexicographer, providing a definition of the term in the specification with
`“reasonable clarity, deliberateness, and precision.” In re Paulsen, 30 F.3d
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`1475, 1480 (Fed. Cir. 1994). Only those terms that are in controversy need
`to be construed, and only to the extent necessary to resolve the controversy.
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999); Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co. Ltd., 868
`F.3d 1013, 1017 (Fed. Cir. 2017).
`C. Level of Skill Analysis
`Petitioner asserts “[a] a person of ordinary skill in the art at the time of
`the ‘434 Patent would have been someone with “a Bachelor’s degree in
`electrical engineering, computer engineering, or in a related field and at least
`one year of work experience relating to memory systems, and would be
`familiar with the design of memory devices, memory modules, and BIST.”
`Pet. 9 (citing Ex. 1003 ¶ 51). Patent Owner asserts through its declarant:
`[A Person of ordinary skill in the art at the time of the invention
`would have been] working on the design of memory devices,
`would have at least a Bachelor of Science degree in Electrical
`and/or Computer Engineering, and at least five years of industry
`experience designing memory devices and controllers.
`Alternatively, one of ordinary skill in the art would have a
`Master of Science degree in Electrical and/or Computer
`Engineering, and at least three years of industry experience
`designing memory devices and controllers. Also alternatively,
`one of ordinary skill in the art would have a Doctorate degree
`in Electrical and/or Computer Engineering, and have at least
`one year of industry experience designing memory devices and
`controllers.
`I agree with Petitioner’s expert that the memory industry
`requires a POSITA with industry experience.
`
`Ex. 2010 ¶¶ 32–33.
`
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`Neither party has argued that the difference between the parties’
`articulated level of skill should change the analysis as to patentability.
`Therefore, we adopt Petitioner’s articulation of the level of skill, above, and
`acknowledge that, commensurate with that articulation of the level of skill,
`the level of ordinary skill in the art is also reflected by the prior art of record.
`See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re
`GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re Oelrich, 579 F.2d 86,
`91 (CCPA 1978).
`
`D. Claim Construction Analysis
`Claims 2–7 do not recite claim limitations whose constructions are in
`controversy. Patent Owner disputes only the construction for the term
`“memory module,” recited in claim 1. PO Resp. 17–25. The “memory
`module” is not argued as a reason that Averbuj or Tsern do not meet the
`limitations of claims 2–7. Id. at 60–71. Thus, we do not further construe
`any terms including memory module in this Final Written Decision.
`E. Claims 1–7 — Anticipation by Averbuj (Ex. 1005) (Ground 1)
`Petitioner argues that claims 1–7 are unpatentable over Averbuj under
`35 U.S.C. § 102. Pet. 24–48. We refer to this as “Ground 1.”
`1. Averbuj (Ex. 1005)
`Averbuj describes a hierarchical built-in self-test (BIST) architecture
`wherein a BIST controller provides centralized, high level control of the
`testing of one or more memory modules. Ex. 1005 ¶¶ 7–8. Figure 1 of
`Averbuj is reproduced below.
`
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`Averbuj Figure 1, above, “is a block diagram illustrating an example
`electronic device 2 having a distributed, hierarchical built-in self-test (BIST)
`architecture.” Id. ¶ 28. “[E]lectronic device 2 may be any device that
`incorporates memory modules, such as an embedded computing system, a
`computer, server, personal digital assistant (PDA), mobile computing
`device, mobile communication device, digital recording device, network
`appliance, mobile positioning device, and the like.” Id. ¶ 32. Averbuj states
`that “electronic devices . . . are [normally] constructed from many integrated
`circuit chips and many supporting components mounted on a circuit board.”
`Id. ¶ 5. “[E]lectronic device 2 includes a built-in self-test (BIST) controller
`4 that provides centralized, high-level control over testing of device blocks
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`6A through 6N (collectively ‘device blocks 6’).” Id. ¶ 28. “Each of device
`blocks 6 includes a Sequencer 8, and a set of one or more memory interfaces
`10 and one or more respective memory modules 12.” Id. BIST controller 4
`provides and communicates test algorithms as a set of commands to
`Sequencers 8 for application to device blocks 6. Id. ¶ 29.
`Figure 5, below, illustrates an exemplary Sequencer 8A. Id. ¶ 22
`
`
`
`As shown in Figure 5, above, exemplary Sequencer 8A includes
`command parser 30 and command controllers 34. Id. ¶¶ 41–42. Command
`parser 30 processes the commands from BIST controller 4 and invokes one
`of command controllers 34, which, in turn, issues command control signals,
`such as signals to provide a memory address and data, to receiving memory
`
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`interfaces 10, 41. Id. ¶¶ 43, 51. An exemplary memory interface is shown
`in Figure 6, below. Id. ¶ 23.
`
`
`
`As shown in the Figure 6 embodiment, above, memory interface 41
`includes multiplexers 45, 46. Id. ¶ 48. “[U]nder normal operating
`conditions, BIST enable (BIST_EN) is de-asserted, causing multiplexers 45,
`46 to select the address/control signals (ADDR/CTRL) and data signals
`(DATA), e.g., as provided by a programmable processor.” Id. “When
`electronic device 2 is operating in BIST mode, however, the BIST enable
`signal causes multiplexers 45, 46 to select the BIST address/control signals
`
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`(BIST_ADDR/CTRL) and the test data provided by a respective higher level
`Sequencer[, e.g., Sequencer 8A].” Id.
`“[M]emory interface 41 processes the sequential memory operations
`issued by [] higher-level Sequencer [8A], and transforms the data and
`addresses provided by the Sequencer as needed based on the particular
`physical characteristics of the memory module” (id. ¶ 54), using address
`generation unit 42 and data generation unit 44 (id. ¶¶ 49, 51). “[A]ddress
`generation unit 42 generates the address applied to [] memory module 12
`based on the addressing requirements specified by Sequencer 8A and the
`physical configuration of the rows and columns of the memory module.”
`Id. ¶ 51. “[D]ata generation unit 44 [] receives BIST _DATA signals and
`default data (DEFAULT_DIN) as provided by [] Sequencer 8[A], and
`generates transformed BIST data signals 49 (BIST_DATA_T) based on
`control signals (BIST_DATA_GEN_CTRL) provided by the Sequencer and
`the specific physical characteristics of the corresponding memory module.”
`Id. ¶ 49. “[D]ata generation unit 44 generates the exact data (RAM_DIN)
`applied to the memory inputs during each operation of the algorithm.” Id.
`2.
`Analysis
`Claim 1
`a.
`Claim 1 is anticipated by Averbuj under the doctrine of collateral
`estoppel. See supra Section II. A.
`b.
`Claim 2
`In the Institution Decision, we found Petitioner has failed to establish
`a reasonable likelihood of prevailing in its assertion that claims 2–7 are
`anticipated by Averbuj. Inst. Dec. 22–23, 33. We now analyze this ground
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`based on the full record before us and under the preponderance of the
`evidence standard. Claim 2 recites “[t]he self-testing memory module of
`claim 1, wherein the plurality of data handlers comprise at least two
`physically separate components mounted on the printed circuit board.”
`Petitioner asserts that
`Averbuj further discloses that electronic devices, such as his
`electronic device (2), are constructed from many integrated
`circuit chips and other components mounted on a circuit board.
`Ex. 1005 at ¶ [0005] (“[The electronic devices] are constructed
`from many integrated circuit chips and many supporting
`components mounted on a circuit board.”); Ex. 1003 ¶ 154.
`Averbuj discloses that BIST units are commonly incorporated
`into chips or integrated circuits, which are synonyms. Ex. 1005
`at ¶ [0003]; Ex. 1012 at 3, 5. Because the memory interface (12)
`is part of a BIST unit, it comprises a chip or an integrated circuit
`of an electronic device “mounted on a circuit board.” Ex. 1005
`at ¶ [0005]; Ex. 1003 ¶ 154.
`
`
`Pet. 41. In other words, Petitioner asserts that because a BIST unit can be
`incorporated into a chip mounted on a PCB and because memory module 12
`is part of the BIST unit, memory unit 12 is mounted on a PCB. We disagree.
`Unlike claim 1, which simply requires the memory unit is “on” the
`PCB, claim 2 requires that the memory module be a “physically separate
`component” and “mounted” on the PCB. Petitioner has not shown sufficient
`support for its broad reading that a module which is a circuit embedded in a
`larger circuit included in a chip may be considered a physically separate
`component mounted on a PCB. Claims 3–7 depend from claim 2, and the
`Petition
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