Trials@uspto.gov
`571-272-7822
`
`
` Paper No. 34
`Entered: June 20, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioners,
`
`v.
`
`NETLIST, INC.
`Patent Owner.
`____________
`
`IPR2017-00587
`Patent 8,671,243 B2
`____________
`
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`McSHANE, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`
`
`571-272-7822
`
`
` Paper No. 34
`Entered: June 20, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioners,
`
`v.
`
`NETLIST, INC.
`Patent Owner.
`____________
`
`IPR2017-00587
`Patent 8,671,243 B2
`____________
`
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`McSHANE, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`
`
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`IPR2017-00587
`Patent 8,671,243 B2
`
`I. INTRODUCTION
`A. Background
`
`SK hynix Inc., SK hynix America Inc. and SK hynix memory
`solutions Inc. (“Petitioner”) filed a Petition requesting inter partes review of
`claims 1–30 (“the challenged claims”) of U.S. Patent No. 8,671,243 B2 (Ex.
`1001, “the ’243 patent”) pursuant to 35 U.S.C. §§ 311–319. Paper 1
`(“Pet.”). Netlist, Inc. (“Patent Owner”) filed a Preliminary Response to the
`Petition. Paper 6 (“Prelim. Resp.”). Pursuant to 35 U.S.C. § 314, we
`instituted an inter partes review as to claims 1–30 of the ’243 patent on June
`22, 2017, but we did not institute on all of the asserted grounds. Paper 7
`(“Dec.” or “Institution Decision”), 10–39. On April 24, 2018, the Supreme
`Court held that a decision to institute under 35 U.S.C. § 314 may not
`institute on less than all claims challenged in the petition. SAS Inst., Inc. v.
`Iancu, 138 S.Ct. 1348, 1358 (2018). Pursuant to SAS, we issued an Order
`modifying the Institution Decision to include a review of all challenged
`claims and all grounds. Paper 33, 2. Accordingly, the following grounds
`have been instituted:
`Ground Claim(s)
`§ 1021
`1–3, 5–15, 17–30
`§ 103
`4, 16
`§ 103
`1, 3, 13, 15, 25
`§ 103
`6, 18
`
`Prior Art
`Shimada2
`Shimada and Oh3
`Shimada and Bonella4
`Shimada
`
`
`1 Petitioner asserts that Shimada is prior art to the ’243 patent under
`§§ 102(a), (b), and (e). Pet. 13.
`2 U.S. Patent No. 6,693,840 B2 (issued February 17, 2004) (Ex. 1005).
`3 U.S. Patent No. 7,486,104 B2 (issued February 3, 2009) (Ex. 1012).
`4 U.S. Publication No. 2007/0136523 A1 (issued June 14, 2007) (Ex. 1009).
`2
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`Patent 8,671,243 B2
`Ground Claim(s)
`§ 103
`9, 21, 28
`§ 103
`10, 22, 29
`§ 103
`11, 12, 23, 24, 30
`
`Prior Art
`Shimada and Goodwin5
`Shimada and Sasaki6
`Shimada and Tsunoda7
`
`Pet. 3.
`During the course of trial, Patent Owner filed a Patent Owner
`Response (Paper 12, “PO Resp.”), and Petitioner filed a Reply to the Patent
`Owner Response (Paper 16, “Pet. Reply”). Petitioner submitted the
`Declaration of Ron Maltiel (Ex. 1003). Patent Owner submitted the
`Declaration of R. Jacob Baker, Ph.D., P.E. (Ex. 2016).
`
`Petitioner filed a Motion to Exclude Evidence (Paper 19, “Pet. Mot.
`Ex.”), with Patent Owner filing an Opposition the Motion to Exclude (Paper
`26, “PO Mot. Ex. Opp.”), and Petitioner filing a Reply thereto (Paper 28,
`“Pet. Mot. Ex. Reply”). Patent Owner filed a Motion to Exclude Evidence
`(Paper 21, “PO Mot. Ex.”), with Petitioner filing an Opposition the Motion
`to Exclude (Paper 24, “Pet. Mot. Ex. Opp.”), and Patent Owner filing a
`Reply thereto (Paper 29, “PO Mot. Ex. Reply”). Patent Owner also filed a
`Listing of New Arguments and Evidence in Petitioner’s Reply (Paper 25,
`“PO Obj.”), with Petitioner filing a Response (Paper 27, “Pet. Resp. Obj.”).
`
`We held a consolidated oral hearing on February 14, 2018, in relation
`to this proceeding and other proceedings involving the same parties. A
`transcript (Paper 32, “Tr.”), of the oral hearing has been entered into the
`record.
`
`5 U.S. Patent No. 4,658,204 (issued April 14, 1987) (Ex. 1015).
`6 U.S. Patent No. 6,721,212 B2 (issued April 13, 2004) (Ex. 1017).
`7 U.S. Publication No. 2003/0028733 Al (published February 6, 2003) (Ex.
`1019).
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`Patent 8,671,243 B2
`We have jurisdiction to hear this inter partes review under 35 U.S.C.
`§ 6, and this Final Written Decision is issued pursuant to 35 U.S.C. § 318(a)
`and 37 C.F.R. § 42.73. For the reasons that follow, we determine that
`Petitioner has shown by a preponderance of the evidence that claims 1–30 of
`the ’243 patent are unpatentable. We grant-in-part and deny-in-part
`Petitioner’s Motion to Exclude and deny Patent Owner’s Motion to Exclude
`as moot.
`
`B. Related Proceedings
`
`Patent Owner indicates related matters are: Netlist, Inc. v. Smart
`Modular Technologies, Inc., Case No. 3:13-cv-05889-YGR (N.D. Cal.);
`Netlist, Inc. v. Smart Modular Technologies, Inc., Case No. 2:13-cv-02613-
`TLN (E.D. Cal.); SanDisk Corp. v. Netlist, Inc., Case No. IPR2014-00982
`(PTAB); SanDisk Corp. v. Netlist, Inc., Case No. IPR2014-00994 (PTAB),
`Smart Modular Technologies, Inc. v. Netlist, Inc., Case No. IPR2014-01371
`(PTAB); Smart Modular Technologies, Inc. v. Netlist, Inc., Case No.
`IPR2014-01370 (PTAB); SK hynix Inc., et al. v. Netlist, Inc., Case No.
`IPR2017-00649 (PTAB); and SK hynix Inc., et al. v. Netlist, Inc., Case No.
`IPR2017-00561 (PTAB). Paper 4, 2–3. Patent Owner also indicates that
`related U.S. Patent Application Nos. 15/000,834, 14/489,281, and
`14/840,865 are pending. Id. at 4.
`C. The ’243 Patent
`The ’243 patent is entitled “Isolation Switching For Backup
`
`Memory,” and issued on March 11, 2014, from an application filed on May
`29, 2013. Ex. 1001, [22], [45], [54]. The ’243 patent claims priority to (1)
`U.S. Patent Application No. 13/536,173, filed on June 28, 2012 (now U.S.
`Patent No. 8,516,187); (2) U.S. Application No. 12/240,916, filed on
`
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`September 29, 2008 (now U.S. Patent No. 8,301,833); (3) U.S. Application
`No. 12/131,873, filed on June 2, 2008; and (4) U.S. Provisional Application
`No. 60/941,586, filed on June 1, 2007. Id. at [60].
`
`The ’243 patent is directed to a memory module system that has a
`volatile memory subsystem, non-volatile memory subsystem, and controller.
`Ex. 1001, Abstract, 3:21–24. The memory module system may switch
`between two states of operation. Id. at 7:49–50. In the first state, a circuit
`couples the volatile memory subsystem to the host system while isolating the
`volatile memory subsystem from the non-volatile memory subsystem. Id.,
`Abstract, 7:50–54. In a second state, a circuit allows data to be
`communicated between the volatile and non-volatile memory subsystems by
`coupling the respective subsystems and isolating the volatile memory system
`from the host system. Id., Abstract, 7:54–58. The memory system uses the
`volatile memory subsystem under normal conditions, but provides back-up
`functions using the non-volatile memory subsystem. Id. at 3:24–27, 6:23–
`34, 7:49–62. In the event of a trigger condition, which may include a power
`failure or power reduction, the controller backs up the system by transferring
`data from a volatile memory system to a non-volatile memory system. Id. at
`3:24–28. The configuration is directed to protecting the operation of the
`volatile memory in the two modes of operation while providing backup and
`restore capability in the event of a trigger condition. Id. at 3:32–36, 3:41–
`45, 8:17–30.
`
`Claims 1, 13, and 24 are independent claims, and the other claims at
`issue are dependent claims, depending directly or indirectly from claims 1,
`13, and 24. Ex. 1001, 20:30–23:20. Claim 1, reproduced below, is
`illustrative of the challenged claims of the ’243 patent.
`
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`1. A memory system comprising:
`
`a volatile memory subsystem;
`a non-volatile memory subsystem;
`a controller coupled to the non-volatile memory subsystem; and
`a circuit coupled to the volatile memory subsystem, to the
`controller, and to a host system, wherein:
`in a first mode of operation, the circuit is operable to
`selectively isolate the controller from the volatile memory
`subsystem, and to selectively couple the volatile memory
`subsystem to the host system to allow data to be communicated
`between the volatile memory subsystem and the host system,
`and
`
`in a second mode of operation, the circuit is operable to
`selectively couple the controller to the volatile memory
`subsystem to allow data to be communicated between the
`volatile memory subsystem and the nonvolatile memory
`subsystem using the controller, and the circuit is operable to
`selectively isolate the volatile memory subsystem from the host
`system.
`Ex. 1001, 20:30–49.
`
`II. ANALYSIS
`A. The Parties’ Post-Institution Arguments
`In our Decision on Institution, we concluded that the arguments and
`evidence advanced by Petitioner demonstrated a reasonable likelihood that
`claims 1–30 of the ’243 patent are unpatentable under 35 U.S.C. § 102
`and/or 35 U.S.C. § 103 over asserted prior art. Inst. Dec. 38–39. We now
`determine whether Petitioner has established by a preponderance of the
`evidence that claims 1–30 are unpatentable under 35 U.S.C. § 102 and/or 35
`U.S.C. § 103(a) over the cited prior art. 35 U.S.C. § 316(e). We previously
`instructed Patent Owner that “any arguments for patentability not raised in
`the [Patent Owner Response] will be deemed waived.” Paper 8, 3; see also
`
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`37 C.F.R. § 42.23(a) (“Any material fact not specifically denied may be
`considered admitted.”); In re Nuvasive, Inc., 842 F.3d 1376, 1379–82 (Fed.
`Cir. 2016) (holding Patent Owner waived an argument addressed in
`Preliminary Response by not raising the same argument in the Patent Owner
`Response). Additionally, the Board’s Trial Practice Guide states that the
`Patent Owner Response “should identify all the involved claims that are
`believed to be patentable and state the basis for that belief.” Office Patent
`Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012).
`With a complete record before us, we note that we have reviewed
`arguments and evidence advanced by Petitioner to support its unpatentability
`contentions where Patent Owner chose not to address certain limitations in
`its Patent Owner Response. Where Patent Owner has provided argument
`and evidence in the Patent Owner Response, it has been considered. In this
`regard, the record now contains persuasive arguments and evidence
`presented by Petitioner regarding the manner in which the asserted prior art
`teaches corresponding limitations of claims 1–30 on all the grounds, except
`for the assertion of anticipation against claims 9–12, 21–24, and 28–30 by
`Shimada because the arguments and evidence provided for this ground in the
`Petition were insufficient. Based on the preponderance of the evidence
`before us, we conclude that the art identified by Petitioner discloses, teaches,
`or suggests all of the limitations of the reviewed claims on all grounds,
`except for the ground asserting anticipation against claims 9–12, 21–24, and
`28–30 by Shimada.
`
`B. Claim Construction
`
`In an inter partes review, the Board interprets claim terms in an
`unexpired patent according to the broadest reasonable construction in light
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`of the specification of the patent in which they appear. 37 C.F.R.
`§ 42.100(b). Under that standard, and absent any special definitions, we
`give claim terms their ordinary and customary meaning, as they would be
`understood by one of ordinary skill in the art at the time of the invention.
`In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`We address the claim terms at issue below.
`“in a first mode of operation, the circuit is operable to
`selectively isolate . . . and to selectively couple the volatile memory
`subsystem to the host system”
`“in a second mode of operation, the circuit is operable to selectively couple
`. . . and the circuit is operable to selectively isolate the volatile memory
`subsystem from the host system”
`
`In the Petition, Petitioner proposed that the entire “first mode”
`limitation be construed as one “in which the circuit does not allow
`communication between the controller and the volatile memory subsystem
`while allowing communication between the volatile memory subsystem and
`the host system,” and that the entire “second mode” limitation be construed
`as one “in which the circuit does not allow communication between the
`volatile memory subsystem and the host system while allowing
`communication between the volatile memory subsystem and the controller.”
`Pet. 8–9, 11. In the Institution Decision, we declined to recast the entire
`limitation with alternative wording, and alternatively construed “couple” to
`mean “operatively couple to allow interaction,” and construed “isolate” to
`mean “operatively decouple to not allow interaction.” Dec. 8–9.
`Patent Owner contends that the term “selectively” should be construed
`separately from the terms “couple” and “isolate” of the “mode” limitations.
`PO Resp. 20–30. Patent Owner did not agree with our preliminary
`interpretation of the terms “couple” and “isolate,” arguing that the addition
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`of “operatively” was not necessary. See PO Resp. 21–24. At oral hearing,
`Patent Owner indicated that the Board’s construction of the terms “couple”
`and “isolate” was not at issue or dispositive to the unpatentability
`challenges. See Tr. 104:15–105:5. Petitioner also contends that any dispute
`regarding the construction of these terms “couple” or “isolate” does not
`require resolution for the invalidity analysis. Pet. Reply 4. Accordingly, we
`determine that it is not necessary to provide construction of the claim terms
`“couple” and “isolate” because, as discussed below, the disputes relate only
`to the construction of the term “selectively.” Vivid Techs., Inc. v. Am. Sci. &
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)) (“[O]nly those terms need
`be construed that are in controversy, and only to the extent necessary to
`resolve the controversy.”).
`As to the term “selectively,” Patent Owner argues that Petitioner
`should not be permitted to read out the term from the claims, the term should
`be given effect, and it should be interpreted as “in response to a selection” in
`light of Specification, dictionary definitions, and the prosecution history.
`PO Resp. 24–30. Patent Owner contends that a Federal Circuit appeal
`decision concerning U.S. Patent Nos. 7,881,150 and 8,081,536 is relevant
`here. Id. at 28 (citing Ex. 2015, Appeal No. 2016-1742 (Netlist, Inc. v.
`Diablo Techs, Inc., 701 Fed. App’x 1001 (Fed. Cir. 2017) (“the Federal
`Circuit decision”))). Patent Owner argues that in that decision, the Federal
`Circuit ruled that the term “selectively electrically coupling” is “coupling in
`response to a selection.” Id.; see Netlist, 701 Fed. App’x at 1004. Patent
`Owner also alleges that the court agreed that the term referred to coupling or
`decoupling specific data lines, and not to the overall process of selecting
`components. Id.
`
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`Petitioner contends that under its proposed construction of the entire
`“in the first mode . . .” and “in the second mode . . .” limitations, the term
`“‘selectively’ has not been read out of the claims.” Pet. Reply 6 (citing Pet.
`8–11). Petitioner does not dispute Patent Owner’s proposed construction of
`the term “selectively,” except to the extent that the term requires
`“independent” selection. See id. at 4–6. Petitioner also argues that the
`Patent Owner’s reliance on the Federal Circuit decision8 is flawed, and
`Petitioner distinguishes the claims, where the claims in the Federal Circuit
`case were directed to selectively coupling signal lines, which are not at issue
`here. Id. at 7–8.
`Patent Owner views the claim construction of the term “selectively”
`as dispositive (see Tr. 104:16), even though Petitioner’s position is that
`Shimada discloses all the claim limitations, even under Patent Owner’s
`construction of the claim term (see id. at 113:6–13). The apparent
`discrepancy in the parties’ views is discussed infra Section II.D.
`Here, we adopt Patent Owner’s proposed construction of the term
`“selectively,” as “in response to a selection.” This is consistent with the
`ordinary meaning of the term and the use of the term in the Specification.
`And although the Federal Circuit decision is not directly relevant to the
`patent at issue here (see infra, Section II.D and IV), the Federal Circuit’s
`manner of considering “selectively electrically coupling” as “coupling in
`response to a selection” similarly parses out the limitation of “selecting” as
`applied here. See Netlist, 701 Fed. App’x at 1004. However, the remainder
`of the claim in the Federal Circuit decision is different than claim 1 of the
`’243 patent—the claim at issue there is directed to “selectively electrically
`
`8 Patent Owner moves to exclude the Federal Circuit decision from
`evidence. See infra Section IV.
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`coupling” “data signal line[s],” and the claim here is to “selectively couple”
`components such as a controller and volatile memory subsystem. See id.
` “communicated between”
`Patent Owner argues that the term “communicated between” should
`be construed as “moved in either direction.” PO Resp. 30–31. In support,
`Patent Owner refers to a portion of the ’243 patent Specification describing
`data being “backed-up” from the volatile to non-volatile memories, and then
`restored. Id. (citing Ex. 1001, Fig. 4A; Ex. 2016 ¶ 91). Petitioner contends
`that Patent Owner also indicates that “either direction” means “both
`directions.” Pet. Reply 9 (citing PO Resp. 54). Petitioner argues that the
`broadest reasonable interpretation of the term “communicated between”
`should not require communication in “both directions.” Id. (citing Ex. 1001,
`17:27–33).
`In light of the Specification and the ordinary meaning of the term, we
`agree with Patent Owner’s proposed construction permitting communication
`of data in “either direction,” but we agree with Petitioner that the ordinary
`meaning of the term “between” does not require data to be communicated in
`both directions.
`
`Other Terms
`
`Although Patent Owner proposes the construction of additional claim
`terms, we determine that it is not necessary to provide an express
`interpretation of any other term of the claims because it is not necessary to
`resolve any issues or disputes. See Vivid Techs., 200 F.3d at 803.
`
`C.
`
`Level of Ordinary Skill in the Art
`
`Petitioner contends that a person of ordinary skill in the art at the time
`
`of the ’243 invention would have had “a Bachelor’s degree in materials
`
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`science, electrical engineering, computer engineering, computer science, or
`in a related field and at least one year of experience with the design or
`development of semiconductor non-volatile memory circuitry or systems.”
`Pet. 4 (citing Ex. 1003 ¶¶ 49–50).
`
`Patent Owner asserts that a person of ordinary skill in the art would
`have “a Bachelor’s degree in electrical and/or computer engineering and at
`least five years of industry experience designing memory devices and
`controllers,” and a Master of Science degree could substitute for two years
`of industry experience. PO Resp. 1–2 (citing Ex. 2016 ¶ 35). Patent Owner
`contends that “[a] degree in material science engineering alone would not
`suffice as an equivalent to a degree in electrical and/or computer
`engineering.” Id. (citing Ex. 2016 ¶¶ 33–34). Based upon its proposed
`educational foundation, Patent Owner argues that some claim terms would
`be understandable to a person of ordinary skill in the art, “but not necessarily
`to Petitioner’s expert who lacks that level of skill.” Id. at 34.
`Although we agree with the Patent Owner that a degree in material
`science alone is not equivalent to a degree in electrical engineering, we also
`agree with Dr. Baker, Patent Owner’s expert, that industry experience can
`substitute for and supplement an educational degree. See Ex. 1030, 55:6–12.
`In this case, we find Petitioner’s proposed qualifications for education, with
`the addition of at least five years of industry experience, to be sufficient.
`Therefore, to the extent necessary, we adopt Petitioner’s assessment of the
`qualifications, with the addition of five years of experience, as sufficient for
`one of ordinary skill in the art.
`Mr. Maltiel, Petitioner’s expert, is senior member of IEEE with more
`than 30 years of experience in design and implementation of computer
`semiconductor devices, including memory chips. Ex. 1004, 1. Mr. Maltiel’s
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`experience is sufficient to supplement his educational degree and qualify
`him as a person of skill in the art for the purposes of this proceeding.
`
`D.
`
`Asserted Anticipation of Claims 1–3, 5–15, and 17–30 over Shimada
`
`In support of this asserted ground of unpatentability, Petitioner
`
`explains how Shimada anticipates claims 1–3, 5–15, and 17–30. Pet. 18–55.
`In its Response, Patent Owner contends that Petitioner fails to demonstrate
`anticipation because Shimada fails to disclose some of the claim limitations.
`See PO Resp. 37–58.
`We find that Petitioner has demonstrated by a preponderance of the
`evidence that Shimada anticipates claims 1–3, 5–8, 13–15, 17–20, and 25–
`27 for the reasons discussed below. Petitioner has not demonstrated by a
`preponderance of the evidence that Shimada anticipates claims 9–12, 21–24,
`or 28–30.
`We begin our analysis with a summary of Shimada, and then address
`the arguments and evidence presented by the parties.
`1. Shimada (Ex. 1005)
`Shimada generally discloses a semiconductor memory device that
`includes a volatile memory and non-volatile memory. Ex. 1005, 3:45–49.
`Figure 2 of Shimada is reproduced below.
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`Figure 2 depicts a functional block diagram illustrating an
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`embodiment of a semiconductor memory device. Ex. 1005, 3:18–20.
`Shimada’s semiconductor memory device has control unit 102, volatile
`memory 103, non-volatile memory 104, selector 101, and power-supply unit
`105. Id. at 3:47–48. Power-supply unit 105 directs externally supplied
`power and also accumulates power required by control unit 102 to save data
`from volatile memory 103 to non-volatile memory 104. Id. at 4:43–53.
`With the start of an external power supply, the control unit restores data of
`the non-volatile memory in the volatile memory, and when the external
`power supply has stopped, as detected by a voltage reduction in the main
`power source, the control unit saves data from the volatile memory to the
`non-volatile memory. Id. at 1:41–45, 3:64–4:6, 4:10–15.
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`Control unit 102 controls operation of semiconductor memory device
`1 and receives a reference signal from outside of it, “and performs data
`copying between volatile memory 103 and non-volatile memory 104 (i.e.[,]
`save or restore), according to the reference signal.” Ex. 1005, 3:54–59.
`Shimada’s selector 101 receives a signal sent from control unit 102 to switch
`between two different modes in which access to volatile memory 103 is
`allowed differently. Id. at 4:20–23. When select signal (H) is received,
`selector 101 allows access from outside the semiconductor memory device 1
`to the volatile memory 103; and when select signal (L) is received, the
`selector 101 allows the control unit 102 to access the volatile memory 103.
`Id. at 4:20–27.
`
`2. Analysis
`To prevail on its challenges to the patentability of the claims, a
`
`petitioner must establish facts supporting its challenge by a preponderance
`of the evidence. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). “In an [inter
`partes review], the petitioner has the burden from the onset to show with
`particularity why the patent it challenges is unpatentable.” Harmonic Inc. v.
`Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed Cir. 2016) (citing 35 U.S.C.
`§ 312(a)(3) (requiring inter partes review petitions to identify “with
`particularity . . . the evidence that supports the grounds for the challenge to
`each claim”)). This burden of persuasion never shifts to the patent owner.
`See Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378–
`79 (Fed. Cir. 2015) (discussing the burdens of persuasion and production in
`inter partes review).
`A claim is unpatentable under 35 U.S.C. § 102 if a prior art reference
`discloses each and every element of the claimed invention, either explicitly
`or inherently. Glaxo Inc. v. Novopharm Ltd., 52 F.3d 1043, 1047 (Fed. Cir.
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`1995); see MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362, 1365
`(Fed. Cir. 1999) (“To anticipate, a claim a prior art reference must disclose
`every limitation of the claimed invention . . . ;” any limitation not explicitly
`taught must be inherently taught and would be so understood by a person
`experienced in the field); In re Baxter Travenol Labs., 952 F.2d 388, 390
`(Fed. Cir. 1991) (the dispositive question is “whether one skilled in the art
`would reasonably understand or infer” that a reference teaches or discloses
`all of the elements of the claimed invention).
`a. Claim 1
`Petitioner asserts that claim 1 is unpatentable as anticipated by
`Shimada. Pet. 18–55; Pet. Reply 11–22.9 Patent Owner disagrees with
`Petitioner’s assertions, focusing its arguments on Shimada’s alleged failure
`to disclose the “circuit” as claimed. See PO Resp. 37–55.
`Petitioner contends that Shimada discloses a volatile memory,
`nonvolatile memory, and controller corresponding to the claim limitations.
`Pet. 18–22. The Petition argues that selector 101 within semiconductor
`memory device 1, as depicted in Figure 2 of Shimada, is coupled to the
`volatile memory subsystem, controller, and host system, as claim 1 recites.
`Id. at 22–24. Petitioner asserts that Shimada discloses that the claimed first
`mode of operation when selector circuit 101 receives input select signal (H),
`and, in this mode, selector 101 allows data to be communicated between
`
`
`9 Patent Owner asserts that portions of Petitioner’s Reply are allegedly
`beyond the scope of what is considered appropriate for a reply. See infra
`Section III. As discussed below, however, we find that the disputed portions
`of Petitioner’s Reply and associated evidence are within the scope of what is
`appropriate for a reply and may be considered. See id.
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`Patent 8,671,243 B2
`volatile memory and the host system. Id. at 24 (citing Ex. 1003 ¶ 119; Ex.
`1005, 4:6–9, 4:23–25, 4:28–33).
`Petitioner further contends that in the first mode, Shimada’s selector
`101 does not allow data communications between the host system and the
`remaining portions of the semiconductor memory device, including control
`unit 102. Pet. 24 (citing Ex. 1003 ¶ 120; Ex. 1005, 3:47–50, 5:30–34, 9:30–
`39). Mr. Maltiel’s testimony refers to Shimada’s “semiconductor memory
`device” that includes the “control unit 102” and “non-volatile memory 104,”
`and in the first mode, selector 101 shuts out access of the host system to
`control unit 102 and non-volatile memory 104. Ex. 1003 ¶ 120 (citing Ex.
`1005, 3:47–50, 9:30–39). Mr. Maltiel further testifies that when the first
`mode is selected, a person of skill in the art would understand that “selector
`101 has coupled the control signal, address signal and data signal lines of the
`outside system to the volatile memory 103 rather than signal lines of the
`control unit.” Id. ¶ 121. Mr. Maltiel additionally testifies that a skilled
`artisan would understand that the terms “selector” and “multiplexer” would
`be used interchangeably and cites to other prior art for support of that
`understanding. Id. ¶¶ 122–127. With this, Petitioner argues that Shimada
`discloses that in the first mode, “the circuit is operable to selectively isolate
`the controller from the volatile memory subsystem” as claimed. Pet. 24–25.
`
`Petitioner alleges that Shimada discloses the second mode of
`operation recited in claim 1 when the selector receives input select signal
`(L). Pet. 26. Petitioner argues that, in this mode, “the ‘selector 101’ allows
`data to be communicated between the ‘volatile memory 103’ and the
`‘nonvolatile memory 104’ using the ‘control unit 102.’” Id. (citing Ex. 1003
`¶¶ 136–137; Ex. 1005, 3:55–62, 4:26–27, 4:34–41). Petitioner further
`contends that when in this mode, “‘selector 101’ does not allow data to be
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`Patent 8,671,243 B2
`communicated between the ‘volatile memory 103’ and the host system.” Id.
`(citing Ex. 1005, 3:64–4:1, 4:10–15, Fig. 3). Referring to Figure 3 of
`Shimada, Petitioner identifies a first scenario where “selector 101” may
`receive an input select signal (L) after the reference signal has changed from
`L to H, then data is copied from non-volatile memory 104 to volatile
`memory 103, and “the control unit 102 . . . shuts out any access to the
`volatile memory 103 from outside, so that the control unit 102 may access
`the volatile memory 103.” Id. at 27 (citing Ex. 1003 ¶¶ 139, 140; Ex. 1005
`at 3:64–4:6, Fig. 3). In a second scenario, Petitioner alleges that “selector
`101” receives an input select signal (L) after the reference signal has
`changed from H to L, and data is copied from the volatile memory 103 to the
`non-volatile memory 104. Id. at 28 (citing Ex. 1003 ¶¶ 139, 141; Ex. 1005,
`4:14–16, Fig. 3). Petitioner avers that in this situation a person of ordinary
`skill understands that “the host system will not be able to communicate with
`the volatile memory 103 because the selector 101 has coupled the volatile
`memory 103 to the control signal, address signal and data signal lines of the
`control unit 102, rather than to the signal lines of the outside system.” Id.
`(citing Ex. 1003 ¶ 142).
`
`Petitioner’s anticipation analysis, as supported by Mr. Maltiel’s
`Declaration, relies on testimony as to where each element of the challenged
`claim 1 is disclosed in Shimada. Pet. 18–28; Ex. 1003 ¶¶ 94–144. After
`having considered Patent Owner’s arguments, which we address below, we
`agree with and adopt Petitioner’s analysis and credit Mr. Maltiel’s
`testimony.
`Patent Owner argues that Shimada fails to disclose the “circuit” as
`claimed because “[t]he Petition fails to show a memory system that
`comprises a first path that can selectively isolate or couple the host system
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`Patent 8,671,243 B2
`and the VMS [volatile memory subsystem] and a second path that can
`selectively isolate or couple the controller and the VMS.” PO Resp. 38.
`Patent Owner alleges that Shimada’s selector—the “circuit” as mapped by
`Petitioner—can only make a selection between operational modes. Id.
`Patent Owner refers to Shimada’s mode selection as discussed in its
`specification, as well as referring to Patent Owner’s annotated versions of
`Figure 2 of Shimada, which are reproduced below. See id at 39–40 (citing
`Ex. 1005, 4:20–27, Fig. 2).
`
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`
`
`Patent Owner’s annotated versions of Figure 2 of Shimada are reproduced
`above.
`Patent Owner additionally argues that in the first mode, the
`“selection” made is to “couple or decouple” the volatile memory subsystem
`and host system, “but not to select between the controller and the host
`system.” PO Resp. 41 (citing Ex. 2016 ¶ 116) (emphases in original); see id.
`at 29–30 (citing Ex. 2016 ¶¶ 87–88). Patent Owner similarly asserts that in
`the second mode, the “selection” is to couple or decouple the controller and
`the volatile memory subsystem, “not to select between the controller and the
`host system.” Id. (emphases in original). It is argued that “the term
`“selectively couple” cannot be reasonably interpreted as making a selection
`between two modes [of] operation.” Id. at 41–42 (citing Ex. 2016 ¶¶ 117,
`136). Patent Owner avers that “the disclosed circuit couples some
`components and not others . . . [b]ut the claim term “selectively” is directed
`to how the claimed circuit performs that function, which is by coupling or
`decoupling specific devices.” Ex. 2016 ¶ 118; see PO Resp. 29–30.
`
`
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`20
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`Patent 8,671,243 B2
`We are not persuaded by Patent Owner’s argument on mode sele
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