throbber
Trials@uspto.gov
`571-272-7822
`
`Paper No. 7
`Entered: June 22, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioners,
`
`v.
`
`NETLIST, INC.
`Patent Owner.
`____________
`
`IPR2017-00587
`Patent 8,671,243 B2
`____________
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`McSHANE, Administrative Patent Judge.
`
`DECISION
`Instituting Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`

`

`IPR2017-00587
`Patent 8,671,243 B2
`
`I. INTRODUCTION
`A. Background
`SK hynix Inc., SK hynix America Inc. and SK hynix memory
`solutions Inc. (“Petitioners”) filed a Petition requesting inter partes review
`of claims 1–30 (“the challenged claims”) of U.S. Patent No. 8,671,243 B2
`(Ex. 1001, “the ’243 patent”) pursuant to 35 U.S.C. §§ 311–319. Paper 1
`(“Pet.”). Netlist, Inc. (“Patent Owner”) filed a Preliminary Response to the
`Petition. Paper 6 (“Prelim. Resp.”).
`We have authority under 35 U.S.C. § 314(a), which provides that an
`inter partes review may not be instituted “unless . . . the information
`presented in the petition . . . shows that there is a reasonable likelihood that
`the Petitioner would prevail with respect to at least 1 of the claims
`challenged in the petition.”
`We determine that Petitioners have demonstrated that there is a
`reasonable likelihood that they would prevail with respect to at least one of
`the challenged claims. For the reasons described below, we institute an inter
`partes review of claims 1–30 of the ’243 patent.
`B. Related Proceedings
`Patent Owner indicates related matters are: Netlist, Inc. v. Smart
`Modular Technologies, Inc., Case No. 3:13-cv-05889-YGR (N.D. Cal.);
`Netlist, Inc. v. Smart Modular Technologies, Inc., Case No. 2:13-cv-02613-
`TLN (E.D. Cal.); SanDisk Corp. v. Netlist, Inc., Case No. IPR2014-00982
`(PTAB); SanDisk Corp. v. Netlist, Inc., Case No. IPR2014-00994 (PTAB),
`Smart Modular Technologies, Inc. v. Netlist, Inc., Case No. IPR2014- 01371
`(PTAB); Smart Modular Technologies, Inc. v. Netlist, Inc., Case No.
`IPR2014-01370 (PTAB); SK hynix Inc., et al. v. Netlist, Inc., Case No.
`IPR2017-00649 (PTAB); and SK hynix Inc., et al. v. Netlist, Inc., Case No.
`
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`IPR2017-00587
`Patent 8,671,243 B2
`IPR2017-00561 (PTAB). Paper 4, 2–3. Patent Owner also indicates that
`related U.S. Patent Application Nos. 15/000,834, 14/489,281, and
`14/840,865 are pending. Id. at 4.
`C. The ’243 Patent
`The ’243 patent is entitled “Isolation Switching For Backup
`
`Memory,” and issued on March 11, 2014, from an application filed on May
`29, 2013. Ex. 1001, [22], [45], [54]. The ’243 patent claims priority to (1)
`U.S. Patent Application No. 13/536,173, filed on June 28, 2012 (now U.S.
`Patent No. 8,516,187); (2) U.S. Application No. 12/240,916, filed on
`September 29, 2008 (now U.S. Patent No. 8,301,833); (3) U.S. Application
`No. 12/131,873, filed on June 2, 2008; and (4) U.S. Provisional Application
`No. 60/941,586, filed on June 1, 2007. Id. at [60].
`
`The ’243 patent is directed to a memory module system that has a
`volatile memory subsystem, non-volatile memory subsystem, and controller.
`Ex. 1001, Abstract, 3:21–24. The memory module system may switch
`between two states of operation. Id. at 7:49–50. In the first state, a circuit
`couples the volatile memory subsystem to the host system while isolating the
`volatile memory subsystem from the non-volatile memory subsystem. Id.,
`Abstract, 7:50–54. In a second state, a circuit allows data to be
`communicated between the volatile and non-volatile memory subsystems by
`coupling the respective subsystems and isolating the volatile memory system
`from the host system. Id., Abstract, 7:54–58. The memory system uses the
`volatile memory subsystem under normal conditions, but provides back-up
`functions using the non-volatile memory subsystem. Id. at 3:24–27, 6:23–
`34, 7:49–62. In the event of a trigger condition, which may include a power
`failure or power reduction, the controller backs up the system by transferring
`data from a volatile memory system to a non-volatile memory system. Id. at
`
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`IPR2017-00587
`Patent 8,671,243 B2
`3:24–28. The configuration is directed to protecting the operation of the
`volatile memory in the two modes of operation while providing backup and
`restore capability in the event of a trigger condition. Id. at 3:32–36, 3:41–
`45, 8:17–30.
`
`Claim 1, reproduced below, is illustrative of the challenged claims of
`the ’243 patent.
`
`1. A memory system comprising:
`
`a volatile memory subsystem;
`a non-volatile memory subsystem;
`a controller coupled to the non-volatile memory subsystem; and
`a circuit coupled to the volatile memory subsystem, to the
`controller, and to a host system, wherein:
`in a first mode of operation, the circuit is operable to
`selectively isolate the controller from the volatile memory
`subsystem, and to selectively couple the volatile memory
`subsystem to the host system to allow data to be communicated
`between the volatile memory subsystem and the host system,
`and
`
`in a second mode of operation, the circuit is operable to
`selectively couple the controller to the volatile memory
`subsystem to allow data to be communicated between the
`volatile memory subsystem and the nonvolatile memory
`subsystem using the controller, and the circuit is operable to
`selectively isolate the volatile memory subsystem from the host
`system.
`
`Ex. 1001, 20:30–49.
`
`
`
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`
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`IPR2017-00587
`Patent 8,671,243 B2
`D. Asserted Grounds of Unpatentability
`Petitioners assert the following grounds of unpatentability:
`Ground Claim(s)
`Prior Art
`§ 1021
`1–3, 5–15, 17–30
`Shimada2
`§ 103
`4, 16
`Shimada and Oh3
`§ 103
`1, 3, 13, 15, 25
`Shimada and Bonella4
`§ 103
`6, 18
`Shimada
`§ 103
`9, 21, 28
`Shimada and Goodwin5
`§ 103
`10, 22, 29
`Shimada and Sasaki6
`§ 103
`11, 12, 23, 24, 30
`Shimada and Tsunoda7
`
`Pet. 3.
`
`II. ANALYSIS
`A. Claim Construction
`In an inter partes review, the Board interprets claim terms in an
`unexpired patent according to the broadest reasonable construction in light
`of the specification of the patent in which they appear. 37 C.F.R.
`§ 42.100(b); Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46
`(2016) (upholding the use of the broadest reasonable interpretation
`approach). Under that standard, and absent any special definitions, we give
`claim terms their ordinary and customary meaning, as they would be
`
`1 Petitioners assert that Shimada is prior art to the ’243 patent under
`§§ 102(a), (b), and (e). Pet. 13.
`2 U.S. Patent No. 6,693,840 B2 (issued February 17, 2004) (Ex. 1005).
`3 U.S. Patent No. 7,486,104 B2 (issued February 3, 2009) (Ex. 1012).
`4 U.S. Publication No. 2007/0136523 A1 (issued June 14, 2007) (Ex. 1009).
`5 U.S. Patent No. 4,658,204 (issued April 14, 1987) (Ex. 1015).
`6 U.S. Patent No. 6,721,212 B2 (issued April 13, 2004) (Ex. 1017).
`7 U.S. Publication No. 2003/0028733 Al (published February 6, 2003) (Ex.
`1019).
`
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`IPR2017-00587
`Patent 8,671,243 B2
`understood by one of ordinary skill in the art at the time of the invention.
`In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`“host system”
`Petitioners propose that the broadest reasonable construction of the
`term “host system” includes a “system external to the memory system that
`communicates with the memory system.” Pet. 7–8 (citing Ex. 1001, 4:56–
`57, 4:65–67, 5:2–5, 6:35–67; Ex. 1003 ¶ 69). In support, Petitioners argue
`that although the ’243 patent does not define the term “host system,” it
`describes its operations that communicate electrically and interact with the
`memory system, and the Specification states that host systems can include
`“blade servers, 1U servers, personal computers (PCs).” Id. (citing Ex. 1001,
`4:60–63; Ex. 1003 ¶ 67).
`Patent Owner asserts that the Petitioners’ proposed construction of
`“host system” is unreasonable because it focuses on communications,
`whereas the ’243 patent describes the “host system” as a “host computer
`system.” Prelim. Resp. 20 (citing Ex. 1001, 1:36–39, 4:17–18). Patent
`Owner argues that a person of ordinary skill in the art would understand the
`plain meaning of the term and that Petitioners’ construction sweeps in any
`external system that has the ability to communicate and is therefore not
`reasonable in view of the Specification. Id.
`Upon this record, it is not clear that the ordinary meaning of the term
`“host system” would be understood by one of skill without reference to the
`term’s use in the ’243 patent Specification. The Specification uses the terms
`“host computer system” and “computer system.” Additionally, it describes
`the host system as separate from the memory system. See Ex. 1001, 1:36–
`41. Consistent with these portions of the Specification, and to the extent
`necessary for this Decision, we adopt a modified version of Patent Owner’s
`
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`IPR2017-00587
`Patent 8,671,243 B2
`proposed construction of “host system” as a “host computer system external
`to the memory system.”
`“first mode” and “second mode”
`Petitioners propose that the broadest reasonable interpretation of “the
`first mode of operation,” recited in claim 1, is a mode “in which the circuit
`does not allow communication between the controller and the volatile
`memory subsystem while allowing communication between the volatile
`memory subsystem and the host system.” Pet. 8–9. Petitioners refer to the
`’243 patent prosecution history and Specification, alleging that the applicant
`argued that claim 1 requires both that the controller be isolated from, and
`that the host system be coupled to, the volatile memory subsystem. Id. at 8–
`11 (citing Ex. 1001, 3:36–41, 7:49–62, 9:40–45; Ex. 1002, 122–23; Ex. 1003
`¶¶ 70–75). In the Declaration of Ron Maltiel (“Maltiel Declaration”) (Ex.
`1003), Mr. Maltiel refers to the ’243 patent’s description of switches 170
`and 172 that can be “selectively switched” to switch the memory system
`between the first and second modes, and to “couple and decouple” the
`controller 62 to and from the volatile memory subsystem. Ex. 1003 ¶ 74
`(citing Ex. 1001, 6:38–49, Fig. 4A). For “the second mode of operation,”
`Petitioners propose that the “second mode of operation,” is one “in which
`the circuit does not allow communication between the volatile memory
`subsystem and the host system while allowing communication between the
`volatile memory subsystem and the controller.” Pet. 11.
`Patent Owner does not propose its own construction of the terms, but
`rather alleges that Petitioners impermissibly add and delete words of the
`claim limitation in their proposed constructions. Prelim. Resp. 21–24. More
`specifically, Patent Owner argues that Petitioners’ substituted verbiage is not
`equivalent to that in the claim, the proposed changes remove the function
`
`
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`IPR2017-00587
`Patent 8,671,243 B2
`claimed, and/or the proposed construction fails to consider all the words of
`the claim. Id.
`Claim 1 recites that in a first mode of operation, “the circuit is
`operable to selectively isolate the controller from the volatile memory
`subsystem, and to selectively couple the volatile memory subsystem to the
`host system to allow data to be communicated between the volatile memory
`subsystem and the host system.” The Specification states
`The memory system 10 of certain embodiments is configured to
`be operated in at least two states. The at least two states can
`comprise a first state in which the controller 62 and the non-
`volatile memory subsystem 40 are operatively decoupled (e.g.,
`isolated) from the volatile memory subsystem 30 by the at least
`one circuit 52 and a second state in which the volatile memory
`subsystem 30 is operatively coupled to the controller 62 to
`allow data to be communicated between the volatile memory
`subsystem 30 and the nonvolatile memory subsystem 40 via the
`controller 62. The memory system 10 may transition from the
`first state to the second state in response to a trigger condition,
`such as when the memory system 10 detects that there is a
`power interruption (e.g., power failure or reduction) or a system
`hang-up.
`Ex. 1001, 7:49–62 (emphases added).
`
`The Specification further states that “one or more isolation devices
`may isolate the non-volatile memory and the controller from the volatile
`memory when the volatile memory is interacting with the host system and
`may allow communication between the volatile memory and the non-volatile
`memory when the data of the volatile memory is being restored or backed-
`up.” Ex. 1001, 3:36–41 (emphases added). The Specification also states
`that “controller 62 transmits a signal to the at least one circuit 52 to
`operatively decouple the controller 62 from the volatile memory subsystem
`30, such that the memory system 10 reenters the first state.” Id. at 9:42–45.
`
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`IPR2017-00587
`Patent 8,671,243 B2
`
`At this juncture, and upon this record, we do not discern a need to
`recast the entire claim limitation with alternative wording, as the Petitioners
`advocate. Most words of the limitation have ordinary meanings that are
`consistent with their use in the Specification. As discussed above, however,
`the Specification describes the terms “couple” and “decouple” with the
`descriptive term “operatively,” and uses “isolate” as an example of
`“decouple.” Thus, for the purposes of this Decision, we construe “couple”
`to encompass “operatively couple,” and “isolate” to mean “operatively
`decouple.” Additionally, when coupled, the Specification supports that
`communication between the components is permitted, but also more broadly
`supports that interactions may occur. See Ex. 1001, 3:36–41, 7:49–62. As
`such, as to the “first mode” and “second mode,” we construe “couple” to
`mean “operatively couple to allow interaction,” and we construe “isolate” to
`mean “operatively decouple to not allow interaction.”
`“one or more switches”
`Petitioners argue that a person of ordinary skill in the art would find
`
`that the broadest reasonable construction of “one or more switches” is “an
`element that allows switching between two or more states.” Pet 11–12
`(citing Ex. 1003 ¶ 77 (additionally citing Ex. 1021, 505) (“switch n. 1. A
`circuit element that has two states: on and off. 2. A control device that
`allows the user to choose one of two or more possible states.”))).
`
`Patent Owner disputes Petitioners’ proposed construction, alleging
`that it is broader than the broadest reasonable interpretation. Prelim. Resp.
`25. As an example, Patent Owner alleges that a light bulb allows switching
`between two states, but it is not a switch. Id. Patent Owner’s position is that
`no construction is necessary as one of ordinary skill in the art would
`understand the meaning of the term in light of the specification. Id.
`
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`Patent 8,671,243 B2
`
`On this record, we are not persuaded by Patent Owner’s arguments.
`Although a light switch may be capable of switching states, we view the
`Petitioner’s proposed construction as requiring a circuit element that
`facilitates switching between two or more states, as opposed to a circuit
`element, like a light bulb, that merely can be switched—i.e., by another
`circuit element—between two or more states. Therefore, we adopt
`Petitioner’s proposed construction, with minor changes to further conform to
`the known definition in light of the Specification, that is, “one or more
`circuit element(s) that allow choosing one of two or more states.”
`Other Terms
`Although the parties propose claim constructions for another term, at
`this juncture of the proceeding, we determine that it is not necessary to
`provide an express interpretation of any other term of the claims. Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))
`(“[O]nly those terms need be construed that are in controversy, and only to
`the extent necessary to resolve the controversy.”).
`B. Alleged Anticipation of Claims 1–3, 5–15, and 17–30 by Shimada
` Petitioners contend that claims 1–3, 5–15, and 17–30 would have been
`anticipated by Shimada. Pet. 18–55. To support their contentions,
`Petitioners provide explanations as to how Shimada discloses each claim
`limitation. Id. Petitioners also rely upon the Maltiel Declaration to support
`their positions. Patent Owner counters that the Petitioners do not establish
`that Shimada discloses some claim limitations and also does not establish
`that some claim limitations are inherently present in Shimada. Prelim. Resp.
`26–49.
` At this stage of the proceedings, we are persuaded by Petitioners’
`explanations and evidence in support of the anticipation ground asserted
`
`
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`IPR2017-00587
`Patent 8,671,243 B2
`under Shimada against claims 1–3, 5–8, 13–15, 17–20, and 25–27, but we
`are not persuaded as to claims 9–12, 21–24, and 28–30. We begin our
`discussion with a brief summary of Shimada, and then address the evidence,
`analysis, and arguments presented by the parties.
`1. Shimada (Ex. 1005)
`Shimada generally discloses a semiconductor memory device that
`includes a volatile memory and non-volatile memory. Ex. 1005, 3:45–49.
`Figure 2 of Shimada is reproduced below.
`
`
`Figure 2 depicts a functional block diagram depicting an embodiment
`of a semiconductor memory device. Ex. 1005, 3:18–20.
`
`11
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`Patent 8,671,243 B2
`
`Shimada’s semiconductor memory device has control unit 102,
`volatile memory 103, non-volatile memory 104, selector 101, and power-
`supply unit 105. Ex. 1005, 3:47–48. Power-supply unit 105 directs
`externally supplied power and also accumulates power required by control
`unit 102 to save data from volatile memory 103 to non-volatile memory 104.
`Id. at 4:43–53. With the start of an external power supply, the control unit
`restores data of the non-volatile memory in the volatile memory, and when
`the external power supply has stopped, as detected by a voltage reduction in
`the main power source, the control unit saves data from the volatile memory
`to the non-volatile memory. Id. at 1:41–45, 3:64–4:6, 4:10–15.
`
`Control unit 102 controls operation of semiconductor memory device
`1 and receives a reference signal from outside of it, and performs data
`copying between volatile memory 103 and non-volatile memory 104 (i.e.
`save or restore), according to the reference signal. Ex. 1005, 3:54–59.
`Shimada’s selector 101 receives a signal sent from control unit 102 to switch
`between two different modes in which access to volatile memory 103 is
`allowed differently. Id. at 4:20–23. When select signal (H) is received,
`selector 101 allows access from outside the semiconductor memory device 1
`to the volatile memory 103; and when select signal (L) is received, the
`selector 101 allows the control unit 102 to access the volatile memory 103.
`Id. at 4:20–27.
`
`2. Analysis
`A claim is unpatentable under 35 U.S.C. § 102 if a prior art reference
`discloses each and every element of the claimed invention, either explicitly
`or inherently. Glaxo Inc. v. Novopharm Ltd., 52 F.3d 1043, 1047 (Fed.
`Cir.1995); see MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362, 1365
`(Fed.Cir.1999) (“To anticipate, a claim a prior art reference must disclose
`
`
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`Patent 8,671,243 B2
`every limitation of the claimed invention . . .;” any limitation not explicitly
`taught must be inherently taught and would be so understood by a person
`experienced in the field); In re Baxter Travenol Labs., 952 F.2d 388, 390
`(Fed.Cir.1991) (the dispositive question is “whether one skilled in the art
`would reasonably understand or infer” that a reference teaches or discloses
`all of the elements of the claimed invention).
`a. Claims 1 and 2
`Petitioners contend that Shimada discloses a volatile memory, non-
`volatile memory, and controller corresponding to the claim limitations. Pet.
`18–22. The Petition argues that selector 101 within semiconductor memory
`device 1, as depicted in Figure 2 of Shimada, is coupled to the volatile
`memory subsystem, controller, and host system, as claim 1 recites. Id. at
`22–24. Petitioners assert that Shimada discloses that the claimed first mode
`of operation is when selector circuit 101 receives input select signal (H), and
`in this mode selector 101 allows data to be communicated between volatile
`memory and the host system. Id. at 24 (citing Ex. 1003 ¶ 119; Ex. 1005 at
`4:6–9, 4:23–25, 4:28–33).
`The Petition further asserts that in the first mode, Shimada’s selector
`101 does not allow data communications between the host system and the
`remaining portions of the semiconductor memory device, including control
`unit 102. Pet. 24 (citing Ex. 1003 ¶ 120; Ex. 1005 at 3:47–50, 5:30–34,
`9:30–39). Mr. Maltiel refers to Shimada’s “semiconductor memory device”
`that includes the “control unit 102” and “non-volatile memory 104,” and in
`the first mode, selector 101 shuts out access of the host system to control
`unit 102 and non-volatile memory 104. Id. ¶ 120 (citing Ex. 1005, 3:47–50,
`9:30–39). Mr. Maltiel testifies that when the first mode is selected, a person
`of skill in the art would understand that “selector 101 has coupled the control
`
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`signal, address signal and data signal lines of the outside system to the
`volatile memory 103 rather than signal lines of the control unit.” Ex. 1003
`¶ 121. He further states that a skilled artisan would understand that the
`terms “selector” and “multiplexer” would be used interchangeably and cites
`to other prior art for support of that understanding. Id. ¶¶ 122–127. With
`this, Petitioners argue that Shimada discloses that in the first mode, “the
`circuit is operable to selectively isolate the controller from the volatile
`memory subsystem” as claimed. Pet. 24–25.
`
`Petitioners further argue that Shimada discloses the second mode of
`operation recited in claim 1 when the selector receives input select
`signal (L). Pet. 26. It is alleged that in this mode, that “the ‘selector 101’
`allows data to be communicated between the ‘volatile memory 103’ and the
`‘nonvolatile memory 104’ using the ‘control unit 102.’ Id. (citing Ex. 1003
`¶¶ 136-137; Ex. 1005, 3:55–62, 4:26–27, 4:34–41). It is further contended
`that when in this mode, “‘selector 101’ does not allow data to be
`communicated between the ‘volatile memory 103’ and the host system.” Id.
`(citing Ex. 1005, 3:64–4:1, 4:10–15, Fig. 3). Referring to Figure 3 of
`Shimada, Petitioners identify a first scenario where “selector 101” can
`receive an input select signal (L) after the reference signal has changed from
`L to H, then data is copied from non-volatile memory 104 to volatile
`memory 103, and “the control unit 102 . . . shuts out any access to the
`volatile memory 103 from outside, so that the control unit 102 may access
`the volatile memory 103.” Id. at 27 (citing Ex. 1003 ¶¶ 139, 140; Ex. 1005
`at 3:64–4:6, Fig. 3). In a second scenario, “selector 101” receives an input
`select signal (L) after the reference signal has changed from H to L, and data
`is copied from the volatile memory 103 to the non-volatile memory 104. Id.
`at 28 (citing Ex. 1003 ¶¶ 139, 141; Ex. 1005, 4:14–16, Fig. 3). Petitioners
`
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`aver that in this situation a person of ordinary skill understands that “the host
`system will not be able to communicate with the volatile memory 103
`because the selector 101 has coupled the volatile memory 103 to the control
`signal, address signal and data signal lines of the control unit 102, rather
`than to the signal lines of the outside system.” Id. (citing Ex. 1003 ¶ 142).
`
`Patent Owner contends that institution should be denied because
`Shimada does not teach that its selector 101 is operable to isolate/decouple
`its control unit 102 from the volatile memory 103 under the first mode of
`operation of claim 1. Prelim. Resp. 29. Patent Owner alleges that the
`portions of Shimada relied upon in the Petition merely state that the volatile
`memory portion may be allowed access from outside, but do not
`demonstrate that selector 101 is operable to selectively isolate the controller
`from the volatile memory subsystem. Id. at 29–30 (citing Pet. 14; Ex. 1005,
`3:47–50, 5:30–34, 9:30–39). It is further argued that the prior art cited by
`Petitioners for support does not disclose selective isolation and, additionally,
`a multiplexer does not act as, nor is it defined as, an isolation device. Id. at
`30–31 (citing Ex. 1006, 3:61–63; Ex. 1007, 6:63–65; Ex. 1008, 2; Ex. 2001,
`353).
`Patent Owner makes similar arguments for an alleged failure to
`
`demonstrate that Shimada discloses the second mode, contending the control
`unit 102 “merely shuts out any access to the volatile memory 103 from
`outside.” Prelim. Resp. 32. It is further alleged that if the control unit is
`operable to control access to volatile memory 103, then it is not isolated
`from the volatile memory subsystem. Id. at 32–33.
`
`At this juncture, we are persuaded that the Petition sufficiently
`demonstrates that Shimada’s selector 101 is operable to isolate/decouple its
`control unit 102 from the volatile memory 103 the first mode as claimed.
`
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`For the embodiment depicted in Figure 3, Shimada states that “control unit
`102 receives a reference signal from outside of the semiconductor memory
`device 1, and performs data copying between the volatile memory 103 and
`the non-volatile memory 104 (i.e. save or restore), according to the reference
`signal.” Ex. 1005, 3:55–58. Shimada also states that
`The selector 101 receives a select signal having been sent from
`the control unit 102 as in the above, and switches between two
`modes in which access to the volatile memory is allowed
`differently. That is, when receiving a select signal (H), the
`selector 101 allows access from outside the semi-conductor
`memory device 1 to the volatile memory 103; and when
`receiving a select signal (L), the selector 101 allows the control
`unit 102 to access the volatile memory 103.
`Ex. 1005, 4:20–27 (emphasis added).
`
`Shimada’s disclosures support that the control unit is used for data
`copying when volatile memory access is “allowed.” Shimada describes
`“switching” between the two modes of volatile memory access, that is, when
`the select signal is an “H,” access to the volatile memory is from outside,
`and when the select signal is an “S,” access to the volatile memory is from
`the control unit. Petitioners map the “first mode” of claim 1 to Shimada’s
`disclosure that, after a restoration of data in the volatile memory (upon
`power supply beginning), the control unit then “inputs a select signal (H), so
`as to permit access from outside to the volatile memory 103.” Ex. 1005,
`4:8–9. At this step in the process, copying to the volatile memory has been
`completed, and the mode is “switched” to allow “different” access to the
`volatile memory from the outside.8 Thus, there is support in Shimada for
`
`
`8 At this juncture, there is no dispute that the “outside access” of Shimada is
`equivalent of the “host system” of claim 1, and we see no issues arising in
`
`
`
`16
`
`

`

`IPR2017-00587
`Patent 8,671,243 B2
`Petitioners’ contention that one of ordinary skill in the art would understand
`that, during the mapped step, “selector 101 has coupled the control signal,
`address signal and data signal lines of the outside system to the volatile
`memory 103 rather than signal lines of the control unit.” See Pet. 24–25.
`The evidence is sufficient to support the contention that Shimada’s operation
`falls within the claim construction used herein for “isolate,” see supra
`Section II.A, that is, there is selective “operatively decoupling,” not allowing
`interaction of the control unit with the volatile memory subsystem as
`required under the claimed first mode limitation. For similar reasons, we
`also determine that the Petition sufficiently demonstrates that Shimada
`discloses the second mode limitation of claim 1.
`
`Claim 2, which depends from claim 1, additionally recites that the
`circuit “is operable to selectively isolate or couple the controller to the
`volatile memory subsystem,” and “is operable to selectively isolate or couple
`the volatile memory subsystem to the host system.” Ex. 1001, 20:50–54.
`Patent Owner makes similar arguments to those presented for claim 1
`(Prelim. Resp. 33–34), and for the reasons discussed above, we do not find
`the arguments persuasive.
`
`On this record, we are persuaded that Petitioners have provided
`sufficient evidence and explanations as to how the prior art discloses each
`claim limitation and have demonstrated a reasonable likelihood of prevailing
`on the assertion that claims 1 and 2 of the ’243 patent are anticipated by
`Shimada.
`
`
`light of the claim construction used herein, that is, a “host system” is a
`“computer system external to the memory system.” See supra Section II.A.
`
`
`
`17
`
`

`

`IPR2017-00587
`Patent 8,671,243 B2
`
`b. Claim 3
`Claim 3, which depends from claim 1, additionally recites that “the
`
`circuit includes one or more switches.” Ex. 1001, 20:55–56. Petitioners
`contend that Shimada discloses that its “circuit,” as claimed, “switches
`between two modes,” and, “[a]ccordingly, one skilled in the art would
`understand that the ‘selector 101’ necessarily includes ‘one or more
`switches.’” Pet. 29–30 (citing Ex. 1003 ¶¶ 149, 150; Ex. 1005, 4:20–23).
`
`Patent Owner alleges that Petitioners’ proposed construction for “one
`or more switches” improperly broadens the meaning of “switch” to mean
`any object that allows “switching.” Prelim. Resp. 35. Patent Owner argues
`that the only mention of “switch” in Shimada is in the verb form, and under
`Petitioners’ proposed construction, selector 101 is analogous to a light bulb,
`and control unit 103 is analogous to a switch. Id. As such, it is contended
`that the alleged “circuit” being switched does not include one or more
`switches. Id.
`
`At this juncture, we do not find Patent Owner’s arguments persuasive.
`As discussed above, we construe “one or more switches” to mean
`“element(s) that allow choosing one of two or more states.” The evidence
`supports Petitioners’ contention that selector 101 of Shimada falls within
`that meaning for the reasons discussed above.
`
`On this record, we are persuaded that Petitioners have provided
`sufficient evidence and explanations as to how the prior art discloses each
`claim limitation of claim 3 and have demonstrated a reasonable likelihood of
`prevailing on the assertion that claim 3 of the ’243 patent is anticipated by
`Shimada.
`
`
`
`18
`
`

`

`IPR2017-00587
`Patent 8,671,243 B2
`c. Claims 5–8, 13–15, 17–20, and 25–27
`Petitioners explain how Shimada discloses each and every limitation
`of claims 5–8, 13–15, 17–20, and 25–27. Pet. 30–39, 45–54. Patent Owner
`alleges that the arguments made in the Petition fail to overcome Shimada’s
`deficiencies for the same reasons discussed for other claims previously
`addressed herein. Prelim. Resp. 35–36, 42–48. We find these arguments
`unpersuasive for the reasons stated above.
`On this record, we are persuaded that Petitioners have provided
`sufficient evidence and explanations as to how the prior art discloses each
`claim limitation and have demonstrated a reasonable likelihood of prevailing
`on the assertion that claims 5–8, 13–15, 17–20, and 25–27 of the ’243 patent
`are anticipated by Shimada.
`d. Claims 9, 21, and 28
`Claim 9 depends from claim 1, and additionally recites “wherein the
`
`memory system transitions from the first mode to the second mode upon
`detecting that a trigger condition is likely to occur.” Ex. 1001, 21:20–23.
`Claims 21 and 28 recite similar limitations. See id. at 22:28–31, 23:6–10.
`
`Petitioners assert that the transition from the first to the second mode
`can be in response to trigger conditions (e.g., the power has stopped), which
`are detected by the “condition-change detect unit” that can detect the
`transition from the fully “power-on” state to the “power-off” state. Pet. 39
`(citing Ex. 1005, 2:28–39; Ex.

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