Trials@uspto.gov Paper No. 36
`Entered: July 18, 2018
`571-272-7822
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.
`Patent Owner.
`____________
`
`IPR2017-00668
`Patent 7,532,537 B2
`____________
`
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`McSHANE, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
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`I. INTRODUCTION
`A. Background
`
`SK hynix Inc., SK hynix America Inc., and SK hynix memory solutions Inc.
`(“Petitioner”) filed a Corrected Petition requesting inter partes review of claims
`18–23, 39–44, and 56–60 of U.S. Patent No. 7,532,537 B2 as amended by
`Reexamination Certificate No. 7,532,537 C1 (Ex. 1001, “the ’537 patent”),
`pursuant to 35 U.S.C. §§ 311–319. Paper 6 (“Pet.”). Netlist, Inc. (“Patent
`Owner”) did not file a Preliminary Response to the Petition.
`Pursuant to 35 U.S.C. § 314, we instituted an inter partes review as to
`claims 18–23, 39–44, and 56–60 of the ’537 patent on July 21, 2017. Paper 10
`(“Dec.” or “Institution Decision”), 7–23. The ground for institution was
`unpatentability under 35 U.S.C. § 103(a) as obvious over the combination of
`Amidi1 and Klein.2 Id. at 21–22.
`During the course of trial, Patent Owner filed a Patent Owner Response
`(Paper 15, “PO Resp.”), and Petitioner filed a Reply to the Patent Owner Response
`(Paper 19, “Pet. Reply”). Petitioner submitted the Declaration of Harold Stone,
`Ph.D. (Ex. 1003), and the Supplemental Declaration of Harold Stone, Ph.D. (Ex.
`1031). Patent Owner submitted the Declaration of Carl Sechen, Ph.D. (Ex. 2001).
`
`Petitioner filed a Motion to Exclude Evidence (Paper 22, “Pet. Mot. Ex.”),
`with Patent Owner filing an Opposition the Motion to Exclude (Paper 31, “Pet.
`Mot. Ex. Opp.”), and Petitioner filing a Reply thereto (Paper 33, “Pet. Mot. Ex.
`Reply”). Patent Owner filed a Motion for Observations (Paper 24, “Mot. Ob.”)
`and Petitioner filed a Response to Patent Owner’s Motion for Observations (Paper
`29, “Mot. Ob. Resp.). Patent Owner also filed a Submission on Propriety of
`
`1 U.S. Patent No. 8,250,295 B2 (issued August 21, 2012) (Ex. 1006).
`2 U.S. Publication No. 2001/0008006 A1 (published July 12, 2001) (Ex. 1007).
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`Petitioner’ Reply and Supplemental Stone Declaration due to alleged new
`arguments in Petitioner’s Reply and related expert declaration (Paper 26, “PO
`Obj.”), with Petitioner filing a Response (Paper 28, “PO Obj. Resp.”).
`
`We held a consolidated oral hearing on April 24, 2018, with the parties
`presenting arguments for this proceeding in combination with IPR2017-00667
`(“the 667 IPR”), as well for another proceeding involving the same parties. A
`transcript (Paper 35, “Tr.”), of the oral hearing has been entered into the record.
`See Tr. 3–45.
`We have jurisdiction to hear this inter partes review under 35 U.S.C. § 6,
`and this Final Written Decision is issued pursuant to 35 U.S.C. § 318(a) and 37
`C.F.R. § 42.73. For the reasons that follow, we determine that Petitioner has
`shown by a preponderance of the evidence that claims 18–23, 39–44, and 56–60 of
`the ’537 patent are unpatentable. We deny Petitioner’s Motion to Exclude.
`
`B. Related Proceedings
`Petitioner and Patent Owner indicate related matters are Netlist, Inc. v. Inphi
`Corp., Case No. 09-cv-6900-FMO (C.D. Cal.); Inter Partes Reexamination No.
`95/001,381 filed by Inphi Corporation on June 9, 2010, with associated Federal
`Circuit decision, Inphi v. Netlist, 805 F.3d 1350 (Fed. Circ. 2015); inter partes
`reexaminations of related U.S. Patent No. 7,619,912 (Control Nos. 95/001,339,
`95/000,578, 95/000,579), U.S. Patent No. 7,864,627 (Control No. 95/001,758), and
`U.S. Patent No. 7,636,274 (Control No. 95/001,337); inter partes reviews of U.S.
`Patent No. 7,881,150 (Case Nos. IPR2014-00882, IPR2014-01011, and IPR2015-
`01020), U.S. Patent No. 8,081,536 (Case Nos. IPR2014-00883 and IPR2014-
`01021), U.S. Patent No. 7,532,537 (Case No. IPR2017-00667), U.S. Patent No.
`8,756,364 (Case No. IPR2017-00549). See Pet. 1–2; Paper 5, 1–3.
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`Another inter partes review was instituted in the 667 IPR, which challenges
`the same ’537 patent, but different claims than those at issue here. See SK hynix
`Inc. v. Netlist, Inc., Case IPR2017-00667, Papers 6 and 10. A final written
`decision in that proceeding issues concurrently with this decision.
`Cases IPR2014-00882 (“882 IPR”), IPR2014-00883 (“883 IPR”), and
`IPR2014-01011 (“1011 IPR”) were directed to different patents, but the patents are
`related and have the same specification as the ’537 patent. Final written decisions
`were issued in these cases, the decisions were appealed to the Federal Circuit, and
`a decision issued in the appeal on July 25, 2017. See Netlist, Inc. v. Diablo Techs.,
`Inc., 701 Fed. App’x 1001 (Fed. Cir. 2017) (Ex. 2003) (“the Federal Circuit
`decision”). In its decision, the Federal Circuit construed some claim terms and
`remanded the cases back to the Patent Trial and Appeal Board for further
`proceedings. See Netlist, 701 Fed. App’x at 1004–7. Subsequently, the Patent
`Trial and Appeal Board issued decisions from the remand in the 882 IPR, the 883
`IPR, and the 1011 IPR, finding that under the Federal Circuit’s claim construction,
`the respective claims challenged were unpatentable. See Diablo Techs., Inc. v.
`Netlist, Inc., Case IPR2014-00882, (PTAB Mar. 29, 2018) (Paper 36); Diablo
`Techs., Inc. v. Netlist, Inc., Case IPR2014-00883, (PTAB Mar. 29, 2018) (Paper
`36); Diablo Techs., Inc. v. Netlist, Inc., Case IPR2014-01011, (PTAB Mar. 29,
`2018) (Paper 37).
`
`C. The ’537 Patent
`The ’537 patent is entitled “Memory Module With A Circuit Providing Load
`
`Isolation and Memory Domain Translation,” and issued on May 12, 2009, from an
`application filed on January 19, 2006. Ex. 1001, [22], [45], [54]. The ’537 patent
`claims priority to (1) U.S. Patent Application No. 11/173,175, filed on July 1, 2005
`(now U.S. Patent No. 7,289,386); (2) U.S. Application No. 11/075,395, filed on
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`March 7, 2005 (now U.S. Patent No. 7,286,436); (3) U.S. Provisional Application
`No. 60/645,087, filed on January 19, 2005; (4) U.S. Provisional Application No.
`60/588,244, filed on July 15, 2004; (5) U.S. Provisional Application No.
`60/550,668, filed on March 5, 2004; (6) U.S. Provisional Application No.
`60/575,595, filed on May 28, 2004; and (7) U.S. Provisional Application No.
`60/590,038, filed on July 21, 2004. Id. at [60], [63]. Inter Partes Reexamination
`No. 95/001,381 was conducted, resulting in claims 1, 7, 13, 16, 18, 21, 23, 24, 35,
`39, 41 and 44 being deemed patentable as amended, claims 2–6, 8–12, 14, 15, 17,
`19, 20, 22, 25–34, 36–38, 40, 42, and 43, which are dependent on amended claims,
`determined to be patentable, and with new claims 45–60 added which were
`determined to be patentable. See Ex. 1001, Inter Partes Reexamination Certificate
`(“Reexam. Cert.”) 1:16–22.3
`
`The ’537 patent is directed to a memory module system that includes
`memory devices and a circuit. Ex. 1001, Abstract, 2:62–63. The circuit can isolate
`one or more of the memory device loads from the computer system. Id. at
`Abstract, 2:67–3:1. The circuit has logic to translate between the system memory
`domain of the computer system and the physical memory domain of the memory
`module. Id. at Abstract, 3:2–4. The memory module has at least two memory
`devices arranged into ranks, and each memory device has a data signal line and
`data strobe line. Id. at 5:64–6:3, 6:27–47. Figure 4A of the ’537 patent is
`reproduced below.
`
`
`3 The Board issued an affirmance in the Reexamination (Ex. 1005, 1947–1970,
`2058–2063), of the Examiner’s Action Closing Prosecution (id. at 1494–1525),
`which determined that the reexamined amended and unamended claims were
`patentable. On appeal to the Federal Circuit, the Board’s determination was
`upheld. Inphi Corp. v Netlist, Inc., 805 F.3d 1350 (Fed. Cir. 2015). The
`Reexamination considered different prior art than the art at issue under this review.
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`Figure 4A above is a schematic illustration of example memory modules with a
`circuit and data signal lines. Ex. 1001, 3:48–53. Circuit 40 may selectively isolate
`or selectively electrically couple data signal lines 102a and 102b of memory ranks
`32a and 32b with common data signal line 112. Id. at 7:44–8:3, Fig. 4A. The
`circuit receives a set of input command and address signals from the memory
`controller and, in response, generates a set of output address and command signals.
`Id. at 16:10–18. Figure 9A is reproduced below.
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`Figure 9A above is a schematic illustration of an example memory module with
`four ranks of memory devices. Ex. 1001, 4:5–7. Memory module 10 is
`connectable to memory controller 20, and comprises printed circuit board 210,
`memory devices 30, and circuit 40. Id. at 15:7–17. Circuit 40 receives a set of
`input address and command signals from the computer system, and generates a set
`of output address and command signals in response to the set of input signals. Id.
`at 15:21–23. In some embodiments, circuit 40 receives a set of input address and
`command signals that corresponds to a number of memory devices for which the
`computer system is configured, and outputs a set of output address and command
`signals that correspond to a larger number of memory devices 30. Id. at 16:19–24.
`In certain embodiments, memory module 10 simulates a virtual memory module
`by operating as having a certain number of ranks of memory devices 30. Id. at
`16:31–40. In certain embodiments, “the load isolation provided by the circuit 40
`advantageously allows the memory module 10 to present a reduced load (e.g.,
`electrical load, such as capacitive load, inductive load, or impedance load) to the
`computer system by selectively switching between the two ranks of memory
`devices 30 to which it is coupled,” where “the memory module 10 operates as
`having a data path rank buffer which advantageously isolates the ranks of memory
`devices 30 of the memory module 10 from one another, from the ranks on other
`memory modules, and from the computer system.” Id. at 8:48–62.
`Claim 18, reproduced below, is illustrative of the challenged claims of the
`’537 patent, with emphasis on the limitation that is the subject of dispute between
`the parties.
`
`18. A memory module connectable to a computer system, the memory
`module comprising:
`a first memory device having a first data signal line and a first data
`strobe signal line;
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`a second memory device having a second data signal line and a
`second data strobe signal line;
`a common data signal line connectable to the computer system; and
`a device electrically coupled to the first data signal line, to the second
`data signal line, and to the common data signal line, the device selectively
`electrically coupling the first data signal line to the common data signal line
`and selectively electrically coupling the second data signal line to the
`common data signal line, the device comprising logic which translates
`between a system memory domain of the computer system and a physical
`memory domain of the memory module, wherein the system memory
`domain is compatible with a first number of chip selects, and the physical
`memory domain is compatible with a second number of chip selects equal to
`twice the first number of chip selects, wherein the first memory device and
`the second memory device are double-data rate (DDR) dynamic random
`access memory (DRAM) devices and the chip selects of the first and second
`number of chip selects are DDR chip selects that are not CAS, RAS, or bank
`address signals.
`Ex. 1001, Reexam. Cert. 2:12–38.
`
`II. ANALYSIS
`A. The Parties’ Post-Institution Arguments
` In our Decision on Institution, we concluded that the arguments and
`evidence advanced by Petitioner demonstrated a reasonable likelihood that claims
`18–23, 39–44, and 56–60 of the ’537 patent would have been unpatentable under
`35 U.S.C. § 103 over Amidi and Klein. Dec. 16–21. We now determine whether
`Petitioner has established by a preponderance of the evidence that claims 18–23,
`39–44, and 56–60 are unpatentable under 35 U.S.C. § 103(a) over Amidi and
`Klein. 35 U.S.C. § 316(e). We previously instructed Patent Owner that “any
`arguments for patentability not raised and fully briefed in the [Patent Owner
`Response] will be deemed waived.” Paper 11, 3; see also 37 C.F.R. § 42.23(a)
`(“Any material fact not specifically denied may be considered admitted.”); In re
`Nuvasive, Inc., 842 F.3d 1376, 1379–82 (Fed. Cir. 2016) (holding Patent Owner
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`waived an argument addressed in Preliminary Response by not raising the same
`argument in the Patent Owner Response). Additionally, the Board’s Trial Practice
`Guide states that the Patent Owner Response “should identify all the involved
`claims that are believed to be patentable and state the basis for that belief.” Office
`Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012).
`With a complete record before us, we note that we have reviewed arguments
`and evidence advanced by Petitioner to support its unpatentability contentions
`where Patent Owner chose not to address certain limitations in its Patent Owner
`Response. In this regard, the record now contains persuasive arguments and
`evidence presented by Petitioner regarding the manner in which the asserted prior
`art teaches corresponding limitations of claims 18–23, 39–44, and 56–60. Based
`on the preponderance of the evidence before us, we conclude that the art identified
`by Petitioner teaches or suggests all of the limitations of the reviewed claims.
`
`B. Claim Construction
`
`In an inter partes review, the Board interprets claim terms in an unexpired
`patent according to the broadest reasonable construction in light of the
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b). Under
`that standard, and absent any special definitions, we give claim terms their
`ordinary and customary meaning, as they would be understood by one of ordinary
`skill in the art at the time of the invention. In re Translogic Tech., Inc., 504 F.3d
`1249, 1257 (Fed. Cir. 2007).
`“selectively electrically coupling/couples”
`As discussed in the Institution Decision, the 882 IPR, 883 IPR, and 1011
`IPR were directed to different patents, but the patents are related and have the same
`specification as the ’537 patent. See Dec. 3, 8–10. Here, we adopt the Federal
`Circuit’s broadest reasonable construction from the 882, 883, and 1011 IPRs of the
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`term “selectively electrically coupling” as “coupling in response to a selection.”
`See Netlist, 701 Fed. App’x at 1004.
`“selectively isolating/isolates”
`The Federal Circuit decision in the 882, 883, and 1011 IPRs finds that “[t]he
`specification uses the terms ‘coupling’ and ‘isolating’ in a similar fashion,” and
`directs that the term be construed in view of the construction of the term
`“selectively electrically coupling.” Netlist, Inc., 701 Fed. App’x at 1005.
`Accordingly, we construe the term “selectively isolating” as “isolating in response
`to a selection,” which conforms with the Federal Circuit’s direction, and also is
`consistent with the Patent Owner’s proposed construction for the term. PO Resp.
`4.
`
`Other Terms
`
`The parties do not propose constructions for any additional claim terms. We
`determine that it is not necessary to provide an express interpretation of any other
`term of the claims because it is not necessary to resolve any issues or disputes.
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))
`(“[O]nly those terms need be construed that are in controversy, and only to the
`extent necessary to resolve the controversy.”).
`
`C.
`
`Level of Ordinary Skill in the Art
`
`Petitioner contends that a person of ordinary skill in the art at the time of the
`
`’537 invention would be “someone with an advanced degree in electrical or
`computer engineering and two years working in the field, or a bachelor’s degree in
`such engineering disciplines and at least three years working the field.” Pet. 3
`(citing Ex. 1003 ¶ 48). Dr. Stone further testifies that a person of ordinary skill in
`the art
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`would have been knowledgeable about the design and operation of
`computer memories, most particular DRAM and SDRAM devices that
`were compliant with various standards of the day, and how they
`interact with other components of a computer system, such as memory
`controllers. He or she would also have been familiar with the
`structure and operation of circuitry used to access and control
`computer memories, including sophisticated circuits such as ASICs
`and CPLDs and more low level circuits such as tri-state buffers, flip
`flops and registers.
`Ex. 1003 ¶ 48.
`
`Patent Owner’s expert offers a proposed level of qualification to include:
`an undergraduate degree in electrical engineering or computer
`engineering, at least two years of professional experience in the
`design of memory systems, familiarity with the latest JEDEC standard
`specifications for memory devices and modules, and familiarity with
`the latest DRAM memory devices widely available in the market.
`Ex. 2001 ¶ 14.
`
`Patent Owner’s expert agrees with Petitioner’s proposed level of skill. Ex.
`2001 ¶ 18.
`We adopt and apply this assessment of the level of ordinary skill in the art
`articulated by Petitioner to our obviousness analysis in this proceeding. In
`addition, we note that the art of record in this proceeding—namely, Amidi and
`Klein—is indicative of the level of ordinary skill in the art. See Okajima v.
`Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001).
`
`D.
`
`Asserted Obviousness of Claims 18–23, 39–44, and 56–60
`by Amidi and Klein
`In support of this asserted ground of unpatentability, Petitioner explains how
`
`the combination of Amidi and Klein would have rendered obvious claims 18–23,
`39–44, and 56–60. Pet. 14–48. In its Response, Patent Owner contends that the
`prior art references fail to teach the “selectively electrically coupling” limitation of
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`claim 18, and that impermissible hindsight was used in the obviousness challenge
`and one of ordinary skill in the art would not have been motivated to combine
`Amidi and Klein nor would the combination have a reasonable likelihood of
`success. See PO Resp. 16–47. Patent Owner directs all its arguments to claim 18.
`Id.
`
`Having considered all of the arguments and evidence, we find that Petitioner
`has demonstrated by a preponderance of the evidence that the combination of
`Amidi and Klein would have rendered obvious claims 18–23, 39–44, and 56–60
`for the reasons discussed below.
`We begin our analysis with a summaries of Amidi and Klein, and then
`address the arguments and evidence presented by the parties.
`Amidi (Ex. 1006)
`1.
`Amidi discloses a memory interface system with a processor, a memory
`
`controller, and a memory module. Ex.1006, 1:21–23. According to Amidi, a
`memory interface system in the prior art is shown in Figure 1, reproduced below.
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`Figure 1 is a schematic of a standard prior art memory interface system with
`memory module 106 with controller address bus 114, controller control signal bus
`116, and controller data bus 118. Ex. 1006, 1:21–29, 3:5–6, Fig. 1. As illustrated
`in Figure 1, memory module 106 communicates with memory controller 104 via
`busses 114, 116, 118. Id. at Fig. 1. Amidi discloses that each stack of double data
`rate (DDR) memory devices has a data signal line and a data strobe line (DQS), as
`shown in Figure 2 below. See id. at 4:24–30.
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`Figure 2 is a diagram illustrating a stacked DDR device. Ex. 1006, 3:7–9. Amidi
`discloses a four-rank memory module with logic that allows the four rank memory
`module “to communicate with a memory socket having only two chip select
`signals routed.” Id. at 4:61–64. Figure 3 of Amidi, which is reproduced in an
`annotated form by Petitioner below, illustrates Amidi’s four-rank memory module.
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`Figure 3, in annotated form above, depicts stacked 8-bit memory devices on the
`front and back side of memory module 300. Ex. 1006, 4:33–35. Each rank
`includes nine memory devices (e.g., U1 to U9 for rank 0, U19 to U27 for rank 3,
`etc.). Id. at 4:36–39. The memory devices in each rank of memory devices are
`coupled to a chip select signal corresponding to that rank. Id. at 4:43–46. Figure
`4A of Amidi is reproduced below.
`
`
`Figure 4A is a diagram schematically illustrating the front side of transparent 72-
`bit registered double data rate (DDR) module 400 in an embodiment of the
`invention. Ex. 1006 at 3:13–15, 4:65–67. Amidi’s memory module includes
`complex programmable logic device (CPLD) 410 that
`emulates a two rank memory module on the four rank memory
`module 400. CPLD 410 allows a system having a memory socket
`with only two chip select signals routed to interface with a four rank
`memory module where typically a two rank memory module couples
`with the memory socket. The CPLD 410 determines which rank from
`the four ranks to activate based upon the address and command
`signals from a memory controller coupled to the memory module 410.
`Id. at 5:30–39.
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`Register 408 and phase-lock loop device (PLL) 412 provide one or more
`
`input control signals to the rank of memory devices activated by the generated chip
`select signals and thereby may control loading. Id. at 5:15–26.
`2. Klein (Ex. 1007)
`Klein discloses a method for bus capacitance reduction. Ex. 1007, Abstract.
`
`According to Klein, data bus capacitance is reduced by decoupling unaccessed
`memory circuits from a data bus during data transfers to or from other memory
`circuits. Id. In one embodiment, memory controller 22 connects to circuitry 26 for
`interfacing with one or more memory circuits 28, as shown in Figure 3, reproduced
`below. Id. ¶ 28, Fig. 3.
`
`
`Figure 3 illustrates that the data bus between memory controller 22 and memory
`elements 28 may comprise several branches 30a, 30b, one for each separate
`memory elements 28. Id. Each branch may include a switch, e.g., switch 32a or
`switch 22b, which may be used to selectively isolate a portion of the data bus, e.g.,
`30c or 30d, from memory controller 22. Id. Klein states that memory circuit 28
`may be a conventional DRAM integrated circuit. Id. ¶ 29. The embodiment
`shown in Figure 3 may reduce the parasitic capacitance that the memory controller
`needs to charge and discharge during data transfers because a portion of the data
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`bus and the stray capacitance of unaccessed memory circuits are removed. Id.
`¶ 28.
`
`
`Another embodiment in Klein is illustrated in Figure 6, reproduced below.
`
`
`
`As shown in Figure 6, a circuit is provided on memory module 76 that includes
`transfer gates 64 and state decoder 78. Ex. 1007 ¶¶ 35, 39. Klein discloses that
`state decoder 78 includes inverter 80 (id. ¶ 36), and that “state decoder 78 could
`comprise a state machine 84 made with a programmable gate array for example”
`(id. ¶ 37). Klein further discloses control logic circuitry, data buffer registers, and
`a bus switch are incorporated into memory modules. Id. ¶¶ 29, 39, 40, Figs. 3, 10.
`The integrated circuit and a transfer gate output are connected to data buffer
`registers. Id. ¶ 40, Fig. 10.
`
`3. Analysis
`To prevail on its challenges to the patentability of the claims, a petitioner
`
`must establish facts supporting its challenge by a preponderance of the evidence.
`35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). “In an [inter partes review], the
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`petitioner has the burden from the onset to show with particularity why the patent
`it challenges is unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356,
`1363 (Fed Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`petitions to identify “with particularity . . . the evidence that supports the grounds
`for the challenge to each claim”)). This burden of persuasion never shifts to the
`patent owner. See Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d
`1375, 1378–79 (Fed. Cir. 2015) (discussing the burdens of persuasion and
`production in inter partes review).
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was made to
`a person having ordinary skill in the art to which said subject matter pertains. KSR
`Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of obviousness is
`resolved on the basis of underlying factual determinations including: (1) the scope
`and content of the prior art; (2) any differences between the claimed subject matter
`and the prior art; (3) the level of ordinary skill in the art; and (4) when in evidence,
`objective evidence of nonobviousness.4 Graham v. John Deere Co., 383 U.S. 1,
`17–18 (1966). For a determination of obviousness, there must be a showing that “a
`skilled artisan would have been motivated to combine the teachings of the prior art
`references to achieve the claimed invention, and that the skilled artisan would have
`had a reasonable expectation of success in doing so.” Procter & Gamble Co. v.
`Teva Pharms. USA, Inc., 566 F.3d 989, 994 (Fed. Cir. 2009) (citing Pfizer, Inc. v.
`Apotex, Inc., 480 F.3d 1348, 1361 (Fed. Cir. 2007)).
`
`
`4 Patent Owner does not present arguments or evidence of objective indicia of
`nonobviousness in its Patent Owner Response.
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`IPR2017-00668
`Patent 7,532,537 B2
`
`
`a. Petitioner’s Assertions
`Petitioner contends that Amidi and Klein teach all the elements of
`
`independent claim 18. Pet. 14–31. Claim 18 recites “[a] memory module
`connectable to a computer system, the memory module comprising . . .” Petitioner
`relies upon Amidi’s disclosure of “a four rank memory module emulating a two
`rank module, in which the third memory rank is stacked on the first memory rank
`and a fourth memory rank is stacked on a second memory rank.” Id. at 14–15
`(citing Ex. 1006, Abstract, Fig. 4A). Claim 18 further recites “a first memory
`device having a first data signal line and a first data strobe signal line,” and
`Petitioner relies upon Amidi’s disclosure in Figure 2 that show stacked DDR
`devices receiving a variety of signals that include data signals and a data strobe
`line and signal (DQS). Id. at 15–16 (citing Ex. 1006, 4:24–30, Fig 2).
`
`Petitioner relies upon Amidi in combination with Klein for the teachings of a
`second memory device having a second data signal line and a second data strobe
`signal line. Pet. 17–21. For the teachings of a second memory device, Klein
`discloses a bus switch that is electrically coupled to output data buses as shown in
`Figure 4, and this switch circuity can be mounted on the motherboard, the memory
`module, or the memory IC. Id. at 17–18 (citing 1007 ¶¶ 29, 30, Fig. 4). Petitioner
`relies upon Amidi for the teaching of the claimed common data signal line. Id. at
`22–23 (citing Ex. 1006, 4:20–30; Ex. 1003 ¶ 282).
`Petitioner asserts that “[i]n order to reduce the capacitive load on the data
`bus lines, one of ordinary skill in the art would be motivated to combine Amidi’s
`teaching of emulating two ranks of memory devices with four ranks of less dense
`memory devices with Klein’s teaching of reducing load of memory devices
`coupled on a memory bus.” Id. at 18–19 (citing Ex. 1003 ¶¶ 136–154, 278).
`Further, “[t]he skilled artisan would achieve a reduction in capacitance that would
`
`
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`IPR2017-00668
`Patent 7,532,537 B2
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`improve the speed of the memory system by reducing the time required to charge
`the parasitic capacitance.” Id. at 19 (citing Ex. 1007 ¶ 7). Petitioner further asserts
`that one of skill in the art would have been motivated to combine the switches of
`Klein with the circuitry of Amidi because both references are analogous art to the
`’537 patent and are pertinent to the particular problem in the patent. Id. at 19–20
`(citing Ex. 1001, 1:29– 32; Ex. 1006, 1:7-10; Ex. 1007 ¶ 10). Petitioner also
`asserts that one of skill in the art would have been motivated to use Klein’s
`circuitry because Klein is directed to “memory module configurations that increase
`the speed at which memory accesses can be performed by isolating memory
`devices from the full capacitive loading effects of the system memory data bus,”
`and it would be desirable to employ those techniques to avoid having parasitic
`capacitance slow the speed of transfer. Id. at 20 (citing Ex. 1007 ¶¶ 7, 10; Ex.
`1003 ¶145). Further, “the flexibility of the circuitry disclosed by Klein allows one
`of skill in the art to isolate a variety of memory elements or memory segments as
`needed.” Id. at 21. Petitioner avers that the combination of Amidi and Klein is an
`arrangement of old elements with each performing the same function it had been
`known to perform. Id. at 22.
`Claim 18 further recites “a device electrically coupled to the first data signal
`line, to the second data signal line, and to the common data signal line, the device
`selectively electrically coupling the first data signal line to the common data signal
`line and selectively electrically coupling the second data signal line to the common
`data signal line,” and we refer to this as the “selectively electrically coupling
`limitation.” For the teaching of this limitation, Petitioner relies on Amidi’s
`disclosure of a CPLD that “select[s] an active rank of the four ranks and []
`inactivate[s] the data paths to the other three ranks of memory devices from the
`computer system.” Pet. 23–25 (citing Ex. 1006, 9:11–38, Fig. 8; Ex. 1003 ¶¶ 285–
`
`
`
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`IPR2017-00668
`Patent 7,532,537 B2
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`287). In the alternative, Petitioner argues Klein’s disclosure of transfer gate
`switches for decoupling of memory elements from other data bus elements teaches
`the coupling limitation. Id. at 26–27. More specifically, Petitioner relies on
`Klein’s teachings of state decoder 78 and transfer gates 64, depicted in Figure 6, as
`the circuitry that selectively allows for data transfers between the system memory
`data bus and a memory element and selectively isolate the load of a memory
`element from the computer system. Id. at 27 (citing Ex. 1007 ¶¶ 29, 33, Figs, 2, 5,
`6; Ex. 1003 ¶¶ 136–154, 289). Dr. Stone refers to inverter 80 of Figure 7, state
`decoder 78 of Figure 8, which includes state machine 84 with a programmable gate
`array that determines the status of memory accesses and “appropriately assert[s]
`the gate control signal 72 when data transfer is to occur,” as well as decode circuit
`86 of Figure 9 of Klein, as reproduced below. Ex. 1003 ¶¶ 140–143.
`
`
`Figures 7, 8, and 9, above, are discussed in combination as teaching the control
`required of the claimed circuit. Id. Dr. Stone refers to Klein embodiments of state
`decoders and testifies
`It also would have been obvious to one of ordinary skill in the art that
`FIG. 8 . . . discloses a circuit that triggers an enable signal based on
`when to enable a transfer, whereas FIG. 9 discloses a circuit that
`triggers an enable signal based on what to enable. One of skill in the
`art would know that it is possible to combine FIGS. 8 and 9, to control
`both what to enable and when to enable it simply by enabling the
`decoder circuit of FIG. 9 by the output of the state machine 84