Trials@uspto.gov
`571-272-7822
`
`
`Paper 25
`Entered: July 5, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00692
`Patent 8,874,831 B2
`____________
`
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`CLEMENTS, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`571-272-7822
`
`
`Paper 25
`Entered: July 5, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00692
`Patent 8,874,831 B2
`____________
`
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`CLEMENTS, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`IPR2017-00692
`Patent 8,874,831 B2
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`INTRODUCTION
`I.
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314, SK
`hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`(“Petitioner”) challenges claims 1–15 (“the challenged claims”) of U.S.
`Patent No. 8,874,831 B2 (Ex. 1001, “the ’831 patent”), owned by Netlist,
`Inc. (“Patent Owner”). We have jurisdiction under 35 U.S.C. § 6. This
`Final Written Decision is entered pursuant to 35 U.S.C. § 318(a) and 37
`C.F.R. § 42.73. For the reasons discussed below, Petitioner has shown by a
`preponderance of the evidence that the challenged claims are unpatentable.
`Petitioner’s Motion to Exclude is dismissed.
`
`A. Procedural History
`Petitioner filed a Petition requesting an inter partes review of claims
`1–15 of the ’831 patent. Paper 1 (“Pet.”). Patent Owner filed a Preliminary
`Response. Paper 6. On July 21, 2017, we instituted inter partes review of
`(1) claims 1–14 of the ’831 patent as unpatentable under 35 U.S.C. § 1021 as
`anticipated by Best;2 (2) claims 1–14 under 35 U.S.C. § 103(a) as obvious
`over Best; (3) claims 1–14 under 35 U.S.C. § 103(a) as obvious over Best
`and Roy;3 and (4) claim 15 over Bowie under 35 U.S.C. § 103(a) as obvious
`
`
`1 The Leahy-Smith America Invents Act, Pub. L. No. 112–29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the ’831
`patent has an effective filing date before the effective date of the applicable
`AIA amendments, we refer to the pre-AIA versions of 35 U.S.C. §§ 102 and
`103.
`2 U.S. Patent Publication No. 2010/0110748 A1 (Ex. 1006, “Best”).
`3 U.S. Patent No. 6,065,092 (Ex. 1008, “Roy”).
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`2
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`over Best, Mills,4,5 and Bonella,6 with or without Roy. Paper 7 (“Inst.
`Dec.”), 28.
`Thereafter, Patent Owner filed a Patent Owner Response (Paper 12,
`“PO Resp.”), to which Petitioner filed a Reply (Paper 15, “Reply”).
`Petitioner filed a Motion to Exclude (Paper 17). Patent Owner filed an
`Opposition (Paper 20) to which Petitioner filed a Reply (Paper 22).
`On April 24, 2018, we held a hearing and a transcript of the hearing is
`included in the record. Paper 24 (“Tr.”).
`On May 3, 2018, following the Supreme Court’s decision in SAS Inst.,
`Inv. v. Iancu, 138 S. Ct. 1348 (2018), we issued an Order (Paper 23)
`modifying our Institution Decision to include review of all challenged
`claims and all grounds presented in the Petition, including these grounds on
`which we had previously not instituted (Pet. 3, 28):
`References
`Basis
`Claim(s)
`challenged
`2 and 8
`
`Best and Tsunoda, with or
`without Roy
`Best and Roohparvar,7 with or
`without Roy
`Best, Mills,8 Bonella, and
`Ashmore, with or without Roy
`
`4 U.S. Patent No. 6,026,465 (Ex. 1010, “Mills”).
`5 Although Petitioner does not include Mills (Ex. 1010) explicitly in its
`ground (Pet. 3), we include it because Petitioner’s analysis relies upon it (id.
`at 61–64) for teaching part of a limitation.
`6 U.S. Patent Publication No. 2007/0136523 A1 (Ex. 1013, “Bonella”).
`7 U.S. Patent Publication No. 2005/0273548 A1 (Ex. 1019, “Roohparvar”).
`8 Although Petitioner does not include Mills (Ex. 1010) explicitly in its
`
`§ 103
`
`§ 103
`
`5 and 12–14
`
`§ 103
`
`15
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`3
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`In our order, we also stated that, “If, after conferring, the parties wish to
`submit further briefing, the parties must, within one week of the date of this
`Order, request a conference call with the panel to seek authorization for such
`briefing.” Paper 23, 2. Neither party requested a conference call with the
`panel.
`
`B. Related Proceedings
`The parties indicate that the ’831 patent is the subject of several
`district court cases and related inter partes reviews. Pet. 2; Paper 4, 3.
`
`C. The ’831 patent (Ex. 1001)
`The ’831 patent, titled “Flash-Dram Hybrid Memory Module,” issued
`October 28, 2014, from U.S. Patent Application No. 13/559,476. Ex. 1001
`at [54], [45], [21]. The ’831 patent generally relates to a memory module
`with a non-volatile memory, a volatile memory, and a data manager through
`which the volatile memory and non-volatile memory may exchange data,
`and a controller to receive read/write commands from a memory controller
`hub (“MCH”) and transfer data between any two or more of the MCH,
`volatile memory, and non-volatile memory. Id. at Abstract.
`
`
`ground (Pet. 3), we include it because Petitioner’s analysis relies upon it (id.
`at 61–64) for teaching part of a limitation.
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`Figure 4A is reproduced below.
`
`
`Figure 4A is a block diagram of a Flash-DRAM hybrid dynamic random
`access memory dual in-line memory module (DIMM). In this embodiment,
`volatile memory subsystem 406 (e.g. DRAM) is used as a data buffer such
`that data from Flash memory 402 is transferred to DRAM 406 at the Flash
`access speed, and buffered or collected into DRAM 406, which then
`transfers the buffered data to the MCH based on the access time of DRAM.
`Id. at 9:15–21. Similarly, when the MCH transfers data to DRAM 406,
`controller 404 manages the data transfer from DRAM 406 to Flash 402. Id.
`at 9:21–23.
`Figure 5A is reproduced below.
`
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`Figure 5A is a block diagram of memory module 500 in accordance with
`certain embodiments. Ex. 1001, 7:7–8. As shown in Figure 5, memory
`module 500 includes two on-module intermediary components: controller
`(CDC) 502 and data manager (DMgr) 504. Id. at 10:35–46. These
`components “manage the interface between a non-volatile memory
`subsystem such as a Flash 506, a volatile memory subsystem such as a
`DRAM 508, and a host system represented by MCH 510.” Id. at 10:49–53.
`“In certain embodiments, CDC 502 controls the read/write access to/from
`Flash memory 506 from/to DRAM memory 508, and to/from DRAM
`memory from/to MCH 510.” Id. at 10:54–56. “In certain embodiments and
`in response to communication from CDC 502, DMgr 504 provides a variety
`of functions to control data flow rate, data transfer size, data buffer size, data
`error monitoring or data error correction.” Id. at 11:18–21.
`Figure 6 is reproduced below.
`
`
`Figure 6 is a block diagram showing some details of data manager 504. Ex.
`1001, 7:11–12. “In certain embodiments, DMgr 504 also functions as a bi-
`directional data transfer fabric.” Id. at 12:1–3. “For example, DMgr 504
`may have more than 2 sets of data ports facing the Flash 506 and the DRAM
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`508.” Id. at 12:3–5. “Multiplexers 611 and 612 provide controllable data
`paths from any one of the DRAMs 508(1) and 508(2) (DRAM-A and
`DRAM-B) to any one of the MCH 510 and the Flash 506.” Id. at 12:5–8.
`“Similarly multiplexers 621 and 622 provide controllable data paths from
`any one of the MCH and the Flash memory to any one of the DRAMs
`508(1) and 508(2) (DRAM-A and DRAM-B).” Id. at 12:8–11.
`
`D. Illustrative Claim
`Of the challenged claims, claims 1 and 7 are independent, claims 2–6
`depend, directly or indirectly, from claim 1, and claims 8–15 depend,
`directly or indirectly, from claim 7. Independent claim 1 is illustrative of the
`challenged claims and is reproduced below:
`1.
`A memory module couplable to a memory controller of a
`host system, comprising:
`a non-volatile memory subsystem;
`a data manager coupled to the non-volatile memory subsystem;
`a volatile memory subsystem coupled to the data manager and
`operable to exchange data with the non-volatile memory
`subsystem by way of the data manager; and
`a controller operable to receive commands from the memory
`controller and to direct (i) operation of the non-volatile memory
`subsystem, (ii) operation of the volatile memory subsystem, and
`(iii) transfer of data between any two or more of the memory
`controller, the volatile memory subsystem, and the non-volatile
`memory subsystem based on at least one received command
`from the memory controller, wherein:
`at least one of the volatile and non-volatile memory subsystems
`comprises one or more memory segments, each memory segment
`comprising at least one memory circuit, memory device, or
`memory die, and
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`the data manager is configured as a bi-directional data transfer
`fabric having two or more sets of data ports, a first set of data
`ports of the two or more sets of data ports is coupled to the
`volatile memory subsystem, a second set of data ports of the two
`or more sets of data ports is coupled to the non-volatile memory
`subsystem, the two or more sets of data ports being operable by
`the data manager to transfer data to or from one or more memory
`segments of the volatile or non-volatile memory subsystems, the
`data manager further including a data buffer for buffering data
`delivered to or from the non-volatile memory subsystem, and a
`data format module configured to format data to be transferred
`between any two or more of the memory controller, the volatile
`memory subsystem, and the non-volatile memory subsystem
`based on control information received from the controller.
`Ex. 1001, 17:44–18:13.
`
`E. Instituted Grounds of Unpatentability
`Petitioner asserted that the challenged claims are unpatentable based
`on the following grounds (Pet. 3), and trial has been instituted on these
`grounds (see supra Section I.A):
`Reference(s)
`Best
`Best and Roy
`Best and Tsunoda, with or without Roy
`Best and Roohparvar, with or without
`Roy
`Best, Mills,9 and Bonella, with or without
`Roy
`Best, Mills,10 Bonella, and Ashmore, with
`or without Roy
`
`
`
`9 Petitioner does not include Mills (Ex. 1010) explicitly (Pet. 3), but the
`analysis relies upon it (id. at 61–64) for teaching part of a limitation.
`10 See n.9, above.
`
`8
`
`Basis Claim(s) challenged
`§ 102 1–14
`§ 103 1–14
`§ 103 2 and 8
`§ 103 5 and 12–14
`
`§ 103 15
`
`§ 103 15
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`II. ANALYSIS
`A. Claim Construction
`We interpret claims of an unexpired patent using the broadest
`reasonable construction in light of the specification of the patent in which
`they appear. See 37 C.F.R. § 42.100(b); see Cuozzo Speed Techs., LLC v.
`Lee, 136 S. Ct. 2131, 2142–46 (2016). Under the broadest reasonable
`construction standard, claim terms are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in the
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007). Any special definition for a claim term must be set
`forth in the specification with reasonable clarity, deliberateness, and
`precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). We must be
`careful not to read a particular embodiment appearing in the written
`description into the claim if the claim language is broader than the
`embodiment. See In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993).
`Only terms that are in controversy need to be construed, and then only to the
`extent necessary to resolve the controversy. Vivid Techs., Inc. v. Am. Sci. &
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`1. “memory module”
`Each independent claim recites a “memory module.” Petitioner did
`not propose a construction for “memory module” in the Petition. Patent
`Owner argued, in its Preliminary Response, that “memory module” should
`be construed to mean “a carrier that contains one or more chips.” Prelim.
`Resp. 21. In our Decision on Institution, we construed “memory module” to
`mean “a carrier that contains one or more memory chips,” where “carrier”
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`encompasses an integrated circuit package. Inst. Dec. 9–10. We observed
`that
`
`The ’831 patent does not define a “memory module.” The ’831
`patent depicts a memory module 500 in Figures 5A and 5B, and
`describes how “[i]n certain embodiments, memory module 500
`is a Flash-DRAM hybrid memory module that has the DIMM
`(dual-inline memory module) form factor” (Ex. 1001, 10:28–31),
`but the ’831 patent also expressly contemplates other form
`factors (see, e.g., id. at 10:32–34 (“it is to be understood that in
`both structure and operation [memory module 500] may be
`different from the FDHDIMM discussed above and described
`with reference to FIGS. 4A and 4B”), 10:46–49 (“While the
`DIMM form factor will predominate the discussion herein, it
`should be understood that this is for illustrative purposes only
`and memory systems using other form factors are contemplated
`as well.”).
`
`Id.
`
`In its Patent Owner Response, Patent Owner argues that “memory
`module” should be construed to mean “one or more memory segments on a
`printed circuit board” (“PCB”). PO Resp. 14–34. According to Patent
`Owner, “[e]very embodiment of a ‘memory module’ disclosed by the ’831
`patent comprises a PCB” and its proposed construction “parallels how the
`term ‘memory module’ is used by those in the industry and standards
`bodies.” Id. at 15. Specifically, Patent Owner annotates Figure 5A, arguing
`that it shows “a PCB (yellow)”:
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`PO Resp. 16; see also id. at 20–23 (“Because the ’831 specification only
`discloses embodiments including memory segments on a PCB, the claimed
`‘memory module’ should be construed to cover such embodiments.”).
`These arguments are not persuasive because the ’831 patent does not
`describe 500, or any other embodiment, as a PCB. Instead, the ’831 patent
`refers to 500 only as a “module.” Ex. 1001, 10:14–15.
`Patent Owner also argues that the ’831 patent “repeatedly and
`consistently describes ‘memory modules’ as having a Dual In-Line Memory
`Module (‘DIMM’) form factor.” PO Resp. 17. As Petitioner points out,
`however, claims are not limited to the embodiments described in the
`Specification. Pet. Reply 3–4 (citing ACUMED LLC v. Stryker Corp., 483
`F.3d 800, 805 (Fed. Cir. 2007)). Moreover, as we noted above, the ’831
`patent expressly contemplates other form factors for its “module” and,
`therefore, does not limit “module” to a DIMM form factor. See, e.g., Ex.
`1001, 10:32–49. The ’831 patent states, for example
`These on-module intermediary components may be physically
`separate components, circuits, or modules, or they may be
`integrated onto a single integrated circuit or device, or integrated
`with other memory devices, for example in a three dimensional
`stack, or in any one of several other possible expedients for
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`integration known to those skilled in the art to achieve a specific
`design, application, or economic goal.
`Id. at 10:36–43.
`For the same reasons, we are unpersuaded by Patent Owner’s
`argument that boilerplate language cannot be used to broaden claims beyond
`what is disclosed in the Specification. PO Resp. 23–26.11 The ’831 patent’s
`disclosure that “[w]hile the DIMM form factor will predominate the
`discussion herein, it should be understood that this is for illustrative
`purposes only and memory systems using other form factors are
`contemplated as well” (Ex. 1001, 10:46–49), is not mere boilerplate.
`Patent Owner also relies upon disclosure in U.S. Patent Application
`No. 12/240,916 (“the ’916 application”), of which the ’831 patent is a
`continuation-in-part. PO Resp. 17–19; Ex. 1001 [63]. The ’916 patent
`explicitly describes an embodiment in which memory system 10 comprises
`PCB 20. Ex. 2018 ¶ 31. This argument is not persuasive, however, because
`when the application leading to the ’831 patent was filed, all references to
`“printed circuit board,” “PCB,” or even “board,” were deleted from the
`Specification and the more generic word “module” was used instead. That
`the applicant for the ’831 patent removed the words “PCB” and “printed
`circuit board” from the ’916 application and used only the word “module”
`instead suggests, if anything, that applicant intended “module” not to be
`limited to a PCB.
`
`
`11 Patent Owner’s citation to the “ID at 5–6” and the quote in parenthetical
`(Pet. 23–24) appears to be a citation to our Institution Decision in IPR2017-
`00560, not to our Institution Decision in this proceeding. Pet. Reply 10–11.
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`Patent Owner also relies upon a Final Written Decision in Diablo
`Techs., Inc. v. Netlist, Inc., Case No. IPR2014-00882, concerning U.S.
`Patent 7,881,150 (“the ’150 patent”). PO Resp. 26–27; Ex. 2021. Patent
`Owner’s reliance on this decision is not persuasive, however, because the
`’150 patent is not related to the ’831 patent and the Specification for the
`’150 patent is different from the Specification of the ’831 patent. For
`example, the ’150 patent explicitly discloses a printed circuit board, whereas
`the ’831 patent does not.
`Patent Owner also relies upon extrinsic evidence as support for its
`proposed construction. PO Resp. 27–31. There is no doubt that the DIMM
`form factor, including a PCB, was well-known. The issue, however, is
`whether the applicant for the ’831 patent intended the term “memory
`module” to require a PCB. In light of the intrinsic evidence that the
`applicant deleted the words “printed circuit board” and “PCB” from the
`Specification, explicitly contemplated non-DIMM form factors, and even
`contemplated a controller and data manager “integrated with other memory
`devices” (Ex. 1001, 10:39–40), Patent Owner’s extrinsic evidence does not
`persuade us that applicant intended “memory module” to require a PCB.
`Patent Owner also argues that our preliminary determination that
`“carrier” encompasses an integrated circuit package is overly broad because
`(a) the ’831 patent “does not describe any IC package comprising a PCB”
`and (b) it lacks any support from the industry or standards bodies. PO Resp.
`33–34. We disagree. As discussed, the ’831 patent explicitly contemplates
`integrating the controller and data manager “with other memory devices, for
`example in a three dimensional stack, or in any one of several other possible
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`expedients for integration known to those skilled in the art to achieve a
`specific design, application, or economic goal.” Ex. 1001, 10:36–43.
`Finally, Patent Owner argues, with respect to Best, that our
`construction “requires two layers of IC packages, in which a first IC package
`(the Board’s ‘carrier’) contains one or more second IC packages (the
`Board’s memory chips).” PO Resp. 39. Petitioner counters that “[t]he
`Board’s construction does no such thing.” Pet. Reply 18–19. We agree with
`Petitioner. Patent Owner’s argument is predicated upon the erroneous
`assertion that “[e]ach memory chip in the Board’s ‘carrier’ requires a
`different IC package (i.e., a second IC package) that encloses at least one
`memory die.” PO Resp. 39. Each memory chip does not require its own
`integrated circuit package. On the contrary, it may be, as Best discloses, a
`die enclosed with another die in a single IC package.
`Having considered the arguments and evidence, we maintain our
`construction of “memory module” to mean “a carrier that contains one or
`more memory chips,” where “carrier” encompasses an integrated circuit
`package.
`
`B. Level of Ordinary Skill in the Art
`Petitioner contends that a hypothetical person of ordinary skill in the
`art, with respect to and at the time of the’831 patent, “would be a person
`with a Bachelor’s degree in materials science, electrical engineering,
`computer engineering, computer science, or in a related field and at least one
`year of experience with the design or development of semiconductor non-
`volatile memory circuitry or systems.” Pet. 7; Ex. 1003 ¶¶ 55–56.
`Patent Owner contends that such a person “would have been a person
`with a Bachelor’s degree in electrical and/or computer engineering and at
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`least five years of industry experience designing memory devices and
`controllers” but that “[a] Master of Science degree in electrical and/or
`computer engineering would substitute for two years of industry experience”
`and “[a] Doctorate degree in electrical and/or computer engineering would
`substitute for four years of industry experience.” PO Resp. 43; Ex. 2016
`¶ 32.
`Patent Owner argues that a degree in material science would not be
`equivalent to a degree in electrical and/or computer engineering, and that
`Petitioner’s expert, Mr. Maltiel, who has only a degree in materials science,
`is not competent to testify to the understanding of a person of ordinary skill
`in the art. PO Resp. 43–44. Patent Owner did not, however, move to
`exclude the testimony of Mr. Maltiel. To the extent Patent Owner is arguing
`that we should accord Mr. Maltiel’s testimony little to no weight based on
`his qualifications, we decline to do so. After earning three degrees, Mr.
`Maltiel joined Intel in 1980 to work on the first commercial non-volatile
`EEPROM devices and, therefore, had 27 years of industry experience as of
`the earliest priority date to which the ’831 patent could be entitled. Ex. 1003
`¶¶ 3–9. Mr. Maltiel was recognized as a Senior Member of the IEEE in
`2008 and is a named inventor on six United States patents covering various
`aspects of memory devices, including for combining non-volatile and
`DRAM memories. Id. ¶¶ 10–12. As a result, we are persuaded that Mr.
`Maltiel is qualified to testify as to the understanding of a person of ordinary
`skill in the art at the time of the ’831 patent.
`Otherwise, we determine that no express finding on a specific
`corresponding level of technical education and experience is necessary.
`Here, the level of ordinary skill in the art is reflected by the prior art of
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`record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In
`re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re Oelrich, 579 F.2d
`86, 91 (CCPA 1978).
`
`C. Whether to Give Weight to Mr. Maltiel’s Testimony
`Patent Owner argues that Mr. Maltiel’s testimony should be given no
`weight because it is neither reliable nor credible. PO Resp. 41–42; see also
`id. at 62–64. In support of the argument, Patent Owner directs attention to
`portions of Dr. Maltiel’s cross examination testimony where he allegedly (1)
`“contradicted himself on critical matters;” (2) “made a number of statements
`that are simply incorrect;” and (3) “concede[d] that he did not consider the
`complete intrinsic record, including the ’916 patent application.” Id.
`Petitioner counters that Mr. Maltiel is qualified, reliable, and credible.
`Pet. Reply 24–25.
`We have reviewed the arguments provided by Patent Owner and
`determine such arguments are insufficient to have Mr. Maltiel’s declaration
`excluded in its entirety. Rather, it is within our discretion to assign the
`appropriate weight to be accorded evidence. See 37 C.F.R. § 42.65(a); see
`also, e.g., Yorkey v. Diab, 601 F.3d 1279, 1284 (Fed. Cir. 2010) (holding the
`Board has discretion to give more weight to one item of evidence over
`another “unless no reasonable trier of fact could have done so”); In re Am.
`Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1368 (Fed. Cir. 2004) (“[T]he Board
`is entitled to weigh the declarations and conclude that the lack of factual
`corroboration warrants discounting the opinions expressed in the
`declarations.”); and Velander v. Garner, 348 F.3d 1359, 1371 (Fed. Cir.
`2003) (“In giving more weight to prior publications than to subsequent
`conclusory statements by experts, the Board acted well within [its]
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`discretion.”). Based on the record before us, we are not persuaded that we
`should give the entirety of Mr. Maltiel’s declaration no weight.
`
`D. The Parties’ Post-Institution Arguments
`In our Decision on Institution, we concluded that the arguments and
`evidence advanced by Petitioner demonstrated a reasonable likelihood that
`(1) claims 1–14 of the ’831 patent are unpatentable under 35 U.S.C. § 102 as
`anticipated by Best; (2) claims 1–14 under 35 U.S.C. § 103(a) are obvious
`over Best; (3) claims 1–14 under 35 U.S.C. § 103(a) are obvious over Best
`and Roy; and (4) claim 15 over Bowie under 35 U.S.C. § 103(a) is obvious
`over Best, Mills, and Bonella, with or without Roy. Inst. Dec. 28. We
`subsequently instituted on the remaining grounds asserted by Petitioner.
`Paper 23. We must now determine whether Petitioner has established by a
`preponderance of the evidence that claims 1–15 are unpatentable over the
`cited prior art. 35 U.S.C. § 316(e). We previously instructed Patent Owner
`that “any arguments for patentability not raised in the [Patent Owner
`Response] will be deemed waived.” Paper 3, 3; see also 37 C.F.R.
`§ 42.23(a) (“Any material fact not specifically denied may be considered
`admitted.”); In re Nuvasive, Inc., 842 F.3d 1376, 1379–1382 (Fed. Cir.
`2016) (holding Patent Owner waived an argument addressed in Preliminary
`Response by not raising the same argument in the Patent Owner Response).
`Additionally, the Board’s Trial Practice Guide states that the Patent Owner
`Response “should identify all the involved claims that are believed to be
`patentable and state the basis for that belief.” Office Patent Trial Practice
`Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012).
`With a complete record before us, we note that we have reviewed
`arguments and evidence advanced by Petitioner to support its unpatentability
`
`17
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`Patent 8,874,831 B2
`
`contentions where Patent Owner chose not to address certain limitations in
`its Patent Owner Response. In this regard, the record now contains
`persuasive, unrebutted arguments and evidence presented by Petitioner
`regarding the manner in which the asserted prior art teaches corresponding
`limitations of the claims against which that prior art is asserted. Based on
`the preponderance of the evidence before us, we conclude that the prior art
`identified by Petitioner teaches or suggests all uncontested limitations of the
`reviewed claims. The limitations that Patent Owner contests in the Patent
`Owner Response are addressed below.
`
`E. Claims 1–14: Anticipation by Best
`Petitioner argues that claims 1–14 are unpatentable under
`35 U.S.C. § 102(e) as anticipated by Best. Pet. 20–49.
`1. Principles of Law
`To establish anticipation, “all of the elements and limitations of the
`claim must be shown in a single prior reference, arranged as in the claim.”
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
`2001). When evaluating a single prior art reference in the context of
`anticipation, the reference must be “considered together with the knowledge
`of one of ordinary skill in the pertinent art.” In re Paulsen, 30 F.3d 1475,
`1480 (Fed. Cir. 1994) (citing In re Samour, 571 F.2d 559, 562 (CCPA
`1978)). “‘[T]he dispositive question regarding anticipation[, therefore, i]s
`whether one skilled in the art would reasonably understand or infer from the
`[prior art reference’s] teaching’ that every claim element was disclosed in
`that single reference.” Dayco Prods., Inc. v. Total Containment, Inc., 329
`F.3d 1358, 1368 (Fed. Cir. 2003) (alterations in original) (quoting In re
`Baxter Travenol Labs., 952 F.2d 388, 390 (Fed. Cir. 1991)). We analyze
`
`18
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`this asserted ground based on anticipation with the principles stated above in
`mind.
`
`2. Best Overview
`Best is directed to a hybrid volatile and non-volatile memory device.
`Ex. 1006, Abstract. Specifically, Best discloses “[a]composite, hybrid
`memory device including a first storage die having an array of volatile
`storage cells and a second storage die having an array of non-volatile storage
`cells disposed within an integrated circuit package.” Id. “The hybrid
`memory device includes a shared interface circuit to receive memory access
`commands directed to the first storage die and the second storage die and to
`convey read and write data between an external data path and the first and
`second storage dice.” Id.
`Figure 2 of Best is reproduced below.
`
`
`Figure 2 illustrates an embodiment of a hybrid, composite memory device
`with shared interface circuitry, volatile memory, and non-volatile memory.
`
`19
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`Id. ¶ 17. “[T]he shared interface circuitry includes an external request
`interface 125, external data interface 133, command decoder 122, address
`queue 135, DRAM control circuit 129, Flash control circuit 137, and data
`control/steering circuit 131.” Id. “[I]ncoming control signals and addresses
`. . . are received in the external request interface 125 via control/address
`(CA) path 126, reformatted as necessary (e.g., deserialized to form a parallel
`command word and one or more address values) and then forwarded to the
`command decoder 122.” Id. “The command decoder 122 in turn forwards
`address to the address queue 135 and stores memory access commands.” Id.
`“[M]emory access operations may be automatically directed to either the
`volatile storage die or non-volatile storage die according to the memory
`address to be accessed.” Id. “[C]ommand decoder 122 outputs, from the
`head of the command queue, an enable signal and corresponding memory
`access control signals to the DRAM control circuit 129 and NV control
`circuit 137.” Id. ¶ 18. “[D]ata control/steering circuit 131 is used to control
`the transfer of data between a shared internal data bus and dedicated internal
`data buses associated with the volatile and non-volatile storage dice,
`respectively.” Id. ¶ 20.
`Figure 3 of Best is reproduced below.
`
`
`
`20
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`Figure 3 illustrates an embodiment of a data control/steering circuit 150 that
`may be used to implement the data control/steering circuit 131 of Figure 2.
`Id. ¶ 21. “[D]ata control circuit 151 receives control signals from the
`command decoder that indicate the direction of data flow during a memory
`access operation (read or write) and whether the volatile or non-volatile
`storage die is the target of the memory access.” Id.
`3. Petitioner’s Initial Positions
`Petitioner contends that Best anticipates claims 1–14 of the ’831
`patent. Pet. 20–49. We have reviewed the Petition, Patent Owner’s
`Response, and Petitioner’s Reply, as well as the relevant evidence discussed
`in those papers and other record papers, and are persuaded that the record
`establishes Petitioner’s contentions for claims 1–14, and we adopt
`Petitioner’s contentions discussed below as our own.
`For example, Claim 1 recites “[a] memory module couplable to a
`memory controller of a host system.” Petitioner relies upon Best’s
`disclosure of “a ‘hybrid composite memory device having non-volatile and
`volatile memories implemented in distinct integrated circuit (IC) dice that
`are packaged together and accessed through a shared interface.’” Pet. 20
`(quoting Ex. 1006 ¶ 12). In light of our construction of “memory module”
`to mean “a carrier that contains one or more memory chips,” where “carrier”
`encompasses an integrated circuit package, we are persuaded by Petitioner’s
`showing and find that Best’s integrated circuit package containing first and
`second storage die teaches the recited “memory module.”
`Claim 1 further recites “a non-volatile memory subsystem.”
`Petitioner relies upon Best’s disclosure of a Flash memory. Pet. 21. We are
`
`21
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`persuaded by Petitioner’s showing and find that Best’s Flash memory
`teaches the recited “non-volatile memory subsystem.”
`Claim 1 further recites “a data manager coupled to the non-volatile
`memory subsystem.” Petitioner relies upon Best’s data control/steering
`circuit i
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