Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`Paper No. 1
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SK HYNIX INC., SK HYNIX AMERICA INC., and SK HYNIX MEMORY
`SOLUTIONS INC.,
`Petitioners,
`
`v.
`
`NETLIST, INC.
`Patent Owner.
`
`Patent No. 9,128,632
`Issued: September 8, 2015
`Filed: July 27, 2013
`Inventors: Hyun Lee and Jayesh R. Bhakta
`Memory Module with Distributed Data Buffers and Method of
`Operation
`
`Title:
`
`____________________
`Inter Partes Review No. IPR2017-00730
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`
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`
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`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 9,128,632
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.1-.80 & 42.100-.123
`________________________
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`

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`Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`TABLE OF CONTENTS
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`I.
`
`COMPLIANCE WITH REQUIREMENTS FOR A PETITION
`
`FOR INTER PARTES REVIEW ................................................................. 1
`A.
`Certification the 632 Patent May Be Contested by Petitioners ............. 1
`B.
`Fee for Inter Partes Review (§ 42.15(a)) ............................................... 1
`C. Mandatory Notices (37 CFR § 42.8(b)) ................................................ 1
`D.
`Proof of Service (§§ 42.6(e) and 42.105(a)) ......................................... 2
`II.
`Identification of Claims Being Challenged (§ 42.104(b)) ........................... 2
`III. Relevant Information Concerning the Contested Patent .......................... 3
`A.
`Effective Filing Date of the 632 Patent ................................................. 3
`B.
`Person of Ordinary Skill in the Art ....................................................... 3
`C.
`The 632 Patent ....................................................................................... 4
`1. Technical Overview of the 632 Patent ............................................ 4
`2. The Prosecution History of The 632 Patent .................................... 5
`D.
`Construction of Terms Used in the 632 Patent Claims ......................... 6
`1. “memory module” ............................................................................ 6
`2. “memory system” ............................................................................. 7
`3. “memory controller” ....................................................................... 7
`4. “memory bus” .................................................................................. 7
`5. “memory command signals” ........................................................... 8
`6. “module command signals” ............................................................ 9
`7. “module control signals” ................................................................ 9
`8. “metastability” ................................................................................. 9
`IV. Overview Of The Prior Art ......................................................................... 10
`A. USPPA 2010/0309706 to Saito (Ex. 1005) ......................................... 10
`USP 7,808,849 to Swain (Ex. 1006) ................................................... 13
`B.
`C.
`USP 6,184,701 to Kim (Ex. 1007) ...................................................... 14
`
`i
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`Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`V.
`
`Claims 1-5, 12-14, and 19-20 are Obvious Over Saito in view
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`Precise Reasons for Relief Requested ........................................................ 15
`A.
`of Swain ............................................................................................... 15
`1. Claim 1 is Obvious ........................................................................ 15
`2. Claim 2 is Obvious ........................................................................ 33
`3. Claim 3 is Obvious ........................................................................ 35
`4. Claim 4 is Obvious ........................................................................ 39
`5. Claim 5 is Obvious ........................................................................ 42
`6. Claim 12 is Unpatentable .............................................................. 42
`7. Claim 13 is Obvious ...................................................................... 45
`8. Claim 14 is Obvious ...................................................................... 46
`9. Claim 19 is Obvious ...................................................................... 46
`10. Claim 20 is Obvious ...................................................................... 49
`B.
`further view of Kim ............................................................................. 49
`1. Claim 3 is Obvious ........................................................................ 49
`VI. CONCLUSION ............................................................................................ 53
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`Claims 3 and 13-14 are Obvious Over Saito in view of Swain in
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`
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`Attachment A. Proof of Service of the Petition
`
`Attachment B. List of Evidence and Exhibits Relied Upon in Petition
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`ii
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`Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`I.
`
`COMPLIANCE WITH REQUIREMENTS FOR A PETITION
`FOR INTER PARTES REVIEW
`A. Certification the 632 Patent May Be Contested by
`Petitioners
`Petitioners certify they are not barred or estopped from requesting inter
`
`partes review of U.S. Patent No. 9,128,632 (“the 632 Patent”) (Ex. 1001). No
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`Petitioner, nor any party in privity with a Petitioner, has filed a civil action
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`challenging the validity of any claim of the 632 Patent. The 632 Patent has not
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`been the subject of a prior inter partes review by any Petitioner or a privy of a
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`Petitioner. Petitioners also certify this petition for inter partes review is filed
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`within one year of the date of service of a complaint alleging infringement of a
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`patent – no complaint alleging infringement of the 632 Patent has been served on
`
`any Petitioner. Petitioners therefore certify this patent is available for inter partes
`
`review.
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`Fee for Inter Partes Review (§ 42.15(a))
`
`B.
`The Director is authorized to charge the fee specified by 37 CFR § 42.15(a)
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`to Deposit Account No. 50-1597.
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`C. Mandatory Notices (37 CFR § 42.8(b))
`The real parties of interest of this petition are the Petitioners.
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`The 632 Patent is not involved in any other legal proceedings, to Petitioners’
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`knowledge.
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`Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`Lead Counsel is Joseph A. Micallef (Reg. No. 39,772), Sidley-SKH-
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`IPR@sidley.com, (202) 736-8492. Backup Lead Counsel is Michael D. Hatcher
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`(Reg. No. 47,636), Sidley-SKH-IPR@sidley.com, (214) 981-3428.
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`Service on Petitioner may be made by mail or hand delivery to: Sidley
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`Austin LLP, 1501 K Street, N.W., Washington, D.C. 20005. The fax number for
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`lead and backup counsel is (202) 736-8711.
`
`D.
`Proof of Service (§§ 42.6(e) and 42.105(a))
`Proof of service of this petition is provided in Attachment A.
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`II.
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`Identification of Claims Being Challenged (§ 42.104(b))
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`Claims 1-5, 12-14 and 19-20 of the 632 Patent are unpatentable as follows:
`
`(i)
`
`Claims 1-5, 12-14 and 19-20 of the 632 Patent are unpatentable as
`obvious under 35 U.S.C. § 103 over United States Published Patent
`Application No. 2010/0309706 to Saito (“Saito”), attached hereto as
`Ex. 1005, in view of United States Patent No. 7,808,849 to Swain
`(“Swain”), attached hereto as Ex. 1006; and
`
`(ii) Claims 3 and 13-14 of the 632 Patent are unpatentable as obvious
`under 35 U.S.C. § 103 Saito in view of Swain in further view of
`United States Patent No. 6,184,701 to Kim (“Kim”), attached hereto
`as Ex. 1007.
`
`Petitioner’s proposed claim constructions, the evidence relied upon, and the precise
`
`reasons why the claims are unpatentable are provided in §§ III-V, below. The
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`evidence relied upon in this petition is listed in Attachment B.
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`Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`III. Relevant Information Concerning the Contested Patent
`A. Effective Filing Date of the 632 Patent
`The application that resulted in the 632 Patent is U.S. Patent Application
`
`Serial No. 13/952,599, filed Jul. 27, 2013. Ex. 1001 at Face. The 632 Patent
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`claims priority to U.S. Provisional Application No. 61/676,883, filed Jul. 27, 2012.
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`Petitioner therefore assumes that the claims of the 632 Patent have an effective
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`filing date of July 27, 2012.
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`Person of Ordinary Skill in the Art
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`B.
`A person of ordinary skill in the art in the field of the 632 Patent would have
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`been someone with an advanced degree in electrical or computer engineering and
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`at least two years working in the field, or a bachelor’s degree in such engineering
`
`disciplines and at least three years working the field. Such a person would have
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`been knowledgeable about the design and operation of computer memories,
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`including DRAM and SDRAM devices that were compliant with various
`
`standards, and how they interact with other components of a computer system,
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`such as memory controllers. He or she would also have been familiar with the
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`structure and operation of circuitry used to access and control computer memories,
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`including sophisticated circuits such as ASICs and CPLDs and less sophisticated
`
`circuits such as data buffers, flip flops and registers. Ex. 1003 at ¶39.
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`Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`C. The 632 Patent
`1.
`Technical Overview of the 632 Patent
`The 632 Patent discloses memory modules with multiple memory devices,
`
`data buffers and circuitry for controlling write and read operations between the
`
`memory module and a memory controller. Ex. 1001 at Abstract. In one exemplary
`
`embodiment, the memory module includes memory devices organized in groups,
`
`each group with an associated data buffer and one module control device for the
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`entire module, id. at 3:8-10, wherein the memory devices and data buffers are
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`distributed length-wise across the memory module and the module control device
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`is centrally located, id. at 3:12-36, Fig. 2C. Ex. 1003 at ¶40.
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`A memory bus includes control/address (C/A) signal lines between the
`
`memory controller and the module control device and data/strobe signal lines
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`between the memory controller and each memory device via each data buffer. Ex.
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`1001 at 4:1-13. The memory controller issues C/A signals to the memory module
`
`via the module control device, and sends and receives data/strobe signals to/from
`
`the memory devices via the data buffers. Id.; see also id. at 4:45-52, 5:34-6-3; Ex.
`
`1003 at ¶¶41-43.
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`Because the data buffers and their associated memory devices are distributed
`
`across the memory module varying distances from the module control device, they
`
`receive module control signals at different times. Ex. 1001 at 9:23-42. Each data
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`buffer thus includes signal alignment circuits that determine appropriate time
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`intervals to use to adjust for the signals arriving at different times. Id. at 9:43-56;
`
`see also Ex. 1003 at ¶44. The 632 patent discloses that a time interval can be
`
`determined by the data buffer based on the timing of a write operation and that
`
`such time interval can be used to adjust timing during a read operations. Ex. 1001
`
`at 15:1-54; see also Ex. 1003 at ¶45.
`
`The Prosecution History of The 632 Patent
`
`2.
`The Examiner rejected the original claims of the application underlying the
`
`632 Patent as anticipated by Manohararajah. Ex. 1002 at 100-108. In response,
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`the applicant amended the claims, inter alia, by adding language requiring each
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`data buffer to be configured to “determine a respective time interval based on
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`signals received by the each respective buffer circuit during a memory write
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`operation” and to “time transmission of a respective set of read data signals
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`received from the respective group of memory devices in accordance with the time
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`interval and a read latency parameter . . . .” Ex. 1002 at 134-135. Among other
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`things, the applicant argued that “[n]owhere in Manohararajah it is [sic] described
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`the transmission of read data signal from each respective buffer is timed in
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`accordance with a time interval determined based signals [sic] received by the each
`
`respective buffer. Thus, Manohararajah does not anticipate claim 1 as amended.”
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`Petition for Inter Partes Review of U.S. Patent No. 9,128,632
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`Id. at 8-9; See also Ex. 1003 at ¶47. In response, the Examiner issued a notice of
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`allowance. Ex. 1002 at 1078.
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`D. Construction of Terms Used in the 632 Patent Claims
`In this proceeding, claims must be given their broadest reasonable
`
`construction in light of the specification. 37 CFR § 42.100(b). If Patent Owner
`
`contends terms in the claims should be read to have a special meaning, those
`
`contentions should be disregarded unless Patent Owner also amends the claims
`
`compliant with 35 U.S.C. § 112 to make them expressly correspond to those
`
`contentions. See 77 Fed. Reg. 48764 at II.B.6 (Aug. 14, 2012); cf. In re Youman,
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`679 F.3d 1335, 1343 (Fed. Cir. 2012).
`
`“memory module”
`
`1.
`The broadest reasonable interpretation of “memory module” is “a removable
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`circuit board, cartridge, or other carrier that contains one or more RAM memory
`
`chips.” For instance, the Microsoft Computer Dictionary defines a “memory
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`module” as “[a] removable circuit board, cartridge, or other carrier that contains
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`one or more RAM memory chips.” Microsoft Computer Dictionary 334 (5th ed.
`
`2002) (attached as Ex. 1009). This is consistent with the 632 Patent: “A memory
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`module usually includes multiple memory devices, such as dynamic random access
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`memory devices (DRAM) or synchronous dynamic random access memory
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`devices (SDRAM), packaged individually or in groups, and/or mounted on a
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`printed circuit board (PCB).” Ex. 1001 at 1:39-44; see also Ex. 1003 at ¶¶53-55.
`
`“memory system”
`
`2.
`The broadest reasonable interpretation of “memory system” is “a collection
`
`of component elements that work together to perform a memory task, including a
`
`memory module and memory controller.” For instance, the Microsoft Computer
`
`Dictionary defines a “system” as “[a] collection of component elements that work
`
`together to perform a task.” Ex. 1009 at 508. And the 632 patent states that its
`
`memory system includes a memory module and a memory controller. Ex. 1001 at
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`Abstract (“A memory module is operable in a memory system with a memory
`
`controller.”); see also id. at Fig. 1. See also Ex. 1003 at ¶¶56-58.
`
`“memory controller”
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`3.
`The broadest reasonable interpretation of “memory controller” is “a device
`
`capable of sending instructions or commands or otherwise controlling memory
`
`devices.” The 632 Patent explicitly states that, “[i]n the context of the present
`
`description, a memory controller refers to any device capable of sending
`
`instructions or commands, or otherwise controlling the memory devices 112.” Ex.
`
`1001 at 4:27-30. This is consistent with the understanding in the field. See Ex.
`
`1003 at ¶¶59-61.
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`4.
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`“memory bus”
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`The broadest reasonable interpretation of “memory bus” is “any component,
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`connection, or groups of components and/or connections, used to provide electrical
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`communication between a memory module and a memory controller.” The 632
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`Patent explicitly states that: “a memory bus refers to any component, connection,
`
`or groups of components and/or connections, used to provide electrical
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`communication between a memory module and a memory controller.” Ex. 1001 at
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`4:30-38. This is consistent with the understanding in the field. See Ex. 1003 at
`
`¶¶62-64.
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`“memory command signals”
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`5.
`The broadest reasonable interpretation of “memory command signals” is
`
`“signals from the memory controller, including control and address signals, that
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`direct memory operations.” The 632 Patent states that “[t]he memory module is
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`operable to perform memory operations in response to memory commands (e.g.,
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`read, write, refresh, precharge, etc.), each of which is represented by a set of
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`control/address (C/A) signals transmitted by the memory controller to the memory
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`module. The C/A signals may include, for example, a row address strobe signal
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`(/RAS), a column address strobe signal (/CAS), a write enable signal (/WE), an
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`output enable signal (/OE), one or more chip select signals, row/column address
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`signals, and bank address signals.” Ex. 1001 at 3:12-21 (emphasis added); see
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`also Ex. 1003 at ¶¶65-67.
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`“module command signals”
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`6.
`The broadest reasonable interpretation of “module command signals” is
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`“signals derived from the memory command signals that are provided to memory
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`devices to control operation of the memory devices.” The 632 Patent states that
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`“the module control device … generates a set of module command signals … in
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`response to each memory command from the memory controller”, Ex. 1001 at
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`3:24-27, and that the “module command signals are provided to memory devices . .
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`. .” Id. at Abstract; see also Ex. 1003 at ¶¶68-70.
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`“module control signals”
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`7.
`The broadest reasonable interpretation of “module control signals” is
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`“signals derived from the memory command signals that are provided to buffer
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`circuits to control operations of the buffer circuits.” The 632 Patent states that “the
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`module control device … generates … a set of module control signals in response
`
`to each memory command from the memory controller,” Ex. 1001 at 3:24-27, and
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`that the “module control signals are provided to a plurality of buffer circuits to
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`control data paths in the buffer circuits.” Id. at Abstract; see also Ex. 1003 at
`
`¶¶71-73.
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`“metastability”
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`8.
`The broadest reasonable interpretation of “metastability” is “misalignment
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`of a signal from the relevant clock signal.” The 632 Patent states that, “[a]s the
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`module control signals travel over such a distance, they can become misaligned
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`with the module clock signal, resulting in metastability in the received module
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`control signals.” Ex. 1001 at 9:15-20 (emphasis added); see also Ex. 1003 at
`
`¶¶74-76.
`
`IV. Overview Of The Prior Art
`A. USPPA 2010/0309706 to Saito (Ex. 1005)
`United States Published Patent Application No. 2010/0309706 to Saito
`
`(“Saito”) was filed on June 3, 2010 and published on December 9, 2010. Saito is
`
`thus prior art to the 632 Patent under 35 U.S.C. §§ 102(a), (b) & (e).
`
`Saito discloses a memory module including “thirty-six memory chips.” Ex.
`
`1005 at [0044]. The memory chips and other components are mounted on “a
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`printed circuit board that includes a multilayer wiring. The planar shape of the
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`module PCB 110 is substantially rectangle.” Id. at [0045]. Along one of the long
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`sides, “a plurality of data connectors 120 and a plurality of
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`command/address/control connectors 130 are provided … for making an electrical
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`connection with a memory controller via a memory slot . . . .” Id.; Ex. 1003 at ¶78.
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`The 36 memory chips are in a “4-rank configuration.” Ex. 1005 at [0049].
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`“[F]our memory chips 200 constitute a single group (a single set), and the four
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`memory chips 200 constituting the single group belong to different Ranks from
`
`each other.” Id. at [0050]. “[T]he memory module 100 includes nine data register
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`buffers 300,” one for each of the nine groups of four memory chips. Id. at [0044],
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`[0053]. “The data connectors 120 are connectors for exchanging write data to be
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`written in the memory chip 200 and read data read from the memory chip 200
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`between the memory module 100 and the memory controller.” Id. at [0046]. The
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`data connectors are “substantially right below the memory chips,” with the
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`corresponding data register buffers in between the memory chips and the
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`connectors. Id.; Ex. 1003 at ¶79.
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`The memory module also includes one centrally located
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`“command/address/control register buffer 400.” Ex. 1005 at [0057]. “The
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`command/address/control connectors 130 are connectors for supplying a command
`
`signal, an address signal, a control signal, and a clock signal to be supplied to the
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`command/address/control register buffer 400.” Id. at [0047]. They are also
`
`centrally located, below the “command/address/control register buffer.” Id.; Ex.
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`1003 at ¶80.
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`“The command/address/control register buffer 400 receives the command
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`signal, the address signal, the control signal, and the clock signal” from the
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`memory controller, “buffers the signals, and supplies the signals to the memory
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`chips 200.” Ex. 1005 at [0058]. “At the same time, the command/address/control
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`register buffer 400 generates a control signal” and supplies it “to the data register
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`buffers . . . .” Id. at [0059]; Ex. 1003 at ¶81.
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`Figure 1 of Saito illustrates its memory module, reproduced below with the
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`“command/address/control register buffer” colored red, the “memory chips”
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`colored green, the “data register buffers” colored blue, the “data connectors” (data
`
`buses) colored yellow, the “command/address/control connectors”
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`(command/address/control bus) colored purple, and the command and control
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`signal buses on the module between the “command/address/control register buffer”
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`and the “memory chips” and “data register buffers” colored orange:
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`Saito recognizes that, with high speed operation and “memory chips” and
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`“data register buffers” distributed different distances from the
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`“command/address/control register buffer,” there will be timing issues with the
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`signals arriving at the respective chips and buffers requiring “timing adjustments.”
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`Ex. 1005 at [0087], [0101]. The memory module sets these “timing adjustments”
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`during initialization by performing write leveling and read leveling operations.
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`Each group of memory chips/data register buffer performs two sets of write and
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`read leveling operations, one “between the data register buffer 300 and the memory
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`chip 200,” id. at [0138], and one “between the memory controller and the data
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`register buffer 300 . . . .” Id. at [0139]; Ex. 1003 at ¶83.
`
`Saito’s “data register buffers” also include “DLL circuits” that operate
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`during normal operation as opposed to initialization. Ex. 1005 at [0082]. “The
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`DLL circuit 310 is a circuit that generates the internal clocks LCLKW and LCLKR
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`based on the clock signal CK that is supplied from the command/address/control
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`register buffer 400 . . . .” Id. at [0084]. It “generates an internal clock signal of
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`which a phase is controlled with respect to an external clock signal, which is used
`
`for matching the phases of the read data DQ and the data strobe signal DQS with
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`the phase of the clock signal CK.” Id. at [0161]; Ex. 1003 at ¶84.
`
`B. USP 7,808,849 to Swain (Ex. 1006)
`United States Patent No. 7,808,849 to Swain (“Swain”) was filed on July 8,
`
`2008 and issued on October 5, 2010. Swain is thus prior art to the 632 Patent
`
`under 35 U.S.C. §§ 102(a), (b) & (e).
`
`Swain is focused on systems and methods for performing read leveling in
`
`memory modules with memory devices spread across a PCB, what Swain refers to
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`as “a sequential chained topology.” Ex. 1006 at Abstract. “Read leveling needs to
`
`be performed for each of the memory units since the accurate values for
`
`corresponding compensation delay are different for different memory units [based
`
`on different propagation delays.]” Id. at 1:39-50; see also Ex. 1003 at ¶86.
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`Swain teaches that its system first performs write leveling during
`
`initialization and that, during the read leveling operation during initialization, one
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`option for setting the timing adjustment or delay for read operations is to use the
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`“parameters determined while write leveling.” Ex. 1006 at 5:59-64. Swain’s
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`exemplary memory module is one without data register buffers between the
`
`memory chips and the memory controller, consequently, Swain has only a single
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`set of write and read leveling operations, between the memory controller and the
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`memory chips. “However,” as Swain explains, “various features can be
`
`implemented in other environments … without departing from the scope and spirit
`
`of various aspects of the present invention, as will be apparent to one skilled in the
`
`relevant arts by reading the disclosure provided herein.” Id. at 5:31-36; see also
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`Ex. 1003 at ¶87.
`
`C. USP 6,184,701 to Kim (Ex. 1007)
`United States Patent No. 6,184,701 to Kim (“Kim”) was filed on May 27,
`
`1999 and issued on February 6, 2001. Kim is thus prior art to the 632 Patent under
`
`35 U.S.C. §§ 102(a), (b) & (e).
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`Kim discloses “a metastability detection/prevention circuit 20” to be
`
`incorporated with any “main active circuit 10” in need thereof. Ex. 1007 at 2:21-
`
`22. Kim teaches that “the circuit 10 may comprise a data input buffer . . . .” Id. at
`
`2:30-31. “[T]he metastability detection/prevention circuit 20 preferably performs
`
`the function of detecting whether the output POUT of the main active circuit 10
`
`has been disposed in a metastable state for a duration in excess of a transition
`
`duration.” Id. at 2:33-37; Ex. 1003 at ¶89.
`
`V.
`
`Precise Reasons for Relief Requested
`A. Claims 1-5, 12-14, and 19-20 are Obvious Over Saito in view
`of Swain
`1.
`
`Claim 1 is Obvious
`a)
`The first part of the preamble of claim 1 requires “[a] memory module to
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`Preamble part 1
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`operate in a memory system with a memory controller.”
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`Saito discloses a memory module 100 that operates in a memory system 20
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`with a memory controller (or MCH) 12. Ex. 1005 at [0062-64], Fig 2. Saito thus
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`discloses this claim element. Ex. 1003 at ¶¶90-92.
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`b)
`The second part of the preamble of claim 1 requires “the memory system
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`Preamble part 2
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`operating according to a system clock.”
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`Saito discloses that his “memory system” operates according to a “system
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`clock” CK, provided by the memory controller. Ex. 1005 at [0045]. Saito thus
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`discloses this claim element. Ex. 1003 at ¶¶93-95.
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`c)
`The third part of the preamble of claim 1 requires “the memory system
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`Preamble Part 3
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`including a memory bus coupling the memory module to the memory controller,
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`the memory bus including a set of control/address signal lines and a plurality of
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`sets of data/strobe signal lines, the memory module comprising.”
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`Saito discloses a group of components and connections that provide
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`electrical communication between the memory module and the memory controller,
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`i.e., a “memory bus,” including data signal lines and control/address signal lines.
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`Specifically, Saito discloses data connectors 120 and command/address/control
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`connectors 130 that connect the signal line 23 on the motherboard to data and
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`control signal lines on the memory module. These data and control signal lines
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`connect to the components of the memory module and the memory controller,
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`respectively. Ex. 1005 at [0045]; [0046]; [0068]; Figs. 1 and 3 (annotated below).
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`Saito discloses that the L0, L1 and L2 signal lines above in Figure 1, “the
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`plurality of data signal lines,” each provide data signal lines DQ and data strobe
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`signal lines DQS to the plurality of memory chips 200 and data register buffers
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`300. Ex. 1005 at [0100].
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`Saito further discloses that the command/address/control register buffer 400
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`(i.e., “module control device”) “receives the command signal, the address signal,
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`the control signal, and the clock signal (in some cases, collectively referred to as a
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`command/address/control signal and the like) that are supplied from the
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`command/address/control connectors 130 through an input terminal 401, buffers
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`the signals, and supplies the signals to the memory chips 200.” Id. at [0058]
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`(emphasis added). Figure 1, annotated above, illustrates that the
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`command/address/control register buffer 400 receives this set of “control/address
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`signal lines” via command/address/control connectors 130 and command/address/
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`control line L3.
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`Data connectors 120, command/address/control line connectors 130, data
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`lines L0, L1 and L2 and command/address/control line L3 are all part of the
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`memory bus, as they are used to provide electrical communication between a
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`memory module and a memory controller. Ex. 1003 at ¶100.
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`Saito thus discloses this claim element. Id. at ¶¶96-101.
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`d)
`Claim 1 requires “a module control device to receive memory command
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`module control device
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`signals from the memory controller and to output module command signals and
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`module control signals in response to the memory command signals.”
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`Saito discloses a command/address/control register buffer 400 (“module
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`control device”) that receives memory command signals from the memory
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`controller. Specifically, Saito discloses that “[t]he command/address/control
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`register buffer 400 receives the command signal, the address signal, the control
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`signal, and the clock signal [“memory command signals”] . . . that are supplied
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`from the command/address/control connectors 130 through an input terminal 401,
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`buffers the signals, and supplies the signals to the memory chips 200.” Ex. 1005 at
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`[0058] (emphasis added); see also id. at [0052]. As explained above,
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`command/address/control connectors 130 connect the command/address/control
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`register buffer 400 to the memory controller. Id. at [0045], [0093].
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`The command/address/control register buffer 400 (“module control device”)
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`outputs module command signals in response to the memory command signals.
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`For example, Saito discloses that “[t]he command/address/control signal
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`[“memory command signal”] that is supplied from the memory controller 12 is
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`input from the input terminal 401. Among input command/address/control signals,
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`the command signal CMD, the address signal ADD, and the control signal CTRL
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`are supplied to a register circuit 410, and the clock signal CK is supplied to a PLL
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`circuit 420. The register circuit 410 is a circuit that buffers the command signal
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`CMD, the address signal ADD, and the control signal CTRL, and the buffered
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`command signal CMD, address signal ADD, and control signal CTRL
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`[“module command signals”] are supplied to the memory chip 200 via the output
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`terminal 402.” Ex. 1005 at [0094] (emphasis added); see also id. at [0072-0077],
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`Figs. 4 and 6.
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`The command/address/control register buffer 400 (“module control device”)
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`likewise outputs module control signals in response to the memory command
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`signals, including the DRC signals and the CK signal. Ex. 1005 at [0096], [0059],
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`Fig. 6. The DRC signals and CK signal are therefore “module control signals”
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`because they are derived from the memory command signals and provided to the
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`buffer circuits to control operations of the buffer circuits. See also, id. at [0084],
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`[0097], Fig. 5; Ex. 1003 at ¶105.
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`Saito thus discloses this claim element. Ex. 1003 at ¶¶102-106.
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`e)
`Claim 1 further requires “memory devices organized in groups, each group
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`memory devices organized in groups
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`including at least one memory device, the memory devices receiving the module
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`command signals from the module control device and performing one or more
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`memory operations in accordance with the module command signals.”
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`Saito discloses memory devices organized in groups with each group
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`including at least one memory device. Ex. 1005 at [0051]; see also id. at [0054].
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`One group is included in the red box in annotated Figure 1 below:
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`Saito further explains that each memory device in th