UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`
`
`Xilinx, Inc.
`Petitioner
`
`
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 7,525,189
`Issue Date: Apr. 28, 2009
`Title: SEMICONDUCTOR DEVICE, WIRING BOARD, AND
`MANUFACTURING METHOD THEREOF
`_______________
`
`Inter Partes Review No. 2017 –
`
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§311 – 319 AND 37 CFR §42.100 ET SEQ.
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`TABLE OF CONTENTS
`
`PETITIONER'S EXHIBIT LIST ............................................................................. iv 
`
`Note Regarding Page Citations ........................................................................ iv 
`
`I. 
`
`INTRODUCTION ............................................................................................. 1 
`
`II.  MANDATORY NOTICES ............................................................................... 1 
`
`A.  Real Party-In-Interest ................................................................................ 1 
`
`B.  Related Matters .......................................................................................... 1 
`
`C.  Lead and Back-up Counsel and Service Information ............................... 1 
`
`D.  Grounds for Standing ................................................................................ 1 
`
`III.  BACKGROUND AND INTRODUCTION TO THE PATENT AND
`PRIOR ART REFERENCES OF THE PRESENT PETITION ........................ 2 
`
`A.  Technology Background ........................................................................... 2 
`
`B.  The Claimed Subject Matter of Tago ........................................................ 4 
`
`C.  Brief Introduction to the Prior Art of the Present Petition ...................... 10 
`
`IV.  STATEMENT OF PRECISE RELIEF REQUESTED ................................... 12 
`
`A.  Claim for Which Review is Requested ................................................... 12 
`
`B.  Claim Construction .................................................................................. 12 
`
`C.  Statutory Grounds for Challenges ........................................................... 19 
`
`D.  The Grounds for Challenges are not Cumulative .................................... 20 
`
`E.  Level of Ordinary Skill ............................................................................ 21 
`
`V.  CLAIMS 1, 2, 4, AND 5 OF TAGO ARE UNPATENTABLE OVER
`THE PRIOR ART ............................................................................................ 22 
`
`ii
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`A.  Challenge # 1: Claims 1 and 4 are unpatentable as being obvious
`under 35 U.S.C. § 103 over Yamaguchi and Lin .................................... 22 
`
`1. 
`
`2. 
`
`Summary of Yamaguchi ................................................................. 22 
`
`Summary of Lin .............................................................................. 24 
`
`3.  Detailed Analysis of Claim 1 .......................................................... 24 
`
`4.  Detailed Analysis of Claim 4 .......................................................... 48 
`
`B.  Challenge # 2: Claims 2 and 5 are unpatentable as being obvious
`under 35 U.S.C. § 103 over Yamaguchi, Lin, and Bohr ......................... 52 
`
`5. 
`
`Summary of Bohr ............................................................................ 52 
`
`6.  Detailed Analysis of Claim 2 .......................................................... 53 
`
`7.  Detailed Analysis of Claim 5 .......................................................... 57 
`
`C.  Challenge #3: Claims 1 and 4 are unpatentable as being obvious
`under 35 U.S.C. § 103 over Yamaguchi and Lin (Alternative
`Position) ................................................................................................... 58 
`
`8.  Detailed Analysis of Claim 1 .......................................................... 58 
`
`9.  Detailed Analysis of Claim 4 .......................................................... 69 
`
`D.  Challenge #4: Claims 2 and 5 are unpatentable as being obvious
`under 35 U.S.C. § 103 over Yamaguchi, Lin, and Bohr (Alternative
`Position) ................................................................................................... 72 
`
`10.  Detailed Analysis of Claim 2 .......................................................... 73 
`
`11.  Detailed Analysis of Claim 5 .......................................................... 74 
`
`VI.  CONCLUSION ................................................................................................ 76 
`
`
`
`
`
`iii
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`PETITIONER'S EXHIBIT LIST
`
`February 1, 2016
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`
`
`U.S. Patent No. 7,525,189 to Tago
`
`Declaration of Dr. Jianmin Qu Under 37 C.F.R. § 1.68.
`
`Curriculum Vitae of Dr. Jianmin Qu.
`
`U.S. Patent Application Publication No. 2002/0180015 to
`Yamaguchi et al.
`
`U.S. Patent No. 5,258,648 to Lin
`
`U.S. Patent No. 6,617,681 to Bohr
`
`Dorf, The Electrical Engineering Handbook, Chapter 24, Surface
`Mount Technology (1993 CRC Press, Inc.), pp.603-615
`
`Note Regarding Page Citations
`For exhibits that include suitable page numbers as originally published,
`
`Petitioner's citations are to those original page numbers and not to the page
`
`numbers added for compliance with 37 CFR 42.63(d)(2)(ii).
`
`iv
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`I.
`
`INTRODUCTION
`Petitioner, Xilinx, Inc. ("Xilinx"), files this petition to institute inter partes
`
`review of claims 1, 2, 4, and 5 of U.S. Patent No. 7,525,189 to Tago. (Ex. 1001,
`
`"Tago") pursuant to 35 U.S.C. §§ 311-319. Tago, titled "Semiconductor Device,
`
`Wiring Board, and Manufacturing Method Thereof," was issued on April 28, 2009
`
`and claims priority back to May 21, 2004.
`
`II. MANDATORY NOTICES
`A. Real Party-In-Interest
`Petitioner and real party-in-interest is Xilinx, Inc. (“XILINX” or
`
`“Petitioner”).
`
`B. Related Matters
`Tago is involved in Xilinx, Inc. v. Godo Kaisha IP Bridge 1, Civ. No. 5:17-
`
`cv-00509 (N.D. Ca.). To the best knowledge of Petitioner, Tago is not involved in
`
`any other litigation matters or post-grant review proceedings.
`
`C. Lead and Back-up Counsel and Service Information
`Lead Counsel is Steven H. Slater (972-732-1001, sslater@slatermatsil.com,
`
`Reg. No. 35,361). Back-up Counsels are Roger C. Knapp (972-707-9022,
`
`rknapp@slatermatsil.com, Reg. No. 46,836) and Lizabeth Vice (972-707-9011,
`
`lvice@slatermatsil.com, Reg. No. 72,415). The address for all counsel is Slater
`
`Matsil, LLP, 17950 Preston Road, Suite 1000, Dallas, TX 75252.
`
`D. Grounds for Standing
`Petitioner certifies that Tago is available for inter partes review and that
`
`1
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`Petitioner is not barred or estopped from requesting inter partes review challenging
`
`the patent claims on the grounds identified in this petition.
`
`III. BACKGROUND AND INTRODUCTION TO THE PATENT AND
`
`PRIOR ART REFERENCES OF THE PRESENT PETITION
`
`
`
`A discussion of the technology background is provided below, followed by
`
`an introduction of the claimed subject matter of Tago as well as the prior art of the
`
`present petition. A more-detailed discussion of these items is also provided in the
`
`accompanying Declaration of Jianmin Qu (Exhibit 1002), ¶¶35-64.
`
`A. Technology Background
`
`
`
`Tago relates to a semiconductor chip mounted on a wiring board.
`
`Typically, semiconductor chips (e.g., a processor) are formed individually and
`
`then mounted on a printed circuit board (PCB), which serves to electrically
`
`connect the chip to other components (e.g., memory) of an electronic device (e.g.,
`
`a laptop). As the input/output (I/O) connections on a chip have decreased in size,
`
`intermediary wiring boards have been placed between the chip and the PCB to
`
`map the densely packed I/O terminals of the chip to larger I/O terminals of the
`
`PCB. The combination of the chip and the intermediary wiring board is referred
`
`to as a package. In some packages, multiple electronic components (e.g., different
`
`chips, capacitors, etc.), are mounted on a single intermediary wiring board to
`
`increase functionality. See, e.g., Ex. 1002, ¶39.
`
`2
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`
`
`Electronic devices experience fluctuations in temperature during operation.
`
`As recognized by Tago, packages may experience reliability and yield issues due
`
`to internal stresses of the package caused by differences in thermal properties of
`
`the chips, the intermediary wiring board, and the PCB. In particular, one thermal
`
`property that can create stress between the chips and the PCB is the amount that
`
`each of these structures expands when heated (i.e. their coefficients of thermal
`
`expansion). See, e.g., Ex. 1002, ¶40.
`
`
`
`The coefficient of thermal expansion (also referred to as heat expansion
`
`coefficient, linear expansion coefficient, etc., herein referred to as "CTE") is a
`
`physical property of a material and measures the linear expansion of the material
`
`per unit change in temperature. Because chips and PCBs are typically made of
`
`different materials, they have different CTEs. For example, the CTEs of PCBs are
`
`typically about five times larger than that of chips. Thus, PCBs expand more than
`
`chips when heated a same amount, which causes cracking at junction points
`
`between the PCBs and the chips. This is referred to as CTE mismatch. See, e.g.,
`
`Ex. 1002, ¶41.
`
`Prior to the filing of Tago, one known mechanism to address CTE mismatch
`
`was to use the intermediary wiring board to match the CTE of both the chip and
`
`the PCB. A first side of the intermediary wiring board was manufactured of a
`
`material having a CTE close to that of the chip, and a second side of the
`
`3
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
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`intermediary wiring board was manufactured of a material having a CTE close to
`
`that of the PCB. Thus, the intermediary wiring board could be used as a transition
`
`structure between different CTEs to relieve internal stress. See, e.g., Ex. 1002, ¶42.
`
`Tago's Background acknowledges this prior mechanism. A prior device is
`
`discussed where a plurality of chips are mounted on a communal wiring board that
`
`has a higher CTE than the plurality of chips. To reconcile CTE mismatch, the prior
`
`device mounted each chip on an individual small wiring board having a lower CTE
`
`than the communal wiring board. The plurality of small wiring boards were then
`
`mounted on the communal wiring board. See, e.g., Ex. 1002, ¶45.
`
`Using individual small wiring boards for each chip in a multi-chip package
`
`increases manufacturing difficulty and expense. The purported invention of Tago is
`
`to address this issue by using a single intermediary wiring board for all chips of a
`
`multi-chip package. See, e.g., Ex. 1002, ¶46.
`
`B. The Claimed Subject Matter of Tago
`
`Tago claims a wiring board on which multiple chips can be mounted. The
`
`wiring board includes a first wiring portion and a second wiring portion. The first
`
`wiring portion has a high CTE while the second wiring portion has a low CTE
`
`(e.g., close to a CTE of a chip mounted on the wiring board). Rather than having
`
`multiple low-CTE wiring boards in a multi-chip package, a single low-CTE wiring
`
`board (the second wiring portion) is used for multiple chips. Thus, Tago purports
`
`4
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`to reduce the expense of using multiple small wiring boards to relieve CTE
`
`mismatch. See, e.g., Ex. 1001, Abstract; Ex. 1002, ¶¶46-47. However, as will be
`
`described in detail below, this purported solution was well known prior to the
`
`filing of Tago.
`
`Claims 1, 2, 4, and 5 of Tago are challenged in this petition. Claims 1 and 4
`
`are representative of the claimed subject matter and are specifically directed to a
`
`wiring board having first and second wiring portions with different CTEs. Claims 2
`
`and 5 depend from claims 1 and 4, respectively, and further limit the wiring board
`
`to include a functional device.
`
`Annotated claim 1 is provided below, setting off claim elements with
`
`reference numerals and colored text. Throughout this petition, claim terms are
`
`presented in bold-italics.
`
`1. A semiconductor device characterized by comprising:
`[1.1a] a wiring board comprising a [1.1b] plurality of
`connecting terminals arranged on one surface in a direction of
`thickness and a [1.1c] plurality of external connecting bumps
`arranged on the other surface in the direction of thickness; and
`[1.2] at least one semiconductor chip connected to said
`connecting terminals,
`[1.3a] wherein said wiring board comprises:
`a first wiring portion comprising a plurality of wiring
`layers and said external connecting bumps; and
`[1.3b] a second wiring portion electrically connected to
`
`
`5
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`said first wiring portion and integrated with said first wiring
`portion in the direction of thickness,
`[1.4] said connecting terminals are made of contact plugs
`formed in through holes extending through the second wiring
`portion in the direction of thickness,
`[1.5] sizes of opposing surfaces of said first wiring portion and
`said second wiring portion are equal,
`[1.6a] a thermal expansion coefficient of said second wiring
`portion is smaller than a thermal expansion coefficient of said
`first wiring portion and [1.6b] equal to a thermal expansion
`coefficient of said semiconductor chip,
`[1.7] said semiconductor chip is a silicon chip,
`[1.8] said second wiring portion comprises a base made of
`silicon, and
`[1.9] said contact plugs are formed in said base.
`
`Figure 1, below, illustrates a wiring board 20 (element [1.1a]) comprising a
`
`first wiring portion 10 (element [1.3a]) and a second wiring portion 15 (element
`
`[1.3b]). The second wiring portion 15 is electrically connected to and integrated
`
`with the first wiring portion 10 in a direction of thickness (i.e., vertically stacked).
`
`See, e.g., Ex. 1001, Fig. 1 and 4:65-67 and 5:1; Ex. 1002, ¶49.
`
`6
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`
`
`Ex. 1001, Tago Figure 1, annotated
`
`As further illustrated by Figure 1, the first wiring portion 10 comprises a
`
`plurality of wiring layers 1, which may be used to electrically connect connecting
`
`terminals 14 (element [1.1b]) arranged on one surface of the wiring board 10 to a
`
`plurality of external connecting bumps 5 (element [1.1c]) arranged on another
`
`surface of the wiring board 20. See, e.g., Ex. 1001, Fig. 1 and 5:1-19. The
`
`connecting terminals 14 are made of contact plugs (also labeled 14, element [1.4])
`
`formed in through holes extending through the second wiring portion. The contact
`
`plugs 14 may or may not include lands (e.g., lands 14a) on one or both ends of
`
`contact plugs 14. See, e.g., Ex. 1001, 9:21-24; Ex. 1002, ¶50. Furthermore, the
`
`contact plugs 14 are formed in a base 12 of the second wiring portion 15 (element
`
`[1.9]). The claim phrase base is a way to describe a bulk material of the second
`
`wiring portion 15, which may be selected to reduce CTE mismatch in
`
`7
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`semiconductor device 50 (element [1.0]). See, e.g., Ex. 1001, 5:53-57; Ex. 1002,
`
`¶50.
`
`Figure 1 also illustrates a semiconductor chip 30 (element [1.2]) electrically
`
`connected to connecting terminals 14. Semiconductor chip 30 is a silicon chip
`
`(element [1.8]). See, e.g., Ex. 1001, 5:53. Although Figure 1 only illustrates a
`
`single semiconductor chip 30, Tago contemplates a multi-chip package having a
`
`plurality of chips and/or other devices (e.g., capacitors or resistors) mounted on the
`
`wiring board 20. See, e.g., Ex. 1001, 6:31-36, 7:1-2; 7:44-49, and Figs. 2-4; Ex.
`
`1002, ¶52.
`
`In order to mitigate CTE mismatch between the first wiring portion 10 and
`
`the semiconductor chip 30, a thermal expansion coefficient of the second wiring
`
`portion 15 is smaller than a thermal expansion coefficient of the first wiring
`
`portion 10 (claim element [1.6a]) and equal to a thermal expansion coefficient of
`
`the semiconductor chip 30 (claim element [1.6b]). In Tago, equal thermal
`
`expansion coefficients does not mean mathematical equality; rather, equal is
`
`defined as a difference in thermal expansion coefficients being within 10 ppm/ºC.
`
`See, e.g., Ex. 1001, 5:53-57; Ex. 1002, ¶53. In order to achieve the claimed CTE
`
`relationships, Tago discloses selecting silicon for base 12 of the second wiring
`
`portion 15 (element [1.8]) so that the thermal expansion coefficient of the second
`
`wiring portion 15 can be equal (i.e., within 10 ppm/ºC) to that of the silicon
`
`8
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`semiconductor chip 30. See, e.g., Ex. 1001, 5:53-57; Ex. 1002, ¶53.
`
`Tago further discloses that sizes of opposing surfaces of said first wiring
`
`portion 10 and said second wiring portion 15 are equal (element [1.5]). The claim
`
`terms sizes of opposing surfaces refers to the sizes planar areas of the first wiring
`
`portion 10 and the second wiring portion 15. Tago states the significance of this
`
`claimed relationship is so that a multi-chip package can be provided with only a
`
`single second wiring portion, as opposed to the prior art device described in Tago's
`
`Background that used multiple second wiring portions. See, e.g., Ex. 1001,
`
`Abstract and 2:4-14, 2:38-43, 3:61-67; Ex. 1002, ¶54.
`
`Furthermore, in Tago, equal sizes of opposing surfaces does not mean
`
`mathematical equality; rather, equal sizes of opposing surfaces means that the
`
`difference between the planar area of the second wiring portion 15 and that of the
`
`first wiring portion 10 is about 1,500 mm2 or less. See, e.g., Ex. 1001, 5:22-32; Ex.
`
`1002, ¶54. Thus, a POSITA would understand Tago is less concerned with actual
`
`dimensions of the second wiring portion 15 relative to the first wiring portion 10
`
`and more concerned with using the second wiring portion 15 to support multiple
`
`semiconductor chips. See, e.g., Ex. 1002, ¶54.
`
`As claimed in claim 4 and as depicted in Figure 4, Tago discusses a
`
`functional element 160 can be formed in the plurality of wiring layers 1 of the
`
`first wiring portion 10 or formed on a surface of the second wiring portion 15
`
`9
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`which faces the first wiring portion 10. See, e.g., Ex. 1001, 8:57-61 and Fig. 4.
`
`Examples of functional devices include capacitors, resistors, and inductors. See,
`
`e.g., Ex. 1001, 8:60-61.
`
`All of these elements were known in the art. Particularly, selecting specific
`
`materials for different portions of a wiring board in order to achieve specific CTE
`
`relationships between portions of the wiring board and components attached to the
`
`wiring board was a well-known mechanism for relieving thermal stress.
`
`Furthermore, the use of a single substrate (e.g., the second wiring portion) having
`
`a specific CTE to support a plurality of semiconductor devices was also well-
`
`known in the field of multi-chip packaging. See, e.g., Ex. 1002, ¶55.
`
`C. Brief Introduction to the Prior Art of the Present Petition
`
`There are two primary references in the present petition, which render the
`
`challenged claims 1 and 4 unpatentable: U.S. Patent Application Publication No.
`
`2002/0180015 to Yamaguchi et al. (“Yamaguchi,” Ex. 1004) and U.S. Patent No.
`
`5,258,648 to Lin ("Lin," Ex. 1005). An annotated version of Fig. 1 of Yamaguchi
`
`is shown below along with annotated Fig. 1 of Tago, again using the same color
`
`scheme and reference numerals for claim 1 of Tago.
`
`10
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`Ex. 1004, Yamaguchi Figure 1, annotated
`
`
`
`As illustrated above, and similar to Tago, Yamaguchi teaches a single
`
`substrate 1 (equivalent to the second wiring portion) having a particular CTE and
`
`supporting multiple semiconductor chips (e.g., semiconductor chips 9). See, e.g.,
`
`Ex. 1004, [0058], [0101]-[0106], and Figs. 1 and 2; Ex. 1002, ¶60. Importantly,
`
`Yamaguchi in view of Lin shows the specific configuration of the first wiring
`
`portion and the second wiring portion, as recited in claims 1 and 4:
`
`[1.5] sizes of opposing surfaces of said first wiring portion and said
`second wiring portion are equal,
`[1.6a] a thermal expansion coefficient of said second wiring portion
`is smaller than a thermal expansion coefficient of said first
`wiring portion and [1.6b] equal to a thermal expansion
`coefficient of said semiconductor chip,
`
`The other primary reference, Lin, discloses a device that is analogous to the
`
`11
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`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`device of Yamaguchi and provides additional details regarding matching CTEs
`
`between a first wiring portion, a second wiring portion, and a semiconductor chip.
`
`See, e.g., Ex. 1005, 4:36-68, 6:28-60; Ex. 1002, ¶62.
`
`The present petition includes one secondary reference, U.S. Patent No.
`
`6,617,681 to Bohr (“Bohr,” Ex. 1006). This reference further supplements the
`
`primary references, Yamaguchi and Lin, and provides a functional device required
`
`by claims 2 and 5. See, e.g., Ex. 1006, 5:61-65, Fig. 5, 6:27-47, and 4:21-28; Ex.
`
`1002, ¶64.
`
`IV. STATEMENT OF PRECISE RELIEF REQUESTED
`
`A. Claim for Which Review is Requested
`
`Petitioner requests review under 35 U.S.C. § 311 of claims 1, 2, 4, and 5 of
`
`Tago, and cancellation of those claims as unpatentable. Claims 1, 2, 4, and 5 of
`
`Tago are challenged herein.
`
`B. Claim Construction
`
`Claim terms in inter partes review are given their "broadest reasonable
`
`constructions in light of the specification." 37 CFR §42.100(b). Any claim term
`
`that lacks a definition in the specification is therefore given a broad interpretation.
`
`For purposes of this proceeding, unless otherwise noted, claim terms have their
`
`plain and ordinary meaning as understood by one of skill in the art in view of the
`
`specification. Petitioner reserves the right to advocate a different claim
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`12
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`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`interpretation in other forums that apply a different standard.
`
`1. contact plug (claims 1 and 4):
`Claims 1 and 4 of Tago recite connecting terminals that are made of contact
`
`plugs formed in through holes extending through the second wiring portion. Tago
`
`uses the terms contact plugs formed in through holes to mean a conductive
`
`material formed in through holes. See, e.g., Ex. 1001, 11:43-48, 9:38-39, 5:17-18,
`
`and Fig. 1; Ex. 1002, ¶29. In addition to portions of the contact plugs that are
`
`formed in through holes, Tago makes clear that a contact plug may or may not
`
`have a land portion at one or both ends in a longitudinal direction. See, e.g., Ex.
`
`1001, 9:21-24; Ex. 1002, ¶29. Therefore, Petitioner proposes that contact plugs
`
`means a conductive material, and the contact plugs may or may not have land
`
`portion(s) on one or both ends. See, e.g., Ex. 1002, ¶29.
`
`2. one surface in a direction of thickness (claim 1)
`Claim 1 of Tago recites a plurality of connecting terminals arranged on one
`
`surface in a direction of thickness and a plurality of external connecting bumps
`
`arranged on the other surface in the direction of thickness. Claim 1 further recites
`
`that the connecting terminals are made of contact plugs formed in through holes
`
`extending through the second wiring portion in the direction of thickness.
`
`Referring to the specification, Tago describes that the external connecting bumps 5
`
`depicted in Figure 1 are formed on one surface in the direction of thickness, and
`
`13
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`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
`
`Figure 1 depicts the external connecting bumps 5 being positioned along a major
`
`surface of the wiring board 10. See, e.g., Ex. 1001, 5:5-8; Ex. 1002, ¶30.
`
`Ex. 1001, Tago Fig. 1, annotated
`
`
`
`Figure 1 also depicts the connecting terminals 14 being exposed along an
`
`opposing major surface of the wiring board 10, and extending through the second
`
`wiring portion 15 in a direction that is perpendicular to the surfaces along which
`
`the connecting terminals 14 and the external connecting bumps 5 are positioned.
`
`Other figures depict similar configurations. See, e.g., Ex. 1001, Figs. 2-4; Ex.
`
`1002, ¶30. There is an ambiguity to the terms direction of thickness as recited in
`
`claim 1, because under the plain language, the direction of thickness refers to two
`
`perpendicular directions: (1) a direction parallel to the major surfaces of the wiring
`
`boards along which the connecting terminals and the external connecting bumps
`
`are respectively positioned; and (2) the direction along which each of the
`
`connecting terminals extend through the second wiring portion. See, e.g., Ex. 1002,
`
`¶30. The direction of thickness is also used in Tago's specification to explain that
`
`14
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
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`the second wiring portion 15 is "integrated with the first wiring portion 10 in the
`
`direction of thickness (i.e. stacked on the first wiring portion 10)," which, as
`
`shown in annotated Figure 1 above, indicates that the direction of thickness
`
`extends in the direction along which the connecting terminals extend through the
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`second wiring portion. Ex. 1001, 4:65-5:1 (emphasis added); see also, Ex. 1002,
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`¶30. Thus, Petitioner proposes that the terms direction of thickness to be the
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`direction along which the connecting terminals extend through the second wiring
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`portion, which is perpendicular to the surfaces on which the plurality of connectors
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`and the connecting terminals are respectively positioned. Furthermore, to reconcile
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`the ambiguity as much as possible, Petitioner proposes a surface in the direction
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`of thickness to be a surface in a plane perpendicular to the direction of thickness
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`and that passes through a line extending in the direction of thickness. See, e.g., Ex.
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`1002, ¶30.
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`3. connected to (claim 1):
`Claim 1 of Tago recites at least one semiconductor chip connected to said
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`connecting terminals. Tago uses the term connect to refer to both physical and
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`electrical connections, and in a manner that includes both direct connections and
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`indirect connections. See, e.g., Ex. 1001, 5:36-38 and 13:1-3; Ex. 1002, ¶31. At
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`times when Tago refers to a specific type of connection, for example an electrical
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`connection, Tago specifies the type of connection that is being described. For
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`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
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`example, claim 1 recites "a second wiring portion electrically connected to said
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`first wiring portion." Ex. 1001, 14:60-62 (emphasis added); see also, Ex. 1002,
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`¶31. Because claim 1 recites "at least one semiconductor chip connected to said
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`connecting terminals," without specifying the type of connection, the connection
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`referred to could be any one of the types of connections contemplated by the
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`disclosure of Tago, such as an electrical connection, a physical connection, or both.
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`Further, Tago uses the term connected to refer to direct connections and indirect
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`connections. For example, the Specification states, referring to Figure 2, that "each
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`electrode terminal 75 formed in the second semiconductor chip 80 directly
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`connects to a predetermined contact plug 64," which is an example of a reference
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`in Tago to a direct physical connection between the electrodes 75 and the contact
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`plugs 64. Ex. 1001, 6:60-62 (emphasis added); see also, Ex. 1002, ¶31. As another
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`example, the Specification states, referring to Figure 2, that "each electrode
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`terminal 95 formed in the passive part 100 connects to a predetermined contact
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`plug 64 via a solder bump 105." Ex. 1001, 7:2-4 (emphasis added); see also, Ex.
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`1002, ¶31. As can be seen from Figure 2, the connection referred to between
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`electrode terminals 95 and contact plugs 64 are indirect connections that depend on
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`intervening solder bumps 105. Therefore, in light of the broadest reasonable
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`interpretation standard used in IPR proceedings, Petitioner propose that the terms
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`connected to means a physical connection, an electrical connection, or both, and
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`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
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`that the connection may be a direct connection or an indirect connection. See, e.g.,
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`Ex. 1002, ¶31.
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`4. integrated with (claims 1 and 4):
`Claims 1 and 4 of Tago recite a second portion electrically connected to said
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`first wiring portion and integrated with said first wiring portion in the direction of
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`thickness. Tago defines that terms integrated with as meaning “stacked.” See, e.g.,
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`Ex. 1002, ¶32. For example, Tago states that the second wiring portion 15 is
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`"integrated with the first wiring portion 10 in the direction of thickness (i.e.
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`stacked on the first wiring portion 10)." Ex. 1001, 4:65-5:1 (emphasis added); see
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`also, Ex. 1002, ¶32. Tago further describes that the second wiring portion may be
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`integrated with the first wiring portion by (1) forming the first wiring portion
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`directly on the base of the second wiring portion or by (2) separately forming the
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`first and second wiring portions and then bonding them together. See, e.g., Ex.
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`1001, 8:34-52; Ex. 1002, ¶32. In each of these examples, the second wiring portion
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`is stacked on the first wiring portion. As such, Petitioner proposes that the terms
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`integrated with in the direction of thickness means stacked. See, e.g., Ex. 1002,
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`¶32.
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`5. sizes of opposing surfaces of said first wiring portion and said
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`second wiring portion are equal (claims 1 and 4):
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`Claims 1 and 4 of Tago recite sizes of opposing surfaces of said first wiring
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`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
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`portion and said second wiring portion are equal. Tago provides a specific
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`definition for this limitation. In particular, Tago states "[the] planar size of the
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`second wiring portion 15 is equal to that of the first wiring portion 10. That is, the
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`sizes of opposing surfaces of the first wiring portion 10 and the second wiring
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`portion 15 are equal. 'The planar size of the second wiring portion 15 is equal to
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`that of the first wiring portion 10' means that the difference between the planar area
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`of the second wiring portion 15 and that of the first wiring portion 10, i.e., the
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`difference between the areas of the opposing surfaces of the second wiring portion
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`15 and first wiring portion 10 is about 1,500 mm2 or less." Ex. 1001, 5:22-33; see
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`also, Ex. 1002, ¶33. As such, Petitioner proposes sizes of opposing surfaces of
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`said first wiring portion and said second wiring portion are equal means a
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`difference in a planar area of the first wiring portion and a planar area of the
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`second wiring portion is 1,500 mm2 or less. See, e.g., Ex. 1002, ¶33.
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`6. a thermal expansion coefficient of said second wiring portion is
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`equal to a thermal expansion coefficient of said semiconductor chip
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`(claims 1 and 4)
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`Claims 1 and 4 recite a thermal expansion coefficient of said second wiring
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`portion is equal to a thermal expansion coefficient of said semiconductor chip.
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`Tago states, "'the thermal expansion coefficient of the second wiring portion 15 is
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`equal to that of the semiconductor chip 30' means that the difference between the
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`Petition for Inter Partes Review of U.S. Patent No. 7,525,189
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`thermal expansion coefficient of the whole second wiring portion 15 and that of the
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`whole semiconductor chip 30 is about 10 ppm/ºC. or less." Ex. 1001, 5:64-67
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`(emphasis added). Given this specific definition provided by Tago, Petitioner
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`proposes a thermal expansion coefficient of said second wiring portion is equal
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`to a thermal expansion coefficient of said semiconductor chip means a difference
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`between the thermal expansion coefficient of the whole second wiring portion and
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`the thermal expansion coefficient of the whole first wiring portion is 10 ppm/ºC or
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`less. See, e.g., Ex. 1002, ¶34.
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`C. Statutory Grounds for Challenges
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`A petition for inter partes review must demonstrate "a reasonable likelihood
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`that Petitioner would prevail with respect to at least one of the claims challenged in
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`the petition." 35 U.S.C. §314(a).The Petition meets this threshold. Each of the
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`elements of claims 1,