UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`
`
`Xilinx, Inc.
`Petitioner
`
`
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 6,653,731
`
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`TABLE OF CONTENTS
`
`PETITIONER’S EXHIBIT LIST .............................................................................. v 
`
`Note Regarding Page Citations .......................................................................... v 
`
`I. 
`
`INTRODUCTION ............................................................................................. 1 
`
`II.  MANDATORY NOTICES ............................................................................... 1 
`
`A.  Real party-in-interest ................................................................................. 1 
`
`B.  Related matters .......................................................................................... 1 
`
`C.  Lead and back-up counsel and service information .................................. 1 
`
`D.  Grounds for standing ................................................................................. 2 
`
`III.  BACKGROUND AND INTRODUCTION TO THE PATENT AND
`PRIOR ART REFERENCES OF THE PRESENT PETITION ........................ 2 
`
`A.  Background of the Technology ................................................................. 2 
`
`B.  The Claimed Subject Matter of the `731 Patent ........................................ 5 
`
`C.  Brief Introduction to the Prior Art of the Present Petition ...................... 12 
`
`1.  Yoshikazu ........................................................................................ 13 
`
`2.  Ohta ................................................................................................. 18 
`
`3.  Lau ................................................................................................... 21 
`
`IV.  STATEMENT OF PRECISE RELIEF REQUESTED ................................... 22 
`
`A.  Claim for Which Review is Requested ................................................... 22 
`
`B.  Claim Construction .................................................................................. 23 
`
`1. 
`
`2. 
`
`“bare chip” ...................................................................................... 23 
`
`“active surface” ............................................................................... 24 
`
`ii
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`3. 
`
`“wherein a sum of a thickness of each of said protective
`members and a width of said bare chip is more than 100 µm” ....... 25 
`
`C.  Statutory grounds for challenges ............................................................. 28 
`
`D.  The grounds for challenges are not cumulative ...................................... 30 
`
`E.  Level of ordinary skill ............................................................................. 33 
`
`V.  CLAIM 5 OF THE `731 PATENT IS UNPATENTABLE OVER THE
`PRIOR ART ..................................................................................................... 33 
`
`A.  Challenge # 1: Claim 5 is unpatentable under 35 U.S.C. §102(a) as
`being anticipated by U.S. Pat. No. 5,989,982 to Yoshikazu
`(“Yoshikazu,” Ex. 1005). ........................................................................ 34 
`
`1. 
`
`Summary of Yoshikazu ................................................................... 34 
`
`2.  Detailed Analysis of Claim 5 .......................................................... 36 
`
`B.  Challenge #2: Claim 5 is unpatentable under 35 U.S.C. §103 as
`being obvious over Yoshikazu (Ex. 1005) in view of US Pat. No.
`6,228,688 to Ohta et al. (“Ohta,” Ex. 1006). ........................................... 44 
`
`1. 
`
`2. 
`
`Summary of Yoshikazu ................................................................... 44 
`
`Summary of Ohta ............................................................................ 44 
`
`3.  Detailed Analysis of Claim 5 .......................................................... 46 
`
`4.  Motivation to Combine Yoshikazu and Ohta ................................. 55 
`
`C.  Challenge # 3: Claim 5 is unpatentable as being anticipated under 35
`U.S.C. §102 by US Pat. No. 6,228,688 to Ohta et al. (“Ohta,” Ex.
`1006). ....................................................................................................... 56 
`
`1. 
`
`Summary of Ohta ............................................................................ 56 
`
`2.  Detailed Analysis of Claim 5 .......................................................... 56 
`
`D.  Challenge #4: Claim 5 is unpatentable as being anticipated under 35
`U.S.C. §102 by the textbook Flip Chip Technologies, ed. John H.
`
`iii
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`Lau, McGraw-Hill, 1996. (“Lau,” Ex. 1007) .......................................... 66 
`
`1. 
`
`Summary of Lau .............................................................................. 66 
`
`2.  Detailed Analysis of Claim 5 .......................................................... 67 
`
`VI.  CONCLUSION ................................................................................................ 77 
`
`
`
`
`
`iv
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`PETITIONER’S EXHIBIT LIST
`
`February 1, 2017
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`
`
`U.S. Patent No. 6,653,731 to Kato et al.
`
`Prosecution File History of U.S. Patent No. 6,653,731.
`
`Declaration of Mr. Peter Elenius Under 37 C.F.R. § 1.68.
`
`Curriculum Vitae of Mr. Peter Elenius.
`
`U.S. Patent No. 5,989,982 to Yoshikazu.
`
`U.S. Patent No. 6,228,688 to Ohta et al.
`
`Selected Portions from Flip Chip Technologies (John H. Lau ed.,
`McGraw-Hill 1996)
`
`Note Regarding Page Citations
`For exhibits that include suitable page numbers as originally published,
`
`Petitioner’s citations are to those original page numbers and not to the page
`
`numbers added for compliance with 37 CFR 42.63(d)(2)(ii).
`
`v
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`I.
`
`INTRODUCTION
`Petitioner, Xilinx, Inc. (“Xilinx”), files this petition to institute inter partes
`
`review of claim 5 of U.S. Patent No. 6,653,731 to Kato et al. (Ex. 1001, “the `731
`
`Patent”) pursuant to 35 U.S.C. §§ 311-319. The `731 Patent, titled
`
`“Semiconductor Device and Method for Fabricating Same” was issued on
`
`November 25, 2003, with a priority claim dating back to February 28, 2000.
`
`
`
`II. MANDATORY NOTICES
`A. Real party-in-interest
`The petitioner and real party-in-interest is Xilinx, Inc. (“Xilinx” or
`
`“Petitioner”).
`
`B. Related matters
`The `731 Patent is involved in Xilinx, Inc. v. Godo Kaisha IP Bridge 1, Civ.
`
`No. 5:17-cv-00509 (N.D. Cal.). To the best knowledge of Petitioner, the `731
`
`Patent is not involved in any other litigation matters or post-grant review
`
`proceedings.
`
`C. Lead and back-up counsel and service information
`Lead Counsel is Steven H. Slater (972-707-9004, sslater@slatermatsil.com,
`
`Reg. No. 35,361). Back-up Counsels are Roger C. Knapp (972-707-9022,
`
`rknapp@slatermatsil.com, Reg. No. 46,836) and Brian A. Mair (972-707-9009,
`
`bmair@slatermatsil.com, Reg. No. 58,233). The address for all counsel is Slater
`
`1
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`Matsil, LLP, 17950 Preston Road, Suite 1000, Dallas, TX 75252.
`
`D. Grounds for standing
`Petitioner certifies that the `731 Patent is available for inter partes review
`
`and that Petitioner is not barred or estopped from requesting inter partes review
`
`challenging the patent claims on the grounds identified in this petition.
`
`
`
`III.
`
`BACKGROUND AND INTRODUCTION TO THE PATENT AND
`PRIOR ART REFERENCES OF THE PRESENT PETITION
`
`A discussion of the technology background is provided below, followed by a
`
`brief introduction of the claimed subject matter of the `731 Patent as well as the
`
`prior art of the present petition. A more-detailed discussion of these items is also
`
`provided in the attached Declaration of Peter Elenius (“Elenius Decl.,” Exhibit
`
`1003), at ¶¶ 31-61 and 70-86.
`
`A. Background of the Technology
`The `731 Patent is directed to a semiconductor device in which a bare chip is
`
`
`
`coated with protective resin to prevent it from being cracked during transportation
`
`and handling. See, e.g., Ex. 1003 ¶ 43. Generally, the process of forming
`
`semiconductor integrated circuits (ICs) starts with a semiconductor wafer, and
`
`electronic devices, e.g., transistors, capacitors, resistors, etc., are formed on the
`
`silicon wafer, with metallization layers formed over the electronic devices in order
`
`to interconnect the electronic devices to form integrated circuits. See, e.g., Ex.
`
`2
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`1003 ¶ 33. Many integrated circuits or dies may be formed on a single wafer,
`
`where each die may be one device, such as a processor, memory, etc. After
`
`forming the individual integrated circuits, the wafer is then diced, singulated, or
`
`separated in order to separate the individual dies. See, e.g., Ex. 1003 ¶ 34.
`
`
`
`However, the individual dies need to be connected to other, external devices
`
`through a connection such as a flip-chip type of connection. See, e.g., Ex. 1003 ¶
`
`35. In such a connection the individual semiconductor die is mounted or bonded to
`
`another substrate, such as a package substrate, with an interconnect material such
`
`as a bump, wherein the die is “flipped” such that the surface of the semiconductor
`
`die that has the interconnect material on it faces the other substrate or device. See,
`
`e.g., Ex. 1003 ¶ 35. As such, the interconnect material is between the individual
`
`semiconductor die and the other substrate. See, e.g., Ex. 1003 ¶ 35.
`
`
`
`As recognized by the `731 Patent, after the wafer is separated and the
`
`individual dies have been obtained, the separated individual dies, referred to in the
`
``731 Patent as bare chips, are relatively fragile. See, e.g., Ex. 1001, 1:62-2:7; see
`
`also, Ex. 1003 ¶ 36. Further, in order to perform additional processing, such as
`
`mounting to the packaging substrate, the individuated semiconductor dies may be
`
`placed in a tray for transportation to and from the additional processing, which
`
`leads to the possibility that, as the tray is being moved, shocks may impact the bare
`
`chip. See, e.g., Ex. 1003 ¶ 36. Accordingly, the edges of the bare chip are prone to
`
`3
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`being damaged, which leads to a deterioration of the yield rate of the products
`
`and/or the quality of the transported semiconductor devices. See, e.g., Ex. 1003 ¶
`
`36.
`
`
`
`Prior to the filing of the `731 Patent, there had been significant innovation in
`
`the protection of the sides of bare chips using protective resins. See, e.g., Ex. 1003
`
`¶ 37. For example, one prior approach is to inject a resin into the spaces located
`
`between the individual dies after singulation. See, e.g., Ex. 1003 ¶ 76. The resin-
`
`coated dies are then singulated again, this time forming individual dies with a
`
`protective resin located on the side walls. See, e.g., Ex. 1003 ¶ 37.
`
`
`
`Another prior approach protects the sides of bare chips by encapsulation,
`
`wherein a protective material (or encapsulant) is placed around sides of the bare
`
`chip in order to seal and protect the bare chips. See, e.g., Ex. 1003 ¶ 38. In still yet
`
`another previously known method, a material known as an underfill is applied to
`
`the bare chip after the bare chip has been connected or bonded to another substrate,
`
`and the underfill, through capillary action, is pulled between the bare chip and the
`
`underlying substrate, and fillets are likewise formed on sidewalls of the bare chip.
`
`See, e.g., Ex. 1003 ¶¶ 39-40. A subsequent curing process solidifies and hardens
`
`the flowable protective material and protects the bare die. See, e.g., Ex. 1003 ¶ 39.
`
`
`
`Using any of these methods, by protecting the sides of the bare chips with
`
`the protective resins, more rugged devices able to withstand significant impacts
`
`4
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`were manufactured and patented prior to the filing of the `731 Patent. See, e.g.,
`
`Ex. 1003 ¶ 41.
`
`
`
`
`
`B.
`The Claimed Subject Matter of the `731 Patent
`The `731 Patent is directed to a semiconductor device in which a bare chip is
`
`coated with a protective resin to prevent it from being cracked. See, e.g., Ex.
`
`1001, 1:7-10; see also, Ex. 1003 ¶ 43. Claim 5 of the `731 Patent is challenged in
`
`this petition, and is specifically directed to a semiconductor device with protective
`
`members formed on side surfaces.
`
`For ease of reference, we have provided an annotated claim 5, setting off
`
`claim elements with reference numerals and colored text. See, e.g., Ex. 1001,
`
`12:56-64; see also, Ex. 1003 ¶ 48. Also throughout the remainder of this petition,
`
`claim terms are presented in bold-italics.
`
`5. A semiconductor device, comprising:
`[1.1] a bare chip;
`[1.2a] plural bumps [1.2b] provided on an active surface of said
`bare chip;
`[1.3a] protective members formed on side surfaces of said bare
`chip [1.3b] to surround a periphery of said bare chip, [1.3c]
`wherein a sum of a thickness of each of said protective members
`and a width of said bare chip is more than 100 µm.
`
`5
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`
`
`To further illustrate the elements of claim 5, we have additionally annotated
`
`Fig. 4C, which is one of the exemplary embodiments of the `731 Patent. See, e.g.,
`
`Ex. 1003 ¶ 49. Each of the claim elements is identified using the same reference
`
`color scheme from claim 5 above. See, e.g., Ex. 1003 ¶ 49.
`
`
`
`Ex. 1001, `731 Patent, Fig. 4C, annotated
`
`As can be seen, Fig. 4C of the `731 Patent shows an LSI chip 1 which is also
`
`referred to as a bare chip (bare chip claim element [1.1]). See, e.g., Ex. 1001,
`
`4:26-28; see also, Ex. 1003 ¶ 50. A plurality of LSI electrodes 2 are formed on a
`
`surface of the LSI chip 1 (bare chip), and a plurality of bumps 3 (claim element
`
`plural bumps [1.2a]) is mounted on the plurality of the LSI electrodes 2. See, e.g.,
`
`Ex. 1001, 4:28-32; see also, Ex. 1003 ¶ 51.
`
`Figure 4C additionally illustrates protective resin 4 (claim element protective
`
`members [1.3a]), which is also described as an epoxy resin. See, e.g., Ex. 1001,
`
`6
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`4:35-36; see also, Ex. 1003 ¶ 52. The `731 Patent also states that “[e]ach side
`
`surface of the LSI chip 1 is coated with protective resin 4” and “since the side
`
`surfaces of the LSI chip 1 is protected by protective resin 4, the LSI chip 1 is
`
`prevented from being chipped off or cracked.” Ex. 1001, 4:49-51 and 4:33-35,
`
`respectively.
`
`
`
`In another disclosed embodiment, the protective resin 4 (protective
`
`members) is also formed on the backside of the LSI chip 1 (bare chip), as
`
`illustrated in Figure 4D of the `731 Patent, which has been reproduced and
`
`annotated below. See, e.g., Ex. 1001, 9:2-6; see also, Ex. 1003 ¶ 53.
`
`
`
`Ex. 1001, `731 Patent, Fig. 4D, annotated
`
`
`
`The `731 Patent also discusses a “permissible width of the semiconductor
`
`device shown in FIG. 4A,” and defines the permissible width of the semiconductor
`
`device as a sum of a width of a crack permissible area of the semiconductor die
`
`and the thickness of the protective resin. See e.g., Ex. 1001, 10:39-40 and 10:36-
`
`7
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`37, respectively; see also, Ex. 1003 ¶ 54. Figure 1 (reproduced below) illustrates
`
`the “crack permissible area” of an LSI chip, and Figure 12 (reproduced below) of
`
`the `731 Patent provides data on a relationship between permissible widths and
`
`defect rates. See, e.g., Ex. 1003 ¶ 54. Figure 4D (reproduced above) does not
`
`specifically identify the thickness of the epoxy resin 4, but the figure shows clearly
`
`that the protective resin 4 has a thickness.
`
`Ex. 1001, `731 Patent, Figure 1
`
`
`
`8
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`Ex. 1001, `731 Patent, Figure 12
`
`
`
`
`
`However, all of these elements were known in the art prior to the filing of
`
`the `731 Patent. See, e.g., Ex. 1003 ¶ 55. In particular, protective members placed
`
`to protect a periphery of a bare chip, wherein a sum of a thickness of the protective
`
`members and the width of the bare chip is greater than 100 µm were common
`
`features. See, e.g., Ex. 1003 ¶ 55. Prior art publications that were before the
`
`Examiner as well as prior art publications that were not before the Examiner
`
`described the exact configurations recited in claim 5 such that the protective
`
`members are formed on the side surfaces of said bare chip to surround the
`
`9
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`

`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`periphery of said bare chip along with the remainder of the claim elements. See,
`
`e.g., Ex. 1003 ¶ 55.
`
`
`
`In particular, the `731 Patent issued from U.S. Patent Application
`
`09/784,490, which was filed on Feb. 15, 2001 and claimed priority to Japanese
`
`Patent Application 2000-051873, filed Feb. 28, 2000. See generally, Ex. 1001; see
`
`also, Ex. 1003 ¶ 56. A copy of the file history of the application which issued as
`
`the `731 Patent is attached to this Petition as Exhibit 1002. See generally, Ex.
`
`1002; see also, e.g., Ex. 1003 ¶ 56.
`
`
`
`During prosecution, the pending claims were repeatedly rejected in
`
`successive office actions under 35 U.S.C. §102(e) as being anticipated by U.S. Pat.
`
`No. 6,204,564 issued to Miyata et al. See, e.g., Ex. 1002, pp. 110-111 and 125-
`
`126; see also, Ex. 1003 ¶ 57. Additionally, claims 1-5 were rejected under 35
`
`U.S.C. § 102(e) as being anticipated by U.S. Pat. No. 6,150,194 issued to
`
`Sakaguchi. See, e.g., Ex. 1002, pp. 110-111 and 125-126; see also, Ex. 1003 ¶ 57.
`
`To overcome these rejections, the applicant significantly narrowed claim 1 to recite
`
`two additional elements, namely (a) “protective members formed on side surface
`
`and on said active surface of said bare chip between said plural bumps” and (2) “a
`
`sum of a thickness of the protective members on the side surfaces and a width of
`
`the bare chip is more than 100 µm” along with other claim amendments. Ex. 1002,
`
`pp. 134 and 131, respectively; see also, Ex. 1003 ¶ 58. Notably, the applicant
`
`10
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`

`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`substantively discussed only newly added claim element (1) and did not
`
`substantively discuss newly added claim element (2) or the other claim
`
`amendments. See, e.g., Ex. 1002, pp. 131 and 134; see also, Ex. 1003 ¶ 58. In the
`
`same response the applicant also added new independent claim 6 (later renumbered
`
`as claim 23), which became the claim 5 in the `731 Patent (referred to as claim
`
`6/23 hereafter when discussing the application phase prior to issuance of claim 5).
`
`See, e.g., Ex. 1002, p. 131; see also, Ex. 1003 ¶ 58. This claim only recites one of
`
`the multiple amendments that the applicant added to get claim 1 allowed (“a sum
`
`of a thickness of the protective members on the side surfaces and a width of the
`
`bare chip is more than 100 µm”) but there was no substantive discussion of claim
`
`6/23 by either the applicant or the examiner. See, e.g., Ex. 1002, p. 131; see also,
`
`Ex. 1003 ¶ 58. More importantly claim 6/23 (now claim 5) does not include the
`
`other amendments relied on most heavily to overcome the prior art references,
`
`specifically “protective members...between said plural bumps.” See, e.g., Ex.
`
`1002, p. 133; see also, Ex. 1003 ¶ 58. The applicant did not address the new claim
`
`substantively, rather stating without elaboration that “[n]ew claim 6 has been
`
`added to more fully cover the scope of the present invention” and “[c]onsideration
`
`and allowance of claim 6 is respectfully and earnestly solicited.” See, e.g., Ex.
`
`1002, p. 131; see also, Ex. 1003 ¶ 59.
`
`11
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`
`
`Significantly, the examiner appears to have mistakenly believed that all of
`
`the newly added limitations of amended claim 1 were also recited in claim 6/23.
`
`See, e.g., Ex. 1002, pp. 139-140; see also, Ex. 1003 ¶ 60. In particular, the
`
`Reasons for Allowance for claims 1, 3-5 and also for the newly added claim 6/23
`
`(now claim 5) identify as the basis for allowance each and every element of
`
`amended claim 1, including those elements that were not recited in the newly
`
`added claim 6/23. See, e.g., Ex. 1002, pp. 139-140; see also, Ex. 1003 ¶ 60.
`
`
`
`If, as the Reasons for Allowance suggest, the examiner believed claim 6/23
`
`included all the limitations of claim 1, this would explain why claim 6/23 issued as
`
`claim 5 over Yoshikazu even though Yoshikazu discloses each element of claim 5,
`
`as detailed below.1 See, e.g., Ex. 1003 ¶ 61.
`
`
`
`C. Brief Introduction to the Prior Art of the Present Petition
`There are three primary references in the present petition, each of which
`
`renders the challenged claim unpatentable: U.S. Pat. No. 5,989,982 to Yoshikazu
`
`(“Yoshikazu,” Ex. 1005), U.S. Pat. No. 6,228,688 to Ohta et al. (“Ohta,” Ex.
`
`1006), and the textbook Flip Chip Technologies (John H. Lau ed., McGraw-Hill
`
`
`1 Petitioner takes no position in this Petition on whether claim 1 should have issued
`
`over Yoshikazu, and Petitioner reserves the right to challenge claim 1 as being
`
`anticipated by and/or unpatentable over Yoshikazu in subsequent proceedings.
`
`12
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`1996) (“Lau,” Ex. 1007). Each of these references is discussed briefly in the
`
`following sections.
`
`
`
`1.
`Yoshikazu
`Yoshikazu was issued on November 23, 1999. Yoshikazu was filed in the
`
`United States on November 10, 1997 and claims priority to a Japanese patent
`
`application (JP 9-275964) filed October 8, 1997. See generally, Ex. 1005; see
`
`also, Ex. 1003 ¶ 70. Hence, Yoshikazu is prior art to the `731 Patent under at least
`
`35 U.S.C. § 102(e) (Pre-AIA). See, e.g., Ex. 1003 ¶ 70. Yoshikazu is titled
`
`“Semiconductor Device and Method of Manufacturing the Same.” See, e.g., Ex.
`
`1003 ¶ 70.
`
`Yoshikazu describes a structure and method that is almost identical to the
`
`disclosed embodiments of the `731 Patent. See generally, Ex. 1003 ¶¶ 71-79.
`
`Yoshikazu’s package is shown below in a comparison of Figure 4C of the `731
`
`Patent and Yoshikazu’s Figure 1, with each figure being annotated to illustrate the
`
`similar structures. See, e.g., Ex. 1003 ¶ 71.
`
`13
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
`
`Ex. 1001, `731 Patent, Fig. 4C
` (annotated)
`
`
`
`
`
`
`
` Ex. 1005, Yoshikazu, Fig. 1
`
` (annotated)
`
`Yoshikazu teaches all of the elements of claim 5 of the `731 Patent. See,
`
`
`
`
`
`
`e.g., Ex. 1003 ¶ 72. The semiconductor package includes a bare chip (LSI chip 1),
`
`upon which are provided plural bumps (solder balls 4). See, e.g., Ex. 1005, Figure
`
`1; see also, Ex. 1003 ¶ 72. Protective members (epoxy resin 3) cover the surface
`
`and sides of the bare chip (LSI chip 1) and provide protection. See, e.g., Ex. 1005,
`
`Figure 1; see also, Ex. 1003 ¶ 72. Finally, the diameter of the plural bumps
`
`(solder balls 4) is expressly described as being 300 µm to 500 µm, and Yoshikazu
`
`teaches multiple plural bumps (solder balls 4) fit on the bare chip (LSI chip 1).
`
`See, e.g., Ex. 1005, 2:32-37 and Figure 1; see also, Ex. 1003 ¶ 72. As such, the
`
`bare chip (LSI chip 1), by itself, is larger than 100 µm and therefore the sum of the
`
`width of the bare chip (LSI chip 1) and the protective members (epoxy resin 3),
`
`regardless of the thickness of the protective members (epoxy resin 3), is more than
`
`100 µm. See, e.g., Ex. 1003 ¶ 72.
`
`14
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`Additionally, the process embodiments described by Yoshikazu are almost
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`identical to the process embodiments described in the `731 Patent, and both
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`Yoshikazu and the `731 Patent begin by placing wafers on a scribe sheet, as shown
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`in Fig. 8(a) from the `731 Patent and Fig. 3B from Yoshikazu, respectively,
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`reproduced below and annotated. See, e.g., Ex. 1001, Figure 8(a) and Ex. 1005,
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`Figure 3B; see also, Ex. 1003 ¶ 73.
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` Ex. 1001, `731 Patent, Fig. 8(a)
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` (annotated)
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`Ex. 1005, Yoshikazu, Fig. 3B
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` (annotated)
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`
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`Thereafter, the wafer is diced into individual chips, and the sheet upon
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`which the individual dies are located is elongated in order to further separate the
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`individual dies. See, e.g., Ex. 1005, 3:41-43 and Ex. 1001, 8:22-24; see also, Ex.
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`1003 ¶ 74. The similarities with the `731 Patent are shown below in the `731
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`Patent’s Figs. 8(c) and Yoshikazu’s 3C, which have been reproduced below.
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`Ex. 1001, `731 Patent, Fig. 8(c)
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`Ex. 1005, Yoshikazu, Fig. 3C
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`Like the `731 Patent, Yoshikazu also teaches applying a protective resin to
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`fill the spaces between the chips, as shown below in the `731 Patent’s Figure 8(f)
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`and Yoshikazu’s Figure 3E, both of which have been reproduced and annotated.
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`See, e.g., Ex. 1001, Figure 8(f) and Ex. 1005, Figure 3E; see also, Ex. 1003 ¶ 75.
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` Ex. 1001, `731 Patent, Fig. 8(f)
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` (annotated)
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`Ex. 1005, Yoshikazu, Fig. 3E
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` (annotated)
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`Next, solder bumps are placed on the active surfaces of the chips, shown
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`below in the `731 Patent’s Figure 8(g) and Yoshikazu’s Figure 3F, which have
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`been reproduced and annotated. See, e.g., Ex. 1001, 8:36-38, and Ex. 1005, 3:49-
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`50; see also, Ex. 1003 ¶ 77.
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`Ex. 1001, `731 Patent, Fig. 8(g)
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`Ex. 1005, Yoshikazu, Fig. 3F
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` (annotated)
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`Finally, both Yoshikazu and the `731 Patent separate the protective resin-
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`coated individual dies. See, e.g., Ex. 1005, 3:9-11 and 3:15-16 and Ex. 1001 8:38-
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`43; see also, Ex. 1003 ¶ 78. These process steps are illustrated below, respectively,
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`in Figure 8(h) of the `731 Patent and Figure 3G of Yoshikazu. Ex. 1003 ¶ 78.
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`Ex. 1001, `731 Patent, Fig. 8(h)
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`(annotated)
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`Ex. 1005, Yoshikazu, Fig. 3G
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` (annotated)
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` As such, just like in the embodiments described in the `731 Patent,
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`Yoshikazu discloses a process in which a wafer is separated into individual dies,
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`the dies are further separated by elongating a sheet, a resin is inserted between the
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`dies, and a smaller blade is used to re-separate the resin-coated dies. See, e.g., Ex.
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`1003 ¶ 79. The resulting structures are likewise nearly identical in form and
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`function. See, e.g., Ex. 1003 ¶ 79.
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`
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`2. Ohta
`Ohta was issued on May 8, 2001. Ohta was filed in the United States on
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`
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`February 2, 1998 and claims priority to a Japanese patent application filed
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`February 3, 1997. See generally, Ex. 1006; see also, Ex. 1003 ¶ 80. Ohta is prior
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`art to the `731 Patent under at least 35 U.S.C. § 102(e) (Pre-AIA). See, e.g., Ex.
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`1003 ¶ 70. Ohta is titled “Flip-Chip Resin-Encapsulated Semiconductor Device.”
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`See, e.g., Ex. 1003 ¶ 70.
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`
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`Ohta teaches a structure that is identical to the structure recited in claim 5.
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`See generally, Ex. 1003 ¶¶ 80-84. In particular, Ohta teaches the structure
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`illustrated in Ohta’s Figure 3, reproduced and annotated below. See, e.g., Ex.
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`1006, Figure 3; see also, Ex. 1003 ¶ 81. Additionally, for comparison purposes,
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`Ohta’s Figure 3 (which has been rotated 180° for a better comparison) is also
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`compared element by element to Figure 4D of the `731 Patent.
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`
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`Ex. 1001, `731 Patent, Fig. 4D
`(annotated)
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` Ex. 1006, Ohta, Fig. 3
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` (annotated)
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`In particular, Ohta teaches a device that includes a bare chip (semiconductor
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`
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`
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`chip 5). See, e.g., Ex. 1006, 14:44-49; see also, Ex. 1003 ¶ 82. Multiple plural
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`bumps (solder bumps 9) are provided on an active surface of the chip. See, e.g.,
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`Ex. 1006, 5:38-41 and 11:43-51, see also, Ex. 1003 ¶ 82. Protective members
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`(resin layer 7) encapsulate the entire bare chip (semiconductor chip 5) and are
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`therefore formed on the sides of the bare chip (semiconductor chip 5) and
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`surrounds its periphery. See, e.g., Ex. 1006, 6:43-46; see also, Ex. 1003 ¶ 82. Ohta
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`further discloses that, in one of the disclosed embodiments, 2.5 mm of the
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`protective members (resin layer 7) is located on each side of the bare chip
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`(semiconductor chip 5). See e.g., Ex. 1006, 33:25-26 and 33:16; see also, Ex. 1003
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`¶ 82. As such, the protective members (resin layer 7) are larger than 100 µm, thus
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`the sum of the width of the bare chip (semiconductor chip 5) and the protective
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`members (resin
`
`layer 7), regardless of
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`the
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`thickness of
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`the bare chip
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`(semiconductor chip 5), is more than 100 µm. See, e.g., Ex. 1003 ¶ 82.
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`
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`To form these structures, Ohta discloses encapsulating a semiconductor
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`element utilizing a mold which includes a frame-like mold 1 and a press mold 2,
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`and which may be seen in Ohta’s Figure 2D, which has been reproduced and
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`annotated below. See, e.g., Ex. 1006, 33:20-21 and Figure 2D; see also, Ex. 1003
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`¶ 83.
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`Ex. 1006, Ohta, Fig. 2D, annotated
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`In this embodiment, a sealing resin 6 and the semiconductor element 5 are placed
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`into the mold, and the resin is pressurized to flow and encapsulate the
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`semiconductor element. See e.g., Ex. 1006, 6:10-14 and 6:17-22; see also, Ex.
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`
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`1003 ¶ 84.
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`3.
`Lau
`Flip Chip Technology, edited by John H. Lau, (“Lau”) is a textbook that was
`
`
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`published by McGraw-Hill in 1996. See generally, Ex. 1007; see also, Ex. 1003 ¶
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`85. Lau is prior art to the `731 Patent under at least 35 U.S.C. § 102(b) (Pre-AIA).
`
`See, e.g., Ex. 1003 ¶ 85.
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`Lau also teaches each and every element of claim 5 of the `731 Patent as
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`shown in Fig. 15.37 from Lau (reproduced and annotated below, and which shows
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`a scale of 1 mm in the original figure). See generally, Ex. 1003 ¶¶ 85-86. In
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`particular, Lau documents an example of a flip-chip technology including a cross-
`
`sectional view of a bare chip (flip-chip) that includes plural bumps (multiple Au
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`bumps). See, e.g., Ex. 1007, p. 466; see also, Ex. 1003 ¶ 86. Lau discloses
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`protective members (underfill) on the side surfaces of the bare chip (flip-chip).
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`See, e.g., Ex. 1007, pp. 467-468; see also Ex. 1003 ¶ 86. The protective members
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`(underfill) adjacent to a side of the bare chip (flip-chip) have a thickness that is
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`greater than 100 µm. See, e.g., Ex. 1007, Figure 15.37; see also, Ex. 1003 ¶ 86.
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`Ex. 1007, Lau, Fig. 15.37
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`
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`IV. STATEMENT OF PRECISE RELIEF REQUESTED
`A. Claim for Which Review is Requested
`Petitioner requests inter partes review and cancellation of claim 5 of U.S.
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`Patent No. 6,653,731 under 35 U.S.C. § 311. A detailed statement of the reasons
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`for the relief requested is set forth in Section III of this Petition.
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`Claim 5 of the `731 Patent recites:
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`5. A semiconductor device, comprising:
`a bare chip;
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`Petition for Inter Partes Review of U.S. Patent No. 6,653,731
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`plural bumps provided on an active surface of said bare chip; and
`protective members formed on side surfaces of said bare chip to
`surround a periphery of said bare chip,
`wherein a sum of a thickness of each of said protective members and a
`width of said bare chip is more than 100µm.
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`
`
`B. Claim Construction
`This petition analyzes the claims consistent with the broadest reasonable
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`interpretation in light of the specification unless otherwise noted below. See 37
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`C.F.R. § 42.100(b). Petitioner reserves the right to advocate a different claim
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`interpretation in other forums that apply a different standard.
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`
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`1. “bare chip”
`Claim 5 of the `731 Patent recites the term bare chip. See, e.g., Ex. 1003 ¶
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`
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`63. The `731 Patent correlates the term “bare chip” with a “conventional
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`semiconductor device” in two sep