Inter Partes review
`United States Patent 7,126,174
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`GlobalFoundries, Inc.
`
`Petitioner
`
`v.
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`Godo Kaisha IP Bridge 1
`
`Patent Owner
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`Patent No. 7,126,174
`Filing Date: November 24, 2004
`Issue Date: October 24, 2006
`
`Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
`THE SAME
`____________
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`Inter Partes Review No.: To be assigned
`___________________________________________________________________________
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`
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`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
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`1
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`I.
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`II.
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`Table of Contents
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`Preliminary Statement .......................................................................................................1
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`Technological Background ................................................................................................1
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`A.
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`B.
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`Integrated Circuits ....................................................................................................1
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`Isolation Structures ..................................................................................................3
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`1.
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`2.
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`LOCOS ....................................................................................................... 4
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`Shallow Trench Isolation ............................................................................ 4
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`C.
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`Insulating Sidewalls .................................................................................................6
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` The ’174 Patent ..................................................................................................................8 III.
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`A.
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`B.
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`C.
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`D.
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`Admitted Prior Art ...................................................................................................8
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`Challenged Claims .................................................................................................10
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`Representative Embodiment ..................................................................................10
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`The ’174 Patent Is Not Entitled to the Benefit of Foreign Priority Before
`December 19, 1995 ................................................................................................11
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`IV.
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`Statement of Precise Relief Requested for Each Claim Challenged ...........................13
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`A.
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`B.
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`C.
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`D.
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`Claims for Which Review is Requested ................................................................13
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`Statutory Grounds of Challenge .............................................................................13
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`Level of Ordinary Skill ..........................................................................................13
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`Claim Construction ................................................................................................13
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`V.
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`Claims 1–3, 5–7, 9–12, and 14–18 of the ’174 Patent Are Unpatentable ....................14
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`A.
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`Disclosures of the Prior Art ...................................................................................14
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`1.
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`2.
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`3.
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`Lee (U.S. Patent No. 5,153,145) ............................................................... 14
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`Noble (U.S. Patent No. 5,539,229) ........................................................... 15
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`Ogawa (U.S. Patent No. 4,506,434) ......................................................... 16
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`B.
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`The Lee-Noble combination renders claims 1–3, 5–7, 9–12, and 14–18 obvious .17
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`1.
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`2.
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`A POSITA would have found it obvious, and even desirable, to have
`combined the teachings of Lee and Noble ................................................ 18
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`Claim 1 is obvious over the Lee-Noble combination ................................ 25
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`3.
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`6.
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`11.
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`12.
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`13.
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`14.
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`15.
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`16.
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`Claim 2 is obvious over the Lee-Noble combination ................................ 38
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`Claim 3 is obvious over the Lee-Noble combination ................................ 38
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`Claim 5 is obvious over the Lee-Noble combination ................................ 39
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`Claim 6 is obvious over the Lee-Noble combination ................................ 41
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`Claim 7 is obvious over the Lee-Noble combination ................................ 42
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`Claim 9 is obvious over the Lee-Noble combination ................................ 43
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`Claim 10 is obvious over the Lee-Noble combination .............................. 45
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`Claim 11 is obvious over the Lee-Noble combination .............................. 47
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`Claim 12 is obvious over the Lee-Noble combination .............................. 49
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`Claim 14 is obvious over the Lee-Noble combination .............................. 50
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`Claim 15 is obvious over the Lee-Noble combination .............................. 51
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`Claim 16 is obvious over the Lee-Noble combination .............................. 53
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`Claim 17 is obvious over the Lee-Noble combination .............................. 56
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`Claim 18 is obvious over the Lee-Noble combination .............................. 57
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`C.
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`The Lee-Ogawa combination renders claims 1–3, 5–7, 9–12, and 14–18
`obvious ...................................................................................................................58
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`1.
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`2.
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`3.
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`4.
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`5.
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`9.
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`10.
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`11.
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`12.
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`A POSITA would have combined the teachings of Lee and Ogawa ........ 58
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`Claim 1 is obvious over the Lee-Ogawa combination .............................. 63
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`Claim 2 is obvious over the Lee-Ogawa combination .............................. 66
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`Claim 3 is obvious over the Lee-Ogawa combination .............................. 66
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`Claim 5 is obvious over the Lee-Ogawa combination .............................. 66
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`Claim 6 is obvious over the Lee-Ogawa combination .............................. 67
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`Claim 7 is obvious over the Lee-Ogawa combination .............................. 67
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`Claim 9 is obvious over the Lee-Ogawa combination .............................. 67
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`Claim 10 is obvious over the Lee-Ogawa combination ............................ 68
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`Claim 11 is obvious over the Lee-Ogawa combination ............................ 69
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`Claim 12 is obvious over the Lee-Ogawa combination ............................ 69
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`Claim 14 is obvious over the Lee-Ogawa combination ............................ 69
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`13.
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`14.
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`15.
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`16.
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`Claim 15 is obvious over the Lee-Ogawa combination ............................ 69
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`Claim 16 is obvious over the Lee-Ogawa combination ............................ 69
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`Claim 17 is obvious over the Lee-Ogawa combination ............................ 70
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`Claim 18 is obvious over the Lee-Ogawa combination ............................ 70
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`VI.
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`Trial Should Be Instituted on Both Grounds ................................................................70
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` Mandatory Notices Under 37 C.F.R. §42.8 ....................................................................70 VII.
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`A.
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`B.
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`C.
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`D.
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`Real Parties-In-Interest ..........................................................................................70
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`Related Matters ......................................................................................................71
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`Lead and Back-Up Counsel ...................................................................................72
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`Service Information ...............................................................................................72
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`VIII.
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` Certification Under 37 C.F.R. §42.24(d) ........................................................................72
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`IX.
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`X.
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`Payment of Fees................................................................................................................72
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`Time for Filing Petition ...................................................................................................73
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`XI.
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` Grounds for Standing ......................................................................................................73
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` Conclusion ........................................................................................................................73 XII.
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`TABLE OF AUTHORITIES
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`CASES
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`Page(s)
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`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc) ...............................................13
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`STATUTES AND RULES
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`35 U.S.C. ........................................................................................................................................12
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`35 U.S.C. § 103 ..............................................................................................................................12
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`35 U.S.C. §§ 311–319 ......................................................................................................................1
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`35 U.S.C. § 311(c) .........................................................................................................................65
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`MISCELLANEOUS
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`37 C.F.R. § 42.1(b) ........................................................................................................................63
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`37 C.F.R. § 42.8 .......................................................................................................................63, 65
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`37 C.F.R. § 42.24 ...........................................................................................................................64
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`37 C.F.R. § 42.24(d) ................................................................................................................64, 65
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` (37 C.F.R. § 42.100(b)) .................................................................................................................13
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`37 C.F.R. § 42.100 et seq. ................................................................................................................1
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`37 C.F.R. § 42.101(b) ....................................................................................................................65
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`37 C.F.R. § 42.102(a).....................................................................................................................65
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`37 C.F.R. §§ 42.103(a) and 42.15(a) .............................................................................................65
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`37 C.F.R. § 42.104(a).....................................................................................................................65
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`V.B.3, Lee ......................................................................................................................................59
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`V.B.4, Lee ......................................................................................................................................59
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`V.B.6, Lee ......................................................................................................................................59
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`V.B.7, Lee ......................................................................................................................................60
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`V.B.8, Lee ......................................................................................................................................60
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`V.B.9, Lee ......................................................................................................................................61
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`V.B.10, Lee ....................................................................................................................................61
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`V.B.11, Lee ....................................................................................................................................62
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`V.B.12, Lee ....................................................................................................................................62
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`V.B.13, Lee ....................................................................................................................................62
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`V.B.14, Lee ....................................................................................................................................62
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`V.B.15, Lee ....................................................................................................................................62
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`V.B.16, Lee ....................................................................................................................................63
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`2:10-cv-01668-JLL-CCC (D.N.J. Apr. 1, 2010) ............................................................................64
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`Additionally, Lee............................................................................................................................51
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`Although Lee ..................................................................................................................................24
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`B.B.M. Brandt et al., “LOCMOS, a New Technology for Complementary MOS Circuits,” ..........1
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`Besides Schuegraf ..........................................................................................................................19
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`Both Lee .........................................................................................................................................20
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`Further, Lee ....................................................................................................................................36
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`J.A. Appels et al., “Some Problems of MOS Technology,” ............................................................1
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`Lee’s Figure 5 ................................................................................................................................48
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`Lee’s Figure 14 ..............................................................................................................................49
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`Lee’s Figure 15 ..............................................................................................................................14
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`LOCOS, Ogawa .............................................................................................................................55
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`Moreover, Noble’s .........................................................................................................................22
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`Noble’s Figure 13 ...........................................................................................................................15
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`Ogawa’s Figure 5(c) ......................................................................................................................16
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`Section V.B., Lee ...........................................................................................................................52
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`Specifically, Lee .......................................................................................................................22, 54
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`STI. Schuegraf (Ex. 1009) .............................................................................................................18
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`U.S. Patent No. 3,617,824............................................................................................................1, 2
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`U.S. Patent No. 3,787,251................................................................................................................1
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`U.S. Patent No. 4,110,899................................................................................................................1
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`U.S. Patent No. 4,506,434......................................................................................................1, 4, 15
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`U.S. Patent No. 4,638,347................................................................................................................1
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`U.S. Patent No. 4,957,590................................................................................................................1
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`U.S. Patent No. 5,021,353................................................................................................................1
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`U.S. Patent No. 5,153,145......................................................................................................1, 6, 14
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`U.S. Patent No. 5,521,422................................................................................................................1
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`U.S. Patent No. 5,539,229..........................................................................................................1, 14
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`U.S. Patent No. 5,702,976................................................................................................................1
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`U.S. Patent No. 5,733,812................................................................................................................1
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`U.S. Patent No. 5,976,939................................................................................................................1
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`U.S. Patent No. 6,165,826................................................................................................................1
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`U.S. Patent No. 7,126,174...................................................................................................... passim
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`Ueda’s Figure 19(a) .......................................................................................................................19
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`Petition Exhibit 1001:
`Petition Exhibit 1002:
`Petition Exhibit 1003:
`Petition Exhibit 1004:
`Petition Exhibit 1005:
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`Petition Exhibit 1006
`Petition Exhibit 1007:
`Petition Exhibit 1008:
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`Petition Exhibit 1009:
`Petition Exhibit 1010
`Petition Exhibit 1011:
`Petition Exhibit 1012:
`Petition Exhibit 1013:
`Petition Exhibit 1014:
`Petition Exhibit 1015:
`Petition Exhibit 1016:
`Petition Exhibit 1017:
`Petition Exhibit 1018:
`Petition Exhibit 1019:
`Petition Exhibit 1020:
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`Petition Exhibit 1021:
`Petition Exhibit 1022:
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`Petition Exhibit 1023:
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`LIST OF EXHIBITS
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`U.S. Patent No. 7,126,174 to Segawa et al.
`U.S. Patent No. 5,153,145 to Lee et al.
`U.S. Patent No. 3,617,824 to Shinoda et al.
`Expert Declaration of Dr. Sanjay Banerjee, Ph.D.
`J.A. Appels et al., “Some Problems of MOS Technology,” Philips
`Tech. Rev. vol. 31 nos. 7–9, pp. 225–36, 276 (1970).
`U.S. Patent No. 4,110,899 to Nagasawa et al.
`U.S. Patent No. 3,787,251 to Brand et al.
`B.B.M. Brandt et al., “LOCMOS, a New Technology for
`Complementary MOS Circuits,” Philips Tech. Rev. vol. 34 no. 1,
`pp. 19–23 (1974).
`U.S. Patent No. 5,702,976 to Schuegraf et al.
`U.S. Patent No. 4,506,434 to Ogawa et al.
`U.S. Patent No. 4,957,590 to Douglas
`U.S. Patent No. 5,976,939 to Thompson et al.
`U.S. Patent No. 6,165,826 to Chau et al.
`U.S. Patent No. 5,733,812 to Ueda et al.
`U.S. Patent No. 5,539,229 to Noble, Jr. et al.
`U.S. Patent No. 5,521,422 to Mandelman et al.
`U.S. Patent No. 5,021,353 to Lowrey et al.
`U.S. Patent No. 4,638,347 to Iyer
`Japanese Patent Application No. 7-192181 to Segawa et al.
`Certified Translation of Japanese Patent Application No. 7-192181
`to Segawa et al.
`File History of U.S. Patent No. 7,126,174 to Segawa et al.
`File History of Japanese Patent Application No. 7-330112 to
`Segawa et al.
`Certified Translation of Portions of the File History of Japanese
`Patent Application No. 7-330112 to Segawa et al.
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`I.
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`Preliminary Statement
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`U.S. Patent No. 7,126,174 to Segawa et al. (Ex. 1001) is directed to structures for metal-
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`oxide-semiconductor field-effect transistors (“MOSFETs”) and their interconnections.
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`MOSFETs, which can act as switches in integrated circuits, are linked by interconnections,
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`which connect parts of an integrated circuit to one another.
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`MOSFET integrated circuits debuted as early as 1965 (see Ex. 1003). By the mid-1990s,
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`MOSFET/interconnection structures were ubiquitous. Virtually all of the limitations in the
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`challenged claims were known and constitute admitted prior art. (See Ex. 1001, 1:52–5:51, Figs.
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`17, 20(e).) The only feature of the sole independent claim in the ’174 patent, claim 1, that is not
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`admitted prior art is the feature of “L-shaped” sidewalls over the MOSFET and interconnection.
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`But this feature had been known for over a decade before the ’174 patent was filed.
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`This Petition, supported by the Expert Declaration of Sanjay Banerjee, Ph.D., (Ex. 1004),
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`establishes that the challenged claims are unpatentable over the prior art. GlobalFoundries, Inc.
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`(“Global”) respectfully requests inter partes review under 35 U.S.C. §§311–319 and 37 C.F.R.
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`§42.100 et seq. and cancellation of all challenged claims.
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`II.
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`Technological Background
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`A.
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`Integrated Circuits
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`A MOSFET includes a “source,” an inlet to receive current, and a “drain” as an outlet to
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`output current. (Ex. 1004, ¶44.) Electrodes on the source and drain allow current to flow into
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`and out of the transistor. (Id.) Another basic MOSFET element is a “gate,” which controls
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`current flow between the source and drain through a “channel” beneath the gate. (Id.) The gate
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`includes a gate insulator (“gate oxide” or “gate dielectric”) and a gate electrode (“gate”). (Id.,
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`¶45.) The gate electrode can receive a control voltage to switch the MOSFET on and off, and the
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`gate insulator generates an associated electric field that controls the channel. (Id.) “ON” and
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`“OFF” states of a MOSFET are depicted below. (Id.; Ex. 1003, Fig. 5 (below with color
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`annotation).)
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`ON
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`OFF
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`To form circuits, MOSFETs are connected by interconnections, which are electrical
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`conductors that provide pathways for electrical signals. (Ex. 1004, ¶46.) They can be made from
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`a variety of conducting materials, including metals, metal alloys, metal compounds,
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`polycrystalline silicon (polysilicon), and combinations of these (e.g., metal-silicon compounds,
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`called “silicides”). (Id.)
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`Integrated circuits having multiple MOSFETs and interconnections have existed for over
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`50 years. For example, a patent filed in 1965 discloses multilevel interconnections formed
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`between MOSFETs in an integrated circuit. (U.S. Patent No. 3,617,824 to Shinoda et al., Ex.
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`1003, 4:30–73, Figs. 6–7 (below with color and annotation).)
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`B.
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`Isolation Structures
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`The semiconductor industry has steadily moved towards packing more MOSFETs onto
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`each chip. (Ex. 1004, ¶48.) As device densities increase, the distance between devices shrinks,
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`and by the early 1970s, decreasing inter-device distances started to cause undesirable interactions
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`between circuit elements. (See Ex. 1005, 10–12; Ex. 1006, 1:40–2:26; Ex. 1007, 1:6–2:32; Ex.
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`1004, ¶49.) The industry’s solution to this problem was to include insulating “isolation” regions
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`between the devices to shield them from one another. (Ex. 1005, 10–12; Ex. 1006, 1:7–2:66; Ex.
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`1007, 1:6–2:32; Ex. 1008, 2–5; Ex. 1004, ¶49.) Use of such isolation regions has continued
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`through the present time. (Ex. 1004, ¶49.)
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`1.
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`LOCOS
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`Reported as early as 1970, LOCOS (LOCal Oxidation of Silicon) was one of the first
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`isolation techniques. (Ex. 1005, 2, 13; Ex. 1008, 2 & n.4; Ex. 1006, 1:8– 14, 1:63–68; Ex. 1004,
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`¶50.) In LOCOS, selected regions of a silicon substrate are exposed to oxygen at a high
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`temperature to convert the silicon in those regions into silicon dioxide. (Ex. 1005, 4, 6, 10; Ex.
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`1006, 3:18–20, 4:18–34; Ex. 1008, 2–3; Ex. 1004, ¶50.)
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`LOCOS has drawbacks. Silicon dioxide grows laterally as the substrate is oxidized,
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`resulting in unintentional silicon dioxide projections into MOSFET regions, called “overhang” or
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`“bird’s beaks.” (Ex. 1006, 6:1:10; Ex. 1009, 1:47–59; Ex. 1004, ¶51; Ex. 1008, Fig. 2a; Ex.
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`1010, 1:33–42, Fig. 1 (below with color and annotation).) By the mid-1990s, this bird’s beak
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`“pose[d] a limitation to device density” that could be addressed by new isolation techniques.
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`(Ex. 1009, 1:47–59; see also Ex. 1001, 1:29–43 (admitted prior art); Ex. 1004, ¶51.) The bird’s
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`beak (see annotated Fig. 1 below from U.S. Patent No. 4,506,434 to Ogawa et al.) also causes
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`undesirable strain. (Ex. 1010, Fig. 1, 1:42–50).
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`2.
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`Shallow Trench Isolation
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`Shallow trench isolation (STI) was developed to replace LOCOS for small-device
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`processes. (Ex. 1001, 1:29–43; Ex. 1009, 2:20–24; Ex. 1004, ¶52.) In STI, trenches are etched
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`into the substrate and filled with insulating material. (Ex. 1004, ¶52.) Although more expensive
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`and complex than LOCOS, STI resolves the problems of LOCOS. (Ex. 1009, 2:20–24; Ex.
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`1010, 1:60–68; Ex. 1004, ¶52.) Because they are so similar otherwise, STI and LOCOS are
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`interchangeable and functionally equivalent. (See Ex. 1009, 1:31–2:24; Ex. 1011, 4:8–16; Ex.
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`1012, 3:1–10; Ex. 1013, 5:56–67; Ex. 1014, 22:49–52; Ex. 1004, ¶¶53, 82, 198.) Despite the
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`added expense and complexity, the industry adopted STI to increase device density. (Ex. 1004,
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`¶53; see also Ex. 1002, 1:10–14.)
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`In some STI processes, the top of the isolation structure is level with the substrate
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`surface. The industry recognized, however, that such an arrangement can interfere with
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`MOSFET operation if the transistors are packed too closely, as sharp corners of the STI structure
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`enhance local electric fields that degrade device performance. (Ex. 1016, 1:16–37, Abstract,
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`1:6–35, Figs. 6a, 6b; Ex. 1004, ¶54.) These problems become worse if the isolation trench
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`recesses below the substrate surface during subsequent etches because the gate can then “wrap
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`around” the trench corner. (Ex. 1016, 1:30–37, 3:27–48, 4:58–62, Fig. 2; Ex. 1004, ¶54.)
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`To mitigate the wrap-around problem, a raised STI structure can extend above the
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`substrate surface. (See Ex. 1015, 5:49–55, 6:32–50, Fig. 12; Ex. 1016, Abstract, 3:33–34, Fig. 5;
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`Ex. 1004, ¶55.) Raised STI also helps localize source/drain regions by providing a barrier during
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`the ion implantation or diffusion processes used to make them. (Ex. 1015, Abstract, 4:62–65,
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`5:5–8; Ex. 1004, ¶55.) Raised STI structures from the prior art appear below in red. (Ex. 1010,
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`Fig. 5(b); Ex. 1015, Fig. 11; Ex. 1016, Fig. 5.)
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`C.
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`Insulating Sidewalls
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`The ’174 patent acknowledges that a “conventional semiconductor device” had
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`MOSFETs, interconnections, and STI regions with sidewalls. (Ex. 1001, 1:52–2:21, Figs. 17
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`(below with color annotation), 20(e); Ex. 1004, ¶56.). Sidewalls 7a and 7b of features 4a and 4b,
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`respectively, appear below.
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`Sidewalls can (1) prevent damage during etching, (2) insulate electrodes and
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`interconnections to eliminate short-circuits, (3) control the shape of the source/drain regions by
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`creating a barrier against the migration of impurities, and (4) reduce parasitic leakage current.
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`(Ex. 1015, 5:5–9, 6:6–8, 6:32–50; Ex. 1002, 1:44–54, 1:64–2:20, 3:22–30, 5:51–6:4, 6:62–7:7,
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`7:44–8:5, Fig. 15; Ex. 1016, 1:6–10, 3:49–53, 4:5–17, 4:30–32, 4:58–5:2, Fig. 5; Ex. 1017, 8:58–
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`9:2; Ex. 1004, ¶57.)
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`One of the prior-art references relied on in this petition, U.S. Patent No. 5,153,145 to Lee
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`et al. (Ex. 1002), provides sidewalls on gates and gate runners (interconnections) to avoid short-
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`circuits. (Id., 1:47–54.) In response to “increasingly complex interconnection schemes” (Ex.
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`1002, 1:44–47), Lee provided insulating sidewalls on the gates and gate runners (Id., 6:62–7:7,
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`Figs. 13, 15). These “prevent[] electrical contact between patterned layer 170 and the conductive
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`polysilicon heart 117′ of runner 203” and “facilitate[] the formation of a sub-gate level
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`interconnection between junction regions of different transistors . . . without the possibility of
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`shorting to a gate runner.” (Id., 7:44–8:5.) Figure 15 of Lee appears below with color.
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`The process for creating a silicon-metal “silicide” may damage the gate (id., 1:40–43), so
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`Lee discloses insulating gate sidewall spacers between the gate and source/drain to address this.
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`(Id., 4:41–5:4, 5:51–60, 7:16–25, Fig. 9 (shown below with color).) Lee explains that sidewalls
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`“prevent the migration of other types or particles into the gate stack” to avoid “shorting of the
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`gate to the source/drain.” (Id., 5:61–6:30; Ex. 1004, ¶59.)
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`As Lee and other references show, L-shaped sidewalls were known in the semiconductor
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`processing art. (Ex. 1004, ¶60; Ex. 1002, 3:8–21, Figs. 9, 15; Ex. 1018, 3:61–68, Fig. 5 (shown
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`below on left with color); Ex. 1012, 3:1–10, 4:1–10, Fig. 7 (shown below on right with color).)
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` The ’174 Patent III.
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`A.
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`Admitted Prior Art
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`The ’174 patent describes a semiconductor device “with high integration and a decreased
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`area.” (Ex. 1001, 1:13–16.) The ’174 patent explains that “there [we]re increasing demands for
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`more refinement of the semiconductor device.” (Id., 1:17–20.) Although “the LOCOS isolation
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`method [had been] conventionally adopted in view of its simpleness [sic] and low cost,” the ’174
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`patent admits that others already recognized that trench isolation was “more advantageous for
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`manufacturing a refined semiconductor device.” (Id., 1:17–28.) This was because the bird’s
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`beak of LOCOS “invades a transistor region against the actually designed mask dimension,”
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`which was “unallowable” for scaling beyond 0.5 µm. (Id., 1:29–36.) The ’174 patent further
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`admits, “even in the mass-production techniques, the isolation forming method ha[d] started to
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`be changed to the trench isolation method.” (Id., 1:36–43.) The ’174 patent also describes
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`“conventional semiconductor device[s]” with “the conventional trench isolation,” shown below
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`in color-annotated Figures 17 and 20(e). (Id., 1:44–2:22, 3:53–5:11.) The ’174 patent further
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`shows that trench isolation with a top surface higher than the surface of the semiconductor
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`substrate is part of a “conventional trench isolation and a MOSFET.” (Id., 3:53–55, 3:64–4:8,
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`4:45–58, 4:16–19, Figs. 19, 20(a)–20(e) (Fig. 20(e) shown below with color annotations).)
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`B.
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`Challenged Claims1
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`The only independent claim of the ’174 patent recites:
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`1. A semiconductor device, comprising:
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`a trench isolation surrounding an active area of a semiconductor substrate;
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`a gate insulating film formed over the active area;
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`a gate electrode formed over the gate insulating film;
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`first L-shaped sidewalls formed over the side surfaces of the gate electrode;
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`first silicide layers formed on regions located on the sides of the first L-shaped
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`sidewalls within the active area;
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`an interconnection formed on the trench isolation; and
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`second L-shaped sidewalls formed over the side surfaces of the interconnection.
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`(Ex. 1001, 29:39–50.) Claims 2, 3, 5–7, 9–12, and 14–18 depend, directly or
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`indirectly, from claim 1.
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`C.
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`Representative Embodiment
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`As shown below in color-annotated Figure 15(f) of the ’174 patent, one embodiment of
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`the claimed structure has a trench isolation region (2b), a gate electrode (4a), an interconnection
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`(4b), a gate electrode sidewall (32a), and an interconnection sidewall (32b). (Ex. 1001, 21:39–
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`65, 26:40–54, 27:4–8, Figs. 15(a)–15(f).) Isolation region 2b may have a top surface higher in a
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`stepwise manner than the surface of an active area. (Ex. 1001, 13:49–64, 15:34–36.) Further,
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`the gate and interconnection sidewalls (32a and 32b) are “L-shaped.” (Id., 27:4–8.)
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`1 The challenged claims are claims 1–3, 5–7, 9–12, and 14–18.
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`For comparison, “a semiconductor device including the conventional trench isolation and
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`a MOSFET having the salicide structure,” as the ’174 patent characterizes it, is shown below.
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`(Ex. 1001, 3:53–5:11, Fig. 20(e) (below with color annotations).) The only difference relevant to
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`the claim limitations is the “L-shaped” sidewall feature.
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`D.
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`The ’174 Patent Is Not Entitled to the Benefit of Foreign Priority Before
`December 19, 1995
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`The ’174 patent, filed on November 24, 2004,2 claims priority to Japanese Patent
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`2 The ’174 patent claims priority through a line of intervening applications to parent U.S. Application No.
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`08/685,726, filed on Jul. 24, 1996. (Ex. 1021, 137.)
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`Application No. 7-192181 (“the ’181 application”) (Ex. 1019; Ex. 1020), filed on July 27, 1995,
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`and Japanese Patent Application No. 7-330112 (“the ’112 application”)(Ex. 1022; Ex. 1023),
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`filed on December 19, 1995.3 The challenged claims are not entitled to the July 1995 priority
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`date.
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`The ’181 application does not disclose the claimed “first silicide layers” or even mention
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`silicide. The local interconnection (13) is polysilicon, as is the interconnection (4b)