UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`BROADCOM LIMITED
`
`Petitioner
`
`v.
`
`TESSERA, INC.
`
`Patent Owner
`
`
`
`Case No. IPR2017-00889
`Patent No. 6,847,107
`
`
`
`
`
`
`
`
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`
`U.S. PATENT NO. 6,847,107
`
`
`
`
`
`

`

`TABLE OF CONTENTS
`
`I.
`II.
`
`V.
`
`INTRODUCTION ........................................................................................... 1
`REQUIREMENTS FOR IPR .......................................................................... 1
`A. Grounds for Standing ............................................................................ 1
`B.
`Challenge and Relief Requested ........................................................... 1
`IV. BACKGROUND ............................................................................................. 3
`A. Overview of the ’107 Patent .................................................................. 3
`B.
`Priority Date .......................................................................................... 4
`C.
`Prosecution History Summary of the ’107 Patent ................................. 4
`D.
`Claim Construction ............................................................................... 6
`FULL STATEMENT OF THE REASONS FOR THE RELIEF
`REQUESTED .................................................................................................. 7
`A. Ground #1: Claims 1, 2, 5, 6 and 8 are unpatentable under 35 U.S.C. §
`102(b) due to anticipation by Yanagihara ............................................. 7
`1.
`Claim 1 is unpatentable due to anticipation by Yanagihara ....... 7
`2.
`Claim 2 is unpatentable due to anticipation by Yanagihara ..... 14
`3.
`Claim 5 is unpatentable due to anticipation by Yanagihara ..... 15
`4.
`Claim 6 is unpatentable as anticipated by Yanagihara ............. 17
`5.
`Claim 8 is unpatentable as anticipated by Yanagihara. ............ 18
`Ground #2: Claim 3 is unpatentable as obvious under 35 U.S.C. § 103
`over Yanagihara in view of Harada .................................................... 20
`Ground #3: Claims 4 and 7 are unpatentable as obvious under 35
`U.S.C. § 103 over Yanagihara in view of Inoue ................................. 23
`VI. MANDATORY NOTICES UNDER 37 C.F.R. §42.8(A)(1) ....................... 27
`A.
`Real Parties-in-Interest ........................................................................ 27
`B.
`Related Matters .................................................................................... 27
`C.
`Fee ....................................................................................................... 27
`D. Designation of Counsel ....................................................................... 28
`E.
`Service Information ............................................................................. 28
`
`B.
`
`C.
`
`
`
`
`
`i
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`

`

`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Cisco Sys., Inc. v. AIP Acquisition, LLC,
`IPR2014-00247, Paper No. 17 (PTAB June 26, 2014) ........................................ 6
`
`In re CSB-Sys. Int’l, Inc.,
`832 F.3d 1335 (Fed. Cir. 2016) ........................................................................ 6, 7
`
`Facebook, Inc. v. Pragmatus AV, LLC,
`582 F. App’x 864 (Fed. Cir. 2014) ....................................................................... 7
`
`Gardner v. TEC Sys., Inc.,
`725 F.2d 1338 (Fed. Cir. 1984) .................................................................... 22, 27
`
`IMS Tech., Inc. v. Haas Automation, Inc.,
`206 F.3d 1422 (Fed. Cir. 2000) ............................................................................ 8
`
`Leapfrog Enters., Inc. v. Fisher-Price, Inc.,
`485 F.3d 1157 (Fed. Cir. 2007) .................................................................... 22, 27
`
`In re Paulsen,
`30 F.3d 1475 (Fed. Cir. 1994) .............................................................................. 7
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ........................................................................ 6, 7
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999) .............................................................................. 7
`
`Webasto Roof Sys., Inc. v. UUSI, LLC,
`IPR2014-00650, Paper No. 14, 2014 WL 5361600 (PTAB Oct. 17,
`2004) ..................................................................................................................... 6
`
`Statutes
`
`35 U.S.C. § 102(b) ............................................................................................. 1, 2, 7
`
`35 U.S.C. § 102(e) ..................................................................................................... 5
`
`35 U.S.C. § 103 .............................................................................................. 1, 20, 23
`
`
`
`ii
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`

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`35 U.S.C. § 103(a) ..................................................................................................... 5
`
`Other Authorities
`
`37 C.F.R. § 1.116 ....................................................................................................... 5
`
`37 C.F.R. § 1.136(a) ................................................................................................... 5
`
`37 C.F.R. § 42.100(b) ................................................................................................ 6
`
`Rule 42.100(b) ........................................................................................................... 7
`
`
`
`iii
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`

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`LIST OF EXHIBITS
`
`1001
`
`U.S. Patent No. 6,847,107 (“the ʼ107 Patent”)
`
`1002
`
`File History of U.S. Patent No. 6,847,107
`
`1003
`
`1004
`
`1005
`
`Japanese Patent Publication No. JPH05-144823
`(“Yanagihara”) (with English translation and
`attendant affidavit)
`
`Japanese Patent Publication No. JPS64-1257
`(“Harada”) (with English translation and attendant
`affidavit)
`
`Japanese Patent Publication No. JPH02-272737
`(“Inoue”) (with English translation and attendant
`affidavit)
`
`1006
`
`Declaration of Dr. C. P. Wong
`
`
`
`iv
`
`

`

`I.
`
`INTRODUCTION
`
`Broadcom Limited (“Petitioner”), asks that the Board review the
`
`accompanying prior art and analysis, institute trial of inter partes review of claims
`
`1-8 (the “Challenged Claims”) of U.S. Patent No. 6,847,107 (“the ’107 patent”)
`
`(Ex. 1001), and render a final written decision finding the Challenged Claims
`
`unpatentable.
`
`II. REQUIREMENTS FOR IPR
`A. Grounds for Standing
`Petitioner certifies that the ’107 patent is available for inter partes review.
`
`
`Petitioner is not barred or estopped from requesting review of the Challenged
`
`Claims on the grounds identified in this petition.
`
`B. Challenge and Relief Requested
`This petition requests a determination that claims 1, 2, 5, 6 and 8 are
`
`unpatentable due to anticipation under Pre-AIA 35 U.S.C. § 102(b) by Exhibit
`
`1003 (Japanese Patent Publication No. JPH05-144823 (“Yanagihara”)).
`
`Additionally, this petition requests a determination that claim 3 is unpatentable as
`
`obvious under Pre-AIA 35 U.S.C. § 103 over Yanagihara in view of Exhibit 1004
`
`(Japanese Patent Publication No. JPS64-1257 (“Harada”)). Finally, petition also
`
`requests a determination that claims 4 and 7 are unpatentable as obvious under Pre-
`
`AIA 35 U.S.C. § 103 over Yanagihara in view of Exhibit 1005 (Japanese Patent
`
`Publication No. JPH02-272737 (“Inoue”)).
`
`
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`- 1 -
`
`

`

`The following table summarizes the grounds for unpatentability set forth in
`
`detail in this petition:
`
`Ground
`
`’946 Claims
`
`Basis
`
`Ground 1
`
`1, 2, 5, 6 and 8
`
`Anticipated by Yanagihara
`
`Ground 2
`
`3
`
`Ground 3
`
`4 and 7
`
`Obvious over Yanagihara in view of
`Harada
`
`Obvious over Yanagihara in view of
`Inoue
`
`Yanagihara is a published Japanese patent application that discloses a
`
`method for forming high-density bumps in a “flip chip” semiconductor device.
`
`Yanagihara was published on June 11, 1993, and thus is prior art under at least 35
`
`U.S.C. § 102(b).
`
`Harada is a published Japanese patent application that discloses a covering
`
`film made of energy ray shielding resin on a semiconductor device main body in a
`
`flip chip semiconductor device. Harada was published on January 5, 1989, and
`
`thus is prior art under at least 35 U.S.C. § 102(b).
`
`Inoue is a published Japanese patent application that discloses an electrode
`
`structure of a flip chip semiconductor device and a method for forming the
`
`electrode. Inoue was published on November 7, 1990, and thus is prior art under at
`
`least 35 U.S.C. § 102(b).
`
`
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`- 2 -
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`

`

`IV. BACKGROUND
`A. Overview of the ’107 Patent
`Generally, the ’107 patent relates to semiconductor chip packaging, and
`
`particularly a compliant semiconductor package structure. (Ex. 1001 at 1:25-28.)
`
`Semiconductor chips are mounted on substrates and connected to other electrical
`
`components via bonding to electrical traces. (Id. at 1:31-39.) In “flip-chip”
`
`bonding, the contact-bearing surface of the chip faces towards the substrate, and
`
`each contact is joined by a solder bond to the corresponding pad on the substrate.
`
`(Id. at 1:65 – 2:1.) This is done by positioning solder balls on the substrate or chip,
`
`juxtaposing the chip with the substrate in the front-face-down orientation, and
`
`momentarily reflowing the solder. (Id. at 2:1-4.) While the flip-chip technique has
`
`several advantages, it potentially creates substantially rigid solder bonds that are
`
`subject to failure under thermal stress. (Id. at 2:6-13.) Further, the ʼ107 Patent
`
`claims that the flip-chip technique makes it difficult to test the chip before
`
`attaching it to the substrate. (Id. at 2:13-15.) This is incorrect, however, as flip-
`
`chips can be tested using a “wafer level test.” (Ex. 1006 ¶ 53.)
`
`The ʼ107 Patent purports to improve the flip chip technique to address the
`
`aforementioned problems. The ʼ107 Patent describes a fabrication process in
`
`which a first dielectric protective layer is provided on a contact bearing surface of
`
`a semiconductor chip. (Id. at 3:31-33.) A compliant layer preferably consisting of
`
`
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`- 3 -
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`

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`silicone, flexibilized epoxy, a thermosetting polymer or polyimide is provided atop
`
`the dielectric protective layer. (Id. at 3:40-43.) The compliant layer has a
`
`substantially flat top surface and edges that gradually slope down to the top surface
`
`of the dielectric protective layer. (Id. at 3:43-45.) Bond ribbons are then
`
`selectively formed atop both the first dielectric protective layer and the compliant
`
`layer such that each bond ribbon electrically connects each chip contact to a
`
`respective terminal position on the compliant layer. (Id. at 3:52-55.) The terminal
`
`positions are the conductive elements that connect the finished assembly to a
`
`separate substrate such as a printed circuit board. (Id. at 3:58-60.)
`
`
`
`As explained in this Petition, the structure disclosed in the ’107 Patent was
`
`known in the art and does not constitute an invention.
`
`Priority Date
`
`B.
`The ’107 patent claims priority to Provisional U.S. Application No.
`
`60/007,128, filed on October 31, 1995.
`
`Prosecution History Summary of the ’107 Patent
`
`C.
`Patent Owner filed the application that eventually issued as the ’107 patent,
`
`U.S. Application No. 10/219,902, with one (1) claim on August 15, 2002. This
`
`was a continuation of U.S. Application No. 10/107,094 filed on March 26, 2002,
`
`which is a continuation of application No. 09/777,782, filed on Feb. 6, 2001, now
`
`Pat. No. 6,465,878, which is a continuation of application No. 09/071,412, filed on
`
`
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`- 4 -
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`

`

`May 1, 1998, now Pat. No. 6,284,563, which is a continuation-in-part of
`
`application No. 08/739,303, filed on Oct. 29, 1996, now Pat. No. 6,211,572.
`
`A first non-final office action was mailed on January 24, 2003, rejecting
`
`claim 1 under 35 U.S.C. § 102(e) as anticipated by U.S. Patent No. 5,777,379
`
`(“Karavakis et al”). Patent Owner filed a petition for extension of time under 37
`
`C.F.R. § 1.136(a) on June 24, 2003. Included with that filing was an amendment
`
`that changed “a plurality of flexible bond ribbons” in claim 1 to “a plurality of
`
`bond ribbons” and added claims 2-8. In the remarks accompanying the
`
`amendment, the Applicant explained that the removal of “flexible” in claim 1 was
`
`“made so as to not unduly limit the scope of claim 1.”
`
`The Applicant further asserted that “claim 1 requires a compliant layer
`
`having an edge surface and a bond ribbon overlying the edge surface,” and asserted
`
`that these features are not disclosed in Karavakis.
`
`The Examiner issued a Final Rejection on August 20, 2003, maintaining that
`
`Karavakis et al rendered claims 1, 2, 3, 5, 7 and 8 anticipated under 35 U.S.C. §
`
`102(e). The Examiner further found that claims 4 and 6 would have been obvious
`
`under 35 U.S.C. § 103(a) in view of Karavakis et al.
`
`The Applicant submitted an Amendment Under 37 C.F.R. § 1.116 on
`
`February 2, 2004, though the amendment did not make any changes to the claims.
`
`
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`- 5 -
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`

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`Instead, the Applicant again challenged the Examiner’s rejections based on
`
`Karavakis et al.
`
`The Examiner issued a Notice of Allowance on March 1, 2004. The
`
`Applicant submitted a Request for Continued Examination and Information
`
`Disclosure Statement on June 7, 2004. The Examiner issued a second Notice of
`
`Allowance on July 30, 2004.
`
`D. Claim Construction
`Because the ’107 patent is expired, the applicable claim construction
`
`standard is that set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005),
`
`rather than 37 C.F.R. § 42.100(b). Webasto Roof Sys., Inc. v. UUSI, LLC,
`
`IPR2014-00650, Paper No. 14 at 6 n.1, 2014 WL 5361600 (PTAB Oct. 17, 2004);
`
`Cisco Sys., Inc. v. AIP Acquisition, LLC, IPR2014-00247, Paper No. 17 at 3
`
`(PTAB June 26, 2014); In re CSB-Sys. Int’l, Inc., 832 F.3d 1335, 1337, 1341 (Fed.
`
`Cir. 2016). Under the Phillips standard, claim terms are given their ordinary and
`
`customary meanings, as would be understood by a person of ordinary skill in the
`
`art at the time of the invention, having taken into consideration the language of the
`
`claims, the specification, and the prosecution history of record. Phillips, 415 F.3d
`
`1303. In this proceeding, one of ordinary skill in the art at the time of the priority
`
`date of the patent would have been someone with at least an undergraduate degree
`
`in engineering, physics, chemistry, materials science, or similar field, and three to
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`
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`- 6 -
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`

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`five years of industry experience in the field of integrated circuit packaging. (Ex.
`
`1006 ¶¶ 20-25.)
`
`“In many cases, the claim construction will be the same under the Phillips
`
`and [Rule 42.100(b) broadest reasonable interpretation] standards.” CSB-Sys., 832
`
`F.3d at 1341; see also Facebook, Inc. v. Pragmatus AV, LLC, 582 F. App’x 864,
`
`869 (Fed. Cir. 2014) (“The broadest reasonable interpretation of a claim term may
`
`be the same as or broader than the construction of a term under the Phillips
`
`standard.”). Any special definition for a claim term must be set forth with
`
`reasonable clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475,
`
`1480 (Fed. Cir. 1994). Only those terms that are in controversy need to be
`
`construed, and only to the extent necessary to resolve the controversy. Vivid
`
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`V.
`
`FULL STATEMENT OF THE REASONS FOR THE RELIEF
`REQUESTED
`A. Ground #1: Claims 1, 2, 5, 6 and 8 are unpatentable under 35
`U.S.C. § 102(b) due to anticipation by Yanagihara
`
`Yanagihara discloses each and every element of claims 1, 2, 5, 6 and 8 as
`
`described in this section and the accompanying claim charts.
`
`1. Claim 1 is unpatentable due to anticipation by Yanagihara
`
` Claim 1 [A]
`
`A microelectronic assembly comprising: Not limiting. Alternatively, Ex. 1003,
`Object.
`
`
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`- 7 -
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`

`

`The preamble of claim 1 is not limiting. See IMS Tech., Inc. v. Haas
`
`Automation, Inc., 206 F.3d 1422, 1434-35 (Fed. Cir. 2000) (“If the preamble adds
`
`no limitations to those in the body of the claim, the preamble is not itself a claim
`
`limitation and is irrelevant to proper construction of the claim.”). Alternatively,
`
`even if the preamble is found to be limiting, Yanagihara discloses “a
`
`microelectronic assembly.” (Ex. 1006 ¶ 61.) Specifically, Yanagihara discloses “a
`
`method for forming high-density bumps, allowing easy formation of bumps for
`
`electrically conductive circuits in high density at pad portions on a wafer.” (Ex.
`
`1003, Object (emphasis added); Ex. 1006 ¶ 61.) An “electrically conductive
`
`circuit” is a “microelectronic assembly.” (Id.)
`
`Claim 1 [B]
`
`a microelectronic element having a first
`surface including a central region and a
`peripheral region surrounding said
`central region, said microelectronic
`element including a plurality of contacts
`disposed in said central region
`
`Ex. 1003, Figs. 12-13; Object.
`
`Yanagihara discloses a microelectronic element having a first surface
`
`including a central region and a peripheral region surrounding said central region,
`
`said microelectronic element including a plurality of contacts disposed in said
`
`central region. (Ex. 1006 ¶ 62.) Figure 13 shows a chip with a first surface
`
`
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`- 8 -
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`

`

`including a central region and a peripheral region surrounding the central region,
`
`with a plurality of contacts in the central region. (Id.)
`
`Central
`region
`
`Peripheral
`region
`
`Contacts
`
`
`
`
`
`
`
`The specification further describes a cushion portion 6 “disposed on the
`
`periphery” that surrounds the central region of the chip shown in Figure 13, and
`
`“forming an electrically conductive circuit 10 from a surface of each pad portion 3
`
`
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`- 9 -
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`

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`to a surface of the cushion portion 6.” (Ex. 1003, Configuration.) Thus,
`
`Yanagihara discloses pad portions 3 (i.e., the claimed “plurality of contacts”)
`
`disposed in the central region of a chip 2 that is surrounded by a periphery region
`
`that includes “cushion portion 6.” (Ex. 1006 ¶ 63.)
`
`Ex. 1003, ¶¶ 5-6, Fig. 13.
`
`Claim 1 [C]
`
`a compliant layer overlying said
`peripheral region of said first surface,
`said compliant layer having a bottom
`surface facing toward said first surface
`of said microelectronic element, a top
`surface facing upwardly away from the
`first surface of said microelectronic
`element and one or more edge surfaces
`extending between said top and bottom
`surfaces of said compliant layer; and
`
`
`
`Yanagihara discloses a compliant layer overlying the peripheral region. (Ex.
`
`1006 ¶ 64.) In particular, Yanagihara discloses a cushion portion 6 composed of a
`
`“a photosensitive polyimide” that is “disposed on the periphery of each of chips on
`
`a wafer.” (Ex. 1003, ¶ 5; Ex. 1006 ¶ 64.) The polyimide cushion portion is a
`
`compliant layer. (Id.)
`
`As seen in annotated Figures 13 and 12 below, Yanagihara also makes clear
`
`that the polyimide compliant-layer cushion portion has three surfaces: a bottom
`
`surface facing the microelectronic element, a top surface facing away from the
`
`microelectronic element, and two edge surface that each “slopes gently” extending
`
`
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`- 10 -
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`

`

`between the top and bottom surfaces. (Ex. 1003 ¶ 6; Ex. 1006 ¶ 65.) The slope of
`
`the edge surfaces can be seen in Figures 13 and 12. (Id.)
`
`Edge surface
`
`Edge surface
`
`
`
`
`
`(Ex. 1003, Figs. 12 & 13.)
`
`In sum, Figures 13 and 12 show the polyimide cushion (i.e., the claimed
`
`“compliant layer”) overlying the peripheral region of the chip, with the bottom
`
`
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`- 11 -
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`

`

`surface contacting the top (first) surface of the chip, a top surface facing away from
`
`the first surface of the chip, and “gently-sloping” edge surfaces extending between
`
`the top and bottom surfaces of the polyimide layer. (Ex. 1006 ¶ 66.)
`
`Ex. 1003, ¶ 6, Fig. 12, Fig. 13.
`
`Claim 1 [D]
`
`a plurality of bond ribbons disposed
`over said compliant layer so that said
`bond ribbons extend over said top
`surface and one or more of said edge
`surfaces and said bond ribbons
`electrically connect said contacts to
`conductive terminals overlying the top
`surface of said compliant layer.
`
`Yanagihara discloses a plurality of bond ribbons disposed over said
`
`compliant layer so that said bond ribbons extend over said top surface and one or
`
`more of said edge surfaces and said bond ribbons electrically connect said contacts
`
`to conductive terminals overlying the top surface of said compliant layer. (Ex.
`
`1006 ¶ 67.)
`
`Yanagihara specifically discloses that “a conductive film” is sputtered over
`
`the entire surface and sticks to the polyimide layer. (Ex. 1003, ¶ 6; Ex. 1006 ¶ 68.)
`
`The conducting film is then etched to form a conducting circuit comprised of bond
`
`ribbons. (Ex. 1003, ¶ 6; Ex. 1006 ¶ 68.)
`
`
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`- 12 -
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`

`

`Figure 13 shows bond ribbons 11 extending over the top surface and one
`
`edge surface of the compliant-layer cushion 6 and electrically connecting to the
`
`contacts (i.e., “pad portions 3”). (Ex. 1006 ¶ 69.)
`
`Bond ribbons
`
`
`
`(Ex. 1003, Fig. 13.)
`
`The bond ribbons 11 connecting the contacts 3 and the bond ribbons 11 over
`
`the top surface and one edge surface of compliant layer 6 are also shown in Figure
`
`12. (Ex. 1006 ¶ 70.)
`
`
`
`- 13 -
`
`

`

`(Ex. 1003, Fig. 12.)
`
`Accordingly, Yanagihara discloses all elements of claim 1. (Ex. 1006 ¶ 71.)
`
`2. Claim 2 is unpatentable due to anticipation by Yanagihara
`
`
`
`Claim 2
`
`The microelectronic assembly as
`claimed in claim 1, wherein said
`microelectronic element is a
`semiconductor chip.
`
`Ex. 1003, Object; ¶ 10.
`
`
`
`As described previously, Yanagihara discloses all the elements of claim 1.
`
`In addition, Yanagihara discloses that the microelectronic element is a
`
`semiconductor chip. (Ex. 1006 ¶ 73.) For example, Yanagihara specifies that
`
`“[t]he cushion portion 6 was formed on the outside of the pad portions 3 on the
`
`periphery of each chip,” and repeatedly refers to the underlying device as a “chip.”
`
`(Ex. 1003 ¶ 10; Ex. 1006 ¶ 73.) Yanagihara further clarifies that such chip
`
`
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`- 14 -
`
`

`

`involves “electrically conductive circuits in high density at pad portions on a
`
`wafer”—a reference one of ordinary skill in the art would understand to refer to a
`
`semiconductor wafer. (Ex. 1006 ¶ 73.) In fact, Yanagihara makes explicit that
`
`“wafer-mounter chips” contain “semiconductor components” (Ex. 1003 ¶ 2), and
`
`that the wafer 1 is made from “silicon”—a ubiquitous semiconductor material used
`
`for microelectronic chips (id. ¶ 7). (Ex. 1006 ¶ 73.)
`
`Accordingly, Yanagihara discloses all elements of claim 2. (Id. ¶ 74.)
`
`3. Claim 5 is unpatentable due to anticipation by Yanagihara
`
`Claim 5
`
`The microelectronic assembly as
`claimed in claim 1, wherein said
`contacts are spaced apart from one
`another in an array.
`
`Ex. 1003, Fig. 13.
`
`
`
`As described previously, Yanagihara discloses all the elements of claim 1.
`
`In addition, Yanagihara discloses that the contacts (i.e., “pad portions 3”) are
`
`spaced apart in an array. (Ex. 1006 ¶ 76.) This is shown in Figures 3 and 13. (Id.)
`
`
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`- 15 -
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`

`

`[3]
`
`.L":
`
`E...DE
`
`_J.
`
`IL!
`
`[|3>!|13]
`
`
`
`
`
`(Ex. 1003, Figs. 3 & 13.)
`(Ex. 1003, Figs. 3 & 13.)
`
`
`
`- 16 -
`
`-16-
`
`
`

`

`
`
`Indeed, Yanagihara specifically references “an array and configuration” of
`
`contacts and bond ribbons shown in Figure 13. (See Ex. 1003 ¶ 7; Ex. 1006 ¶ 77.)
`
`Accordingly, Yanagihara discloses all elements of Claim 5. (Id. ¶ 78.)
`
`4. Claim 6 is unpatentable as anticipated by Yanagihara
`
`Ex. 1003, ¶ 6.
`
`Claim 6
`
`The microelectronic assembly as
`claimed in claim 1, wherein said
`compliant layer is selected from the
`group of materials consisting of a
`curable liquid, silicone, flexibilized
`epoxy, a thermosetting polymer,
`fluoropolymer and thermoplastic
`polymer.
`
`As described previously, Yanagihara discloses all the elements of claim 1.
`
`In addition, Yanagihara teaches that the compliant layer is selected from the group
`
`of materials consisting of a curable liquid, silicone, flexibilized epoxy, a
`
`thermosetting polymer, fluoropolymer and thermoplastic polymer. (Ex. 1006 ¶
`
`80.) In particular, Yanagihara specifies that the compliant layer is a polyimide
`
`layer. (See Ex. 1003 ¶ 6; Ex. 1006 ¶ 80.) Polyimide is a thermosetting polymer
`
`and can also be a thermoplastic polymer. (Ex. 1006 ¶ 80.) For thermosetting
`
`polyimide, after spin coating of the polyimides on a substrate, a soft bake is needed
`
`to remove the solvent from the polyimide solution and subsequently it cures at a
`
`higher temperature to crosslink the polyamic acid to form the polyimide by a ring
`
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`closing of the polyamic acid by eliminating a water molecule to form a polyimide
`
`structure. (Id. ¶ 81.) For thermoplastic polyimide, the polyimide is precured, and
`
`thus a soft bake process is only needed to remove the solvent. (Id. ¶ 82.)
`
`Accordingly, Yanagihara discloses all elements of claim 6. (Id. ¶ 83.)
`
`5. Claim 8 is unpatentable as anticipated by Yanagihara.
`
`Claim 8
`
`The microelectronic assembly as
`claimed in claim 1, wherein said bond
`ribbons are flexible.
`
`Ex. 1003, ¶ 6, Fig. 12, Fig. 13.
`
`As described previously, Yanagihara discloses all the elements of claim 1.
`
`In addition, Yanagihara teaches that the bond ribbons are flexible. (Ex. 1006 ¶ 85.)
`
`As an initial matter, the bond ribbons must be flexible to conform to the sloping
`
`shape of the cushion layer. (Id.) A bond ribbon is made of a material that can
`
`always be extended and absorbs stress causes by the thermal coefficient of
`
`expansion (TCE) that generates stress on two dissimilar TCE materials, here the
`
`integrated circuit and the substrate. (Id.)
`
`Figure 12 shows the bond ribbon conforming to the shape of the compliant
`
`layer. (Id. ¶ 86.)
`
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`
`
`(Ex. 1003, Fig. 12.)
`
`Further, the bond ribbons (i.e., bumps 11) of Yanagihara are taught to be
`
`“extended-life” because, in combination with the compliant-layer cushion portion,
`
`“elastic deformation [is] possible, thereby allowing not only absorption of strains
`
`caused by thermal expansion and shrinkage occurring after placement of wafer
`
`chips containing semiconductor components on a glass-epoxy printed circuit
`
`board, but also control of rupture caused by shear stress.” (Id. ¶ 11; Ex. 1006 ¶
`
`87.) Such “elastic deformation” and “absorption of strains” would not be possible
`
`if the bond ribbons 11 over the cushion 6 were not “flexible.” (Id. ¶ 87.) As
`
`explained above, bond ribbon materials are used as buffer between the two
`
`materials with different TCEs, and thus must be flexible. (Id.) Accordingly,
`
`Yanagihara discloses all elements of claim 8. (Id. ¶ 88.)
`
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`B. Ground #2: Claim 3 is unpatentable as obvious under 35 U.S.C. §
`103 over Yanagihara in view of Harada
`
`Ex. 1004 at 5.
`
` Claim 3
`
`The microelectronic assembly as
`claimed in claim 1, further comprising a
`dielectric passivation layer between the
`first surface of said microelectronic
`element and said compliant layer,
`wherein said dielectric passivation layer
`has apertures extending therethrough in
`substantial alignment with said contacts.
`
`As described previously, Yanagihara discloses all the elements of claim 1.
`
`Harada discloses a dielectric passivation layer between the first surface of said
`
`microelectronic element and said compliant layer, wherein said dielectric
`
`passivation layer has apertures extending therethrough in substantial alignment
`
`with said contacts. (Ex. 1006 ¶ 90.)
`
`In particular, Harada discloses that “26 is a passivation film, and is formed
`
`on the lower surface of the device main body 25 excluding the electrodes 24,” i.e.,
`
`a dielectric passivation layer on the first surface of the microelectronic element
`
`with apertures extending therethrough in substantial alignment with the contacts.
`
`On top of the passivation film, there is “a first polyimide layer,” i.e. a compliant
`
`layer as claimed in the ʼ107 Patent. (Ex. 1004 at 5; Ex. 1006 ¶ 91.) Harada thus
`
`discloses a passivation film between the microelectronic element and the compliant
`
`layer, with holes (apertures) over the electrodes (contacts). (Id.)
`
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`On its part, Harada reflects the general state of the art of semiconductor
`
`packaging at the time of the alleged invention of the ’107 Patent wherein compliant
`
`layers were formed on top of microelectronic devices. (Id. ¶ 92.) For the reasons
`
`described in more detail below, it would have been obvious to a person of skill in
`
`the art to combine Yanagihara with the teachings of Harada to create the
`
`passivation film between the microelectronic device and the compliant layer with
`
`the contacts exposed. (Id.)
`
`Harada and Yanagihara both relate to “flip chip” technology. (Compare Ex.
`
`1003 ¶ 1 (“The present invention relates to a method for forming bumps in high
`
`density on a wafer in a TAB or flip chip process . . . .”) with Ex. 1004 at 3 (“The
`
`present invention relates to a semiconductor device, especially to a semiconductor
`
`device that is a flip chip.”); see also Ex. 1006 ¶ 93.) Both references are also
`
`primarily concerned with forming “bumps” in a manner that minimizes the risk of
`
`cracks or ruptures in the device. (Compare Ex. 1003 ¶ 11 (“thereby allowing not
`
`only absorption of strains caused by thermal expansion and shrinkage occurring
`
`after placement of wafer chips on a glass-epoxy printed circuit board, but also
`
`control of rupture caused by shear stress, so that it has become feasible to obtain
`
`extended-life bumps”) with Ex. 1004 at 2 (“so that crack and soft error do not
`
`occur in a passivation film”); see also Ex. 1006 ¶ 93.) Thus, a person of ordinary
`
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`skill in the art seeking to solve the problems addressed by these patents would have
`
`considered the references together. (Id.)
`
`Further, one of ordinary skill in the art would have understood the
`
`advantages of combining a compliant layer with a passivation film as taught by
`
`Harada. (Id. ¶ 94.) Harada teaches the use of a polyimide layer (compliant layer)
`
`over the passivation film. (Ex. 1004 at 5; Ex. 1006 ¶ 94.) The polyimide later “has
`
`an impact buffering function” to protect the passivation film from cracks. (Ex.
`
`1004 at 5-6; Ex. 1006 ¶ 94.) Specifically, “due to the force acting on the
`
`passivation film 26 becomes scarce [i.e., becoming smaller], no crack is generated
`
`in the passivation film, and protection of the device main body 25 is not
`
`compromised.” (Ex. 1004 at 6; Ex. 1006 ¶ 94.)
`
`Thus, the use of passivation layers and compliant layers was known in the
`
`art, and Claim 3 merely combines two well-known concepts in an obvious manner.
`
`Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007)
`
`(finding obvious “the adaptation of an old idea or invention . . . using newer
`
`technology that is commonly available and understood in the art.”). (Ex. 1006 ¶
`
`95.) This is especially true given that the mere inclusion of a passivation layer in
`
`Claim 3 of the ’107 Patent does nothing to “specify a device which performed and
`
`operated any differently from the prior art.” See Gardner v. TEC Sys., Inc., 725
`
`F.2d 1338, 1349 (Fed. Cir. 1984). (Ex. 1006 ¶ 95.)
`
`
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`Therefore, claim 3 is unpatentable as obvious in view of Yanagihara in view
`
`of Harada. (Ex. 1006 ¶ 96.)
`
`C. Ground #3: Claims 4 and 7 are unpatentable as obvious under 35
`U.S.C. § 103 over Yanagihara in view of Inoue
`
` Claim 4
`
`The microelectronic assembly as
`claimed in claim 1, further comprising
`an encapsulant layer overlying said
`bond ribbons.
`
`Claim 7
`
`The microelectronic assembly as
`claimed in claim 1, further comprising a
`top dielectric layer overlying said bond
`ribbons so that only the conductive
`terminals are accessible at a top surface
`of said compliant layer.
`
`Ex. 1005 at 6, Fig. 2(d).
`
`Ex. 1005 at 6, Fig. 2(d).
`
`As described previously, Yanagihara discloses all the elements of claim 1.
`
`Inoue discloses an encapsulant layer overlying said bond ribbons and a top
`
`dielectric layer overlying said bond ribbons so that only the conductive terminals
`
`are accessible at a top surface of said compliant layer. (Ex. 1006 ¶ 98.) Either of
`
`these limitations may be met by a dielectric layer overlaying the bond ribbons such
`
`that the conductive terminals on the top surface of the compliant layer are
`
`accessible. (Id.) In particular, it was well-known to use polymeric encapsulants to
`
`protect the metal traces (bond ribbons). (Id.) When such encapsulants are used,
`
`
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`the terminal pa