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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`________________
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`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`________________
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`NVIDIA CORPORATION,
`Petitioner
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`
`v.
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`POLARIS INNOVATIONS LIMITED,
`Patent Owner
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`________________
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`
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`Case No. IPR2017-00901
`Patent No. 7,405,993
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`________________
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`PATENT OWNER’S AMENDED NOTICE OF APPEAL
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`

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`Pursuant to 35 U.S.C. §§ 141(c) and 319 and the February 10, 2022 order from
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`the United States Court of Appeals for the Federal Circuit (CM/ECF Dkt. # 87), the
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`patent owner, Polaris Innovations Limited (“Polaris”) hereby provides this amended
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`notice of appeal. Polaris intends to continue its appeal (no. 2019-1484) at the court
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`following the recent limited remand for the purpose of Director rehearing pursuant
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`to United States v. Arthrex, Inc., 141 S. Ct. 1970 (2021).
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`In particular, Polaris continues to appeal from the Final Written Decision
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`entered by the Patent Trial and Appeal Board on December 19, 2018 (Paper 45, copy
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`attached) and from all underlying orders, decisions, rulings and opinions. In
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`addition, Polaris now gives notice that it wishes to appeal from (1) the January 14,
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`2022 decision (Paper 54, “Rehearing Decision,” copy attached) of Andrew
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`Hirshfeld, Commissioner for Patents, Performing the Functions and Duties of the
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`Under Secretary of Commerce for Intellectual Property and Director of the United
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`States Patent and Trademark Office, denying Polaris’s request for Director rehearing
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`and (2) the Board’s refusal to grant the parties’ joint motion to terminate (Paper 48)
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`following the parties’ settlement.
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`This notice of appeal is timely filed within seven days of the court’s February
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`10, 2022 order.
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`In accordance with 37 C.F.R. § 90.2(a)(3)(ii), Polaris indicates that the issues
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`on appeal include (1) all of the issues identified in Polaris’s original notice of appeal
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`filed January 25, 2019 (Paper 4) except the constitutionality of the appointments of
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`the Board judges who rendered the Final Written Decision and (2) the Board’s
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`refusal to grant the parties’ joint motion to terminate and the Board’s failure to
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`terminate this inter partes review after the parties settled this case.
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`Polaris’s original notice of appeal, which is incorporated by reference herein,
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`noted, inter alia, the following issues for appeal:
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`(A) The Board’s determinations of unpatentability of claims 2-6 of U.S.
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`Patent No. 7,405,993, including the determinations that (1) claims 2-6
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`are unpatentable under 35 U.S.C. § 103 as obvious over LaBerge (U.S.
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`Patent Appl. Publ. No. 2005/0177690, Ex. 1005) in view of Bhakta (U.S.
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`Patent Appl. Publ. No. 2005/0281096, Ex. 1010), (2) claims 2 and 4 are
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`unpatentable under 35 U.S.C. § 103 as obvious over Kinsley (U.S. Patent
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`Appl. Publ. No. 2006/0044860, Ex. 1006) in view of Swanson (U.S.
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`Patent Appl. Publ. No. 2003/0046507, Ex. 1007), and (3) claims 2-4 are
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`unpatentable under 35 U.S.C. § 103 as obvious over Kinsley in view of
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`Swanson and further in view of Stave (U.S. Patent Appl. Publ. No.
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`2005/0283671, Ex. 1011);
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`(B) The Board’s interpretations of claims 1 and 2 of the ’993 Patent,
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`including by way of example and not limitation, the phrases “memory
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`chips,” “semiconductor memory component,” and “wherein
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`the
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`semiconductor memory component comprises a plurality of memory
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`chips”; and
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`(C) The Board’s determinations that the references, particularly LaBerge,
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`Bhakta, and Kinsley, disclose the recited semiconductor memory
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`component comprising a plurality of memory chips.
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`Polaris also objects to the Director participating in this appeal as an intervenor
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`regarding the patentability issues (A)-(C) above for lack of constitutional standing.
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`Date: 2022 Feb. 17
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`Respectfully submitted,
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`By: / M.C. Phillips /
`Matthew C. Phillips
`Registration No. 43,403
`Lead Counsel for Patent Owner
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`CERTIFICATE OF SERVICE AND FILING
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`I hereby certify that on February 17, 2022, copies of the foregoing PATENT
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`OWNER’S AMENDED NOTICE OF APPEAL and all documents filed with it were
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`served via electronic mail, as agreed to by counsel, upon the following counsel for
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`the Petitioner:
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`David M. Hoffman:
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`Jeremy J. Monaldo:
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`W. Karl Renner:
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`Oliver Richards:
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`Katherine A. Vidal:
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`IPR24069-0005IP1@fr.com,
`PTABInbound@fr.com,
`hoffman@fr.com
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`IPR24069-0005IP1@fr.com,
`PTABInbound@fr.com,
`monaldo@fr.com
`
`IPR24069-0005IP1@fr.com,
`PTABInbound@fr.com,
`renner@fr.com
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`IPR24069-0005IP1@fr.com,
`PTABInbound@fr.com,
`orichards@fr.com
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`kvidal@winston.com
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`I further certify that on February 17, 2022, the foregoing PATENT OWNER’S
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`AMENDED NOTICE OF APPEAL was sent by Priority Mail Express® to the
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`Director of the United States Patent and Trademark Office, at the following address:
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`Director of the U.S. Patent & Trademark Office
`c/o Office of the General Counsel
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`
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`I further certify that on February 17, 2022, the foregoing PATENT OWNER’S
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`AMENDED NOTICE OF APPEAL and a copy of the Final Written Decision and
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`the Rehearing Decision were filed with the United States Court of Appeals for the
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`Federal Circuit via its CM/ECF electronic filing system.
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`
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`/ M.C. Phillips /
`Matthew C. Phillips
`Registration No. 43,403
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` Paper 45
`Trials@uspto.gov
`571-272-7822 Entered: December 19, 2018
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`____________
`
`Case IPR2017-00901
`Patent 7,405,993 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`MONICA S. ULLAGADDI, Administrative Patent Judges.
`
`MEDLEY, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
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`

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`IPR2017-00901
`Patent 7,405,993 B2
`
`I. INTRODUCTION
`NVIDIA Corporation (“Petitioner”) filed a Petition for inter partes
`review of claims 1–14 of U.S. Patent No. 7,405,993 B2 (Ex. 1001, “the
`’993 patent”). Paper 2 (“Pet.”). Polaris Innovations Limited (“Patent
`Owner”) filed a Preliminary Response. Paper 6 (“Prelim. Resp.”). On
`August 30, 2017, we instituted an inter partes review of all of the challenged
`claims 1–14 of the ’993 patent on several, but not all, grounds raised in the
`Petition. Paper 9, 28 (“Dec.”). Thereafter, Patent Owner filed a Patent
`Owner Response. Paper 13 (“PO Resp.”). Petitioner filed a Reply to the
`Patent Owner Response. Paper 20 (“Reply”).1
`On April 24, 2018, the Supreme Court issued its decision in SAS Inst.,
`Inc. v. Iancu, 138 S. Ct. 1348 (2018). In light of SAS and “Guidance on the
`Impact of SAS on AIA Trial Proceedings,” issued by the Office, April 26,
`2018 (“Office Guidance”), we instituted review of all challenged claims and
`all grounds presented in the Petition and authorized further briefing. Paper
`29. Subsequently, the Chief Administrative Patent Judge extended the one-
`year period for issuing a Final Written Decision in the present proceeding.
`Papers 30, 31.
`Patent Owner filed a Supplemental Response. Paper 35 (“Supp.
`Resp.”). Petitioner filed a Supplemental Reply. Paper 37 (“Supp. Reply”).
`An oral hearing was held on September 28, 2018. A transcript of the
`hearing has been entered into the record. Paper 44 (“Tr.”).
`
`
`1 Patent Owner filed a listing of alleged improper reply content. Paper 24.
`Petitioner filed a response to the listing. Paper 26. We have considered both
`submissions.
`
`2
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`IPR2017-00901
`Patent 7,405,993 B2
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`In its briefs, Patent Owner only provides arguments regarding claim 2,
`which depends from claim 1. PO Resp. 2, 23–36; Supp. Resp. 3–4, 6, 17–
`18, 25, 31. Claims 3–6 depend directly or indirectly from claim 2, but
`Patent Owner does not provide arguments with respect to any of the
`additional elements claimed in claims 3–6. Id. However, because claims 3–
`6 ultimately depend from claim 2, Patent Owner is contesting the
`unpatentability showing by Petitioner of claims 2–6. Id.
`Per our Scheduling Order, we notified the parties that “any arguments
`for patentability not raised in the [Patent Owner] response will be deemed
`waived.”2 During oral hearing, Patent Owner confirmed that it is “only
`defending claims 2 through 6.” Tr. 28:17–29:8. Nonetheless, Petitioner
`bears the burden to show, by a preponderance of the evidence, that the
`challenged claims are unpatentable. For the reasons that follow, Petitioner
`has shown by a preponderance of the evidence that claims 1–14 of the ’993
`patent are unpatentable.
`
`A. Related Matters
`According to the parties, the ’993 patent was the subject of a pending
`lawsuit that was transferred from the United States District Court for the
`Western District of Texas to the United States District Court for the
`Northern District of California. Pet. 105; Paper 4 (“Patent Owner’s Initial
`Mandatory Notices”), 2–3. Patent Owner identifies the lawsuit pending in
`the Northern District of California, i.e., Polaris Innovations Ltd. v. Dell Inc.,
`
`
`2 See Paper 10, 3; see also Office Patent Trial Practice Guide, 77 Fed. Reg.
`48,756, 48,766 (Aug. 14, 2012) (a patent owner’s “response should identify
`all the involved claims that are believed to be patentable and state the basis
`for that belief”).
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`3
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`Patent 7,405,993 B2
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`Case No. 4:16–cv-07005 (N.D. Cal.). Patent Owner’s Initial Mandatory
`Notices, 2–3. The lawsuit has been stayed pending this proceeding. Tr.
`15:23–16:4, 30:4–8.
`
`B. The ’993 Patent
`The ʼ993 patent is directed to a control component for controlling a
`semiconductor memory component in a semiconductor memory module.
`Ex. 1001, [57], 2:57–59. Depending on the storage capacity and rank
`configuration of the semiconductor memory module, address terminals are
`actuated through selection circuits either with address or control signals. Id.,
`[57]. Control terminals are actuated with different control signals. Id.
`Multiplexing of address and control signals allows the control component to
`control semiconductor memory components with different memory
`configurations without requiring an increased number of control terminals.
`Id. Figure 4 of the ’993 patent is reproduced below.
`
` 
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`4
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`IPR2017-00901
`Patent 7,405,993 B2
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`Figure 4 shows a control unit in a control component for controlling
`semiconductor memory components in a semiconductor memory module.
`Id. at 3:39–41.
`Address terminals A14L, A14R, A15L, and A15R may be used to
`supply address or control signals. See id. at 6:5–14. To control whether
`address or control signals are provided, selection circuits (labeled M1A–
`M4A) select between “address” or “control” signals. Id. at 6:15–60. The
`selection circuits are described as multiplexers and are controlled via a
`control circuit CTR based on a stored module configuration (stored in
`memory circuit EP). Id. at 6:61–67.
`
`C. Illustrative Claim
`Petitioner challenges claims 1–14 of the ’993 patent. Claim 1 and
`claim 2, both reproduced below, are illustrative of the claimed subject matter
`(italicizing added for emphasis):
`1. A control component for controlling a semiconductor
`memory component in a semiconductor memory module,
`comprising:
`a control unit for generating control signals for controlling
`read and write access to the semiconductor memory component
`and for generating address signals for addressing memory cells
`in the semiconductor memory component for read and write
`access;
`a plurality of address terminals for providing the address
`signals; and
`a selection circuit for supplying one of the address
`terminals with a selected signal selected between one of the
`address signals and one of the control signals.
`Id. at 11:24–37.
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`5
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`2. The control component as claimed in claim 1,
`wherein the semiconductor memory component comprises
`a plurality of memory chips; and
`wherein the control unit generates a first of the control
`signal for selecting one of the memory chips for read and write
`access.
`Id. at 11:38–43.
`
`D. Instituted Grounds of Unpatentability
`We instituted trial based on all asserted claims and grounds of
`unpatentability as follows (Dec. 28; Paper 29):
`
`References
`Ajanovic3
`LaBerge4
`Kinsley5 and Swanson6
`Kinsley, Swanson,
`Hung7, and Holman8
`LaBerge and Bhakta9
`
`Challenged Claims
`1, 2, 4, 7, and 8
`1–10
`1, 2, 4, 7, and 8
`9, 10, and 12–14
`1–11 and 14
`
`Basis
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`
`
`3 U.S. Patent No. 6,298,426, issued Oct. 2, 2001 (Ex. 1004) (“Ajanovic”).
`4 U.S. Patent Application Publication No. 2005/0177690 A1, filed Feb. 5,
`2004, published Aug. 11, 2005 (Ex. 1005) (“LaBerge”).
`5 U.S. Patent Application Publication No. 2006/0044860 A1, filed Sep. 1,
`2004, published Mar. 2, 2006 (Ex. 1006) (“Kinsley”).
`6 U.S. Patent Application Publication No. 2003/0046507 A1, filed Aug. 30,
`2001, published Mar. 6, 2003 (Ex. 1007) (“Swanson”).
`7 U.S. Patent No. 7,023,719, issued Apr. 4, 2006 (Ex. 1008) (“Hung”).
`8 U.S. Patent No. 6,968,419, issued Nov. 22, 2005 (Ex. 1009) (“Holman”).
`9 U.S. Patent Application Publication No. 2005/0281096 A1, filed Mar. 7,
`2005, published Dec. 22, 2005 (Ex. 1010) (“Bhakta”).
`6
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`

`IPR2017-00901
`Patent 7,405,993 B2
`
`References
`Ajanovic and Stave10
`Kinsley, Swanson, and
`Stave
`
`Basis
`§ 103(a)
`§ 103(a)
`
`Challenged Claims
`1–4, 7, and 8
`1–4, 7, and 8
`
`II. DISCUSSION
`
`A. Principles of Law
`To prevail in its challenge to Patent Owner’s claims, Petitioner must
`demonstrate by a preponderance of the evidence that the claims are
`unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). A claim is
`unpatentable under 35 U.S.C. § 103(a) if the differences between the
`claimed subject matter and the prior art are such that the subject matter, as a
`whole, would have been obvious at the time of the invention to a person
`having ordinary skill in the art. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398,
`406 (2007). The question of obviousness is resolved on the basis of
`underlying factual determinations including (1) the scope and content of the
`prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of ordinary skill in the art; and (4) when in evidence,
`objective evidence of nonobviousness. Graham v. John Deere Co., 383 U.S.
`1, 17–18 (1966).
`
`B. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art, various factors
`may be considered, including the “type of problems encountered in the art;
`prior art solutions to those problems; rapidity with which innovations are
`
`
`10 U.S. Patent Application Publication No. 2005/0283671 A1, filed June 21,
`2004, published Dec. 22, 2005 (Ex. 1011) (“Stave”).
`7
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`IPR2017-00901
`Patent 7,405,993 B2
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`made; sophistication of the technology; and educational level of active
`workers in the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`(citation omitted). Petitioner’s declarant, Dr. Harry L. Tredennick, testifies
`that a person with ordinary skill in the art “would have a Bachelor’s degree
`in Electrical Engineering and at least 2 years of experience working in the
`field of semiconductor logic design.” Ex. 1003 ¶ 13. Dr. Steven A.
`Przybylski, Patent Owner’s declarant, applies the same definition. Ex. 2002
`¶ 31.
`
`Therefore, we adopt Dr. Tredennick’s assessment of a person with
`ordinary skill in the art. We further note that the prior art of record in the
`instant proceeding reflects the appropriate level of ordinary skill in the art.
`Cf. Okajima v. Bourdeau, 261 F.3d 1350, 1354–55 (Fed. Cir. 2001) (holding
`the Board may omit specific findings as to the level of ordinary skill in the
`art “where the prior art itself reflects an appropriate level and the need for
`testimony is not shown”).
`
`C. Claim Interpretation
`In an inter partes review, claim terms in an unexpired patent are given
`their “broadest reasonable construction in light of the specification of the
`patent in which they appear.” 11 37 C.F.R. § 42.100(b) (2016). Under the
`broadest reasonable construction standard, claim terms are given their
`ordinary and customary meaning, as would be understood by one of ordinary
`skill in the art in the context of the entire disclosure. In re Translogic Tech.,
`Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Only terms which are in
`controversy need to be construed, and only to the extent necessary to resolve
`
`11 We would construe the claim terms discussed below the same under
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc).
`8
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`IPR2017-00901
`Patent 7,405,993 B2
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`the controversy. See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d
`795, 803 (Fed. Cir. 1999).
`If an inventor acts as his or her own lexicographer, the definition must
`be set forth in the specification with reasonable clarity, deliberateness, and
`precision. Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243,
`1249 (Fed. Cir. 1998). It is improper to add an extraneous limitation into a
`claim, i.e., one that is added wholly apart from any need for the addition to
`accord meaning to a claim term. See, e.g., Hoganas AB v. Dresser Indus.,
`Inc., 9 F.3d 948, 950 (Fed. Cir. 1993); E.I. du Pont de Nemours & Co. v.
`Phillips Petroleum Co., 849 F.2d 1430, 1433 (Fed. Cir. 1988). There is a
`presumption that a claim term carries its ordinary and customary meaning.
`CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002).
`To overcome this presumption, the patentee must “clearly set forth” and
`“clearly redefine” a claim term away from its ordinary meaning. Bell
`Atlantic Network Servs., Inc. v. Covad Commc’ns Grp., Inc., 262 F.3d 1258,
`1268 (Fed. Cir. 2001). The disavowal must be “unmistakable” and
`“unambiguous.” Dealertrack, Inc. v. Huber, 674 F.3d 1315, 1322 (Fed. Cir.
`2012).
`Petitioner proposes claim interpretations for “address terminal” and
`“control terminal.” Pet. 18–19. In our Decision to Institute, we interpreted
`these terms. Dec. 6–7. Neither party has indicated that our interpretations
`were improper and we do not perceive any reason or evidence that now
`compels any deviation from our initial interpretations. Accordingly, the
`following constructions apply to this Decision: “address terminal” means “a
`terminal that is capable of providing an address signal,” and “control
`terminal” means “a terminal that is capable of providing a control signal.”
`
`9
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`Patent 7,405,993 B2
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`Patent Owner proposes claim interpretations for “semiconductor
`memory component,” “memory chips,” and “wherein the semiconductor
`memory component comprises a plurality of memory chips,” recited in claim
`2. PO Resp. 8–23. Petitioner opposes Patent Owner’s proposed
`interpretations and proposes its own interpretations. Reply 12, 15. As
`explained below, we do not adopt Patent Owner’s proposed interpretations
`for “semiconductor memory component,” “memory chips,” and “wherein
`the semiconductor memory component comprises a plurality of memory
`chips,” but adopt Petitioner’s proposed interpretations.
`Claim 1 recites in the preamble, “[a] control component for
`controlling a semiconductor memory component in a semiconductor
`memory module.” Ex. 1001, 11:24–37. Claim 2 recites “wherein the
`semiconductor memory component comprises a plurality of memory chips.”
`Id. at 11:39–40.
`Patent Owner argues that “semiconductor memory component” means
`“one discrete packaged semiconductor memory device.” PO Resp. 15–20.
`And although it is not in dispute that the ordinary meaning of “memory
`chip” can refer to either a packaged integrated circuit or a single die (PO
`Resp. 20 (citing Ex. 2002 ¶¶ 38, 48); Reply 12 (citing Ex. 2002 ¶ 38; Ex.
`1019, 43:17–21)), Patent Owner argues that the ’993 patent specification
`only contemplates the latter and not the former, such that a “memory chip”
`means “a single memory IC die.” PO Resp. 20–22. Putting it all together,
`Patent Owner argues that “wherein the semiconductor memory component
`comprises a plurality of memory chips,” recited in claim 2 means a
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`10
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`IPR2017-00901
`Patent 7,405,993 B2
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`“discrete, packaged semiconductor memory device ha[ving] a plurality of
`single memory IC die within the same package.” Id. at 22; Supp. Resp. 7.12
`Petitioner argues that Patent Owner is imposing constructions that
`would require memory ICs (dies) to be packaged in a single piece of plastic,
`as opposed to chips that are themselves packaged integrated circuits, any
`number of which comprise a “semiconductor memory component.” Reply
`5–6; Supp. Reply 1, 3–4.13 Petitioner further argues that to the extent
`“semiconductor memory component” should be construed, the phrase is
`limited only by the number of memory chips that make up the
`“semiconductor memory component.” Reply 12; Ex. 1001, 1:33–34.
`Petitioner argues that to the extent “memory chip” should be construed, that
`term means “a packaged integrated circuit or a single die.” Reply 15.14
`
`
`12 The parties sometimes refer to Patent Owner’s proposed construction as a
`“multi-die package.” See, e.g., Tr. 12:11–14, 16:8–9, 34:18, 45:8–10.
`13 Our citations to the unnumbered pages begins with page 1 on the page
`with the “INTRODUCTION.”
`14 Petitioner alternatively argues that the claims are directed to a “control
`component” for controlling memory, not the memory being controlled, such
`that the specific configuration of the “memory component” does not matter
`by design for the purpose of patentability. Reply 18, 21–23; Tr. 8:18–9:15
`(arguing for the “appropriate weight” we should give the disputed terms).
`We agree with Patent Owner that Petitioner’s appropriate weight argument,
`which we understand to mean that little or no patentable weight should be
`given to the disputed terms, was not presented in the Petition and comes too
`late in the Reply. Paper 24, 1; Tr. 34:3–8. In the Petition, Petitioner clearly
`gives full patentable weight to the disputed terms by showing where in the
`prior art those terms are met. See, e.g., Pet. 70–71, 94–96. Petitioner’s
`“appropriate” or “little” patentable weight argument was not necessitated by
`the arguments presented by Patent Owner’s Response. Rather, Petitioner’s
`appropriate weight theory could have and should have been presented in the
`Petition. As such, the argument comes too late. See 37 C.F.R. § 42.23(b).
`11
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`IPR2017-00901
`Patent 7,405,993 B2
`
`Semiconductor Memory Component
`Although Patent Owner argues that “semiconductor memory
`component” means “one discrete packaged semiconductor memory device”
`(PO Resp. 15–20), nowhere in the claims or the specification of the ’993
`patent is the phrase “discrete package[d],” the individual words of that
`phrase, or the phrase “semiconductor memory device.” Tr. 29:9–18.
`Moreover, Patent Owner does not direct us to anything in the prosecution
`history that would support a construction of the phrase “semiconductor
`memory component” to mean “one discrete packaged semiconductor
`memory device.” Id. at 29:18–21. We do not find anything in the
`prosecution history to support Patent Owner’s construction. The first Office
`Action from the Examiner was “A Notice of Allowability.” Ex. 1002, 12–
`14.
`Patent Owner argues, however, that certain figures of the ’993 patent,
`for example Figure 1 annotated below, describe the “semiconductor memory
`component” as “one discrete packaged semiconductor memory device.” PO
`Resp. 15–18; Supp. Resp. 7.
`
`
`Patent Owner’s annotated Figure 1 from the ’993 patent, shown
`above, is described in the “BACKGROUND” section. Ex. 1001, 1:21–38.
`Patent Owner reproduces Figure 1, with shading, and also refers to
`Figures 5, 7, and 9, and concludes that no other form of a “semiconductor
`memory component,” labeled “HB” in pink shading above, is described and
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`that the ’993 Patent never discloses or contemplates a “semiconductor
`memory component” formed of more than one separately packaged memory
`chip. PO Resp. 15–16 (citing Ex. 2002 ¶ 55; Ex. 2004, 27:12–16). That
`argument, however, is misplaced. The specification of the ’993 patent need
`not explicitly show or describe two separately packaged memory chips
`together as a memory component for the broad claim language to encompass
`such an arrangement. Patent Owner has not directed us to anything in the
`specification or prosecution history that indicates that Patent Owner
`disclaimed a “semiconductor memory component” formed of more than one
`separately packaged memory chip, one which Patent Owner readily
`acknowledges is a possibility. See, e.g., PO Resp. 20 (admitting that the
`term “chip” can refer to either a packaged integrated circuit or a single die).
`The specification of the ’993 patent describes that a semiconductor memory
`component “includes one or more memory chips,” which is a broad
`description, meeting the broad claim language. Ex. 1001, 1:33–35. Neither
`Patent Owner nor Dr. Przybylski address this description. See, e.g., Ex.
`2002 ¶ 55 (asserting that “[n]o broader interpretation of the term
`[semiconductor memory component] is reasonable” despite not addressing
`the description that a semiconductor memory component “includes one or
`more memory chips”).
`Moreover, there are other descriptions in the ’993 patent specification
`that undermine Patent Owner’s proposed construction and its argument that
`the specification makes a “distinction between a ‘memory chip’ and a
`‘semiconductor memory component.’” PO Resp. 21. The specification
`sometimes uses the two terms interchangeably. For instance, the
`specification describes that “the control component SB actuates the relevant
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`semiconductor memory component or the memory chip of the memory
`component via a control signal.” Ex. 1001, 1:54–56 (emphasis added). And
`although Figure 1 shows semiconductor memory components HB arranged
`on a module board, the specification describes “memory chips” being
`“situated on the module board,” and that “the module board holds a total of
`72 memory chips.” Id. at 2:6–8, 2:36–38; see also id. at 8:42–53, 9:25–31
`(interchanging the term “memory chips” located on a particular side of the
`control component with “semiconductor memory components” located on a
`particular side of the control component). Such descriptions would have
`indicated to a person having ordinary skill in the art that the specification of
`the ’993 patent does not necessarily make a distinction between a “memory
`chip” and a “semiconductor memory component” insofar as the exact
`physicality of those elements is concerned. Such descriptions would have
`further indicated that the “semiconductor memory component” is limited by
`the number of memory chips that make up the “semiconductor memory
`component.” Id. at 1:33–35. We note, however, neither Patent Owner nor
`its expert address these other passages.
`Because there are descriptions in the ’993 specification, not addressed
`by Patent Owner, that support a broader construction than the one proposed
`by Patent Owner, we decline to read limitations from the few figures into the
`claim language. Indeed, our reviewing court consistently has not construed
`claims as being limited to particular embodiments. Thorner v. Sony
`Computer Entm’t Am. LLC, 669 F.3d 1362, 1366 (Fed. Cir. 2012) (holding
`that it is not enough that the only embodiment, or all of the embodiments,
`contain a particular limitation to limit a claim to that particular limitation);
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111,
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`1117 (Fed. Cir. 2004); see, e.g., SRAM Corp. v. AD-II Eng’g, Inc., 465 F.3d
`1351, 1359 (Fed. Cir. 2006) (“While SRAM strongly urges the court to
`interpret the claim to encompass the innovative precision indexing shifting
`feature it contends it has invented, we are powerless to rewrite the claims
`and must construe the language of the claim at issue based on the words
`used” (citing Hoganas AB v. Dresser Indus., Inc., 9 F.3d 948, 951 (Fed. Cir.
`1993)); “In this case, the words are clear and the claim covers no more than
`the recited method of taking up lost motion and effecting a shift.”).
`Furthermore, the court “has repeatedly cautioned against limiting the
`claimed invention to preferred embodiments or specific examples in the
`specification.” Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1346–47
`(Fed. Cir. 2015); SuperGuide Corp. v. DirecTV Enters., Inc., 358 F.3d 870,
`875 (Fed. Cir. 2004) (noting that “it is important not to import into a claim
`limitations that are not a part of the claim”). “[I]t is the claims, not the
`written description, which define the scope of the patent right.” Williamson,
`792 F.3d at 1346–47; see also Phillips v. AWH Corp., 415 F.3d 1303, 1312
`(Fed. Cir. 2005) (en banc) (noting that “[i]t is a bedrock principle of patent
`law that the claims of a patent define the invention to which the patentee is
`entitled the right to exclude”). Here we decline the invitation to limit the
`claim language of claim 2 by importing limitations, to the extent they even
`exist, from the specification into the claim.
`We next address Patent Owner’s argument that the Petition’s implied
`interpretation of “semiconductor memory component” is unreasonably broad
`and would include anything with semiconductor memory in it. PO Resp. 17
`(citing Ex. 2002 ¶¶ 50–53). We disagree that Petitioner has applied such a
`broad construction to the phrase. Claim 1 requires the “semiconductor
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`memory component” be in a “semiconductor memory module.” Petitioner
`acknowledges as much. Reply 10–11. The term “semiconductor memory
`component” is not untethered from it being a part of the “semiconductor
`memory module.” Petitioner has correctly applied it that way. Id.; see also
`Pet. 70, 94–95.
`Patent Owner additionally argues that its proposed construction is
`consistent with the art-recognized meaning of the phrase, because the term
`“component” in the electrical arts typically refers to a “discrete packaged
`electronic element.” PO Resp. 18 (citing Ex. 2007; Ex. 2002 ¶ 39). Patent
`Owner’s dictionary definition for “component” is “[a] discrete packaged
`electronic element, such as a resistor, that performs one electrical function.”
`Ex. 2007, 95. Patent Owner fails to explain the relevance of this definition,
`which is directed to a single electronic element, such as a resistor, to the
`term “semiconductor memory component,” which as described in the
`specification “includes one or more memory chips,” and is broadly
`described. Ex. 1001, 1:33–34. Accordingly, we give little weight to Patent
`Owner’s dictionary definition of “component.” Nor are we persuaded by
`Patent Owner’s arguments that Bhakta confirms the meaning of the phrase
`“semiconductor memory component” to mean a discrete packaged
`semiconductor device. PO Resp. 18–19 (citing Ex. 1010 ¶¶ 3, 88, Abstract,
`Fig. 10A; Ex. 2002 ¶¶ 68, 72). Patent Owner fails to explain how Bhakta’s
`use of the term “memory component” is used to narrowly mean a discrete
`packaged semiconductor device only.
`We also have considered Dr. Przybylski’s testimony that “the most
`common use of ‘component’ is to refer to a discrete packaged integrated
`circuit or comparable circuit element.” Ex. 2002 ¶ 39. In support of that
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`assertion, Dr. Przybylski relies on Exhibit 2005, which has a date of 2008.
`The effective filing date of the ’993 patent, however, is no later than October
`31, 2006. Yet, Patent Owner and Dr. Przybylsk