`
`DECLARATION OF R. JACOB BAKER, PH.D., P.E.
`REGARDING U.S. PATENT NO. RE45,542
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`I.
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`TABLE OF CONTENTS
`INTRODUCTION............................................................................................................. 1
`A. Educational Background ..................................................................................................... 1
`B. Career History ..................................................................................................................... 2
`C. Other Relevant Qualifications ............................................................................................. 7
`D. Materials and Other Information Considered ..................................................................... 8
`II.
`UNDERSTANDING OF THE LAW ............................................................................... 8
`A. Legal Standard for Prior Art ............................................................................................... 8
`B. Legal Standard for Anticipation........................................................................................ 10
`C. Legal Standard for Obviousness ....................................................................................... 10
`D. Legal Standard for Claim Construction ............................................................................ 15
`E. Legal Standard for Priority Date ....................................................................................... 21
`III.
`LEVEL OF SKILL OF ONE OF ORDINARY SKILL IN THE ART ...................... 22
`IV.
`TECHNOLOGY BACKGROUND ............................................................................... 23
`A. Power Needs of Peripheral Devices .................................................................................. 24
`B. Power Management .......................................................................................................... 26
`C. Limiting Power Consumption ........................................................................................... 30
`V.
`THE ’542 PATENT......................................................................................................... 34
`A. Summary of the ’542 Patent ............................................................................................. 34
`B.
`’542 Patent Prosecution History ....................................................................................... 44
`VI.
`THE CHALLENGED CLAIMS .................................................................................... 54
`VII. CLAIM CONSTRUCTION ........................................................................................... 57
`A. “peripheral device” ........................................................................................................... 57
`B. “default value” .................................................................................................................. 60
`C. “limiting value” ................................................................................................................. 62
`D. “a connector configured to connect the peripheral device to an electronic device for
`supplying power to the peripheral device” ....................................................................... 65
`“maximum power consumption of the peripheral device” ............................................... 66
`E.
`“means for setting the maximum power consumption of the peripheral device” ............. 75
`F.
`ANALYSIS OF THE PRIOR ART ........................................................................... 79
`VIII.
`A. U.S. Patent No. 5,724,592 to Garner (“Garner”) .............................................................. 80
`B. U.S. Patent No. 6,279,114 to Toombs et al. (“Toombs”) ................................................. 84
`IX. GROUND 1: GARNER ANTICIPATES CLAIMS 28-33, 37-38, AND 40 ............... 86
`A.
`Independent Claim 28 ....................................................................................................... 86
`B. Dependent Claim 29 ....................................................................................................... 112
`C. Dependent Claim 30 ....................................................................................................... 114
`D. Dependent Claim 31 ....................................................................................................... 118
`E. Dependent Claim 32 ....................................................................................................... 120
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`F. Dependent Claim 33 ....................................................................................................... 121
`G. Dependent Claim 37 ....................................................................................................... 122
`H. Dependent Claim 38 ....................................................................................................... 123
`I. Dependent Claim 40 ....................................................................................................... 124
`GROUND 2: COMBINATION OF GARNER AND TOOMBS RENDERS CLAIMS
`X.
`28-33 AND 37-40 OBVIOUS .................................................................................................... 125
`A.
`Independent Claim 28 ..................................................................................................... 147
`B. Dependent Claim 29 ....................................................................................................... 160
`C. Dependent Claim 30 ....................................................................................................... 161
`D. Dependent Claim 31 ....................................................................................................... 162
`E. Dependent Claim 32 ....................................................................................................... 163
`F. Dependent Claim 33 ....................................................................................................... 164
`G. Dependent Claim 37 ....................................................................................................... 165
`H. Dependent Claim 38 ....................................................................................................... 165
`I. Dependent Claim 39 ....................................................................................................... 166
`J. Dependent Claim 40 ....................................................................................................... 167
`XI. RESERVATION OF RIGHTS .................................................................................... 168
`APPENDIX 1: CURRICULUM VITAE OF DR. JACOB BAKER ........................................ 1
`APPENDIX 2: MATERIALS CONSIDERED IN THE PREPARATION OF THIS
`DECLARATION........................................................................................................................... 1
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`I. INTRODUCTION
`1. My name is R. Jacob Baker, Ph.D., P.E. I am a Professor of
`
`Electrical and Computer Engineering at the University of Nevada, Las Vegas. I
`
`have prepared this declaration as an expert witness on behalf of the Petitioner. I am
`
`being compensated for my services at a rate of $550 per hour, which does not
`
`depend on the outcome of this review proceeding or any of the related proceedings
`
`and litigations. In this declaration I give my opinions as to whether claims 28-33
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`and 37-40 of U.S. Patent No. RE 45,542 (the “’542 Patent”) (EX1001) are valid. I
`
`provide technical bases for these opinions as appropriate.
`
`2.
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`This declaration contains statements of my opinions formed to
`
`date and the bases and reasons for those opinions. I may offer additional opinions
`
`based on further review of materials in this case, including opinions and/or
`
`testimony of other expert witnesses.
`
`3.
`
`I have summarized in this section my educational background,
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`career history, publications, and other relevant qualifications. My full curriculum
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`vitae is attached as Appendix 1 to this declaration.
`
`A. Educational Background
`4.
`I received a B.S. degree and a M.S. degree in electrical
`
`engineering from the University of Nevada, Las Vegas (“UNLV”) in 1986 and
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`
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`1988, respectively. I received my Ph.D. in Electrical Engineering from the
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`University of Nevada, Reno, in 1993.
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`5. My doctoral research, culminating in the award of a Ph.D. in
`
`Electrical Engineering in 1993, investigated the use of power MOSFETs (metal
`
`oxide semiconductor field effect transistors) in the design of very high peak power,
`
`and high-speed, instrumentation. I developed techniques to reliably stack power
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`MOSFETs to switch higher voltages, that is, greater than 1,000 V at near 100
`
`Amps of current with nanosecond switching times. This work was reported in the
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`paper entitled “Transformerless Capacitive Coupling of Gate Signals for Series
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`Operation of Power MOSFET Devices,” published in the IEEE Transactions on
`
`Power Electronics. The paper received the 2000 Best Paper Award from the Power
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`Electronics Society. In addition, I have published several other papers in this area
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`and I hold a patent, Patent No. 5,874,830, in the area of power supply design,
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`titled, “Adaptively biased voltage regulator and operating method,” which was
`
`issued on February 23, 1999.
`
`B. Career History
`6.
`I am a licensed Professional Engineer in the State of Idaho and
`
`have more than 30 years of experience, including extensive experience in circuit
`
`design and manufacture of Dynamic Random Access Memory (DRAM)
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`semiconductor integrated circuit chips and CMOS Image Sensors (CISs) at Micron
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`
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`Technology, Inc. (“Micron”) in Boise, Idaho. I also spent considerable time
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`working on the development of Flash memory while at Micron. My efforts resulted
`
`in more than a dozen patents relating to Flash memory. One of my projects at
`
`Micron included the development, design, and testing of circuit design techniques
`
`for a multi-level cell (MLC) Flash memory using signal processing for a 35 nm
`
`technology node. Among many other experiences, I led the development of the
`
`delay locked loop (DLL) in the late 1990s so that Micron DRAM products could
`
`transition to the DDR memory command standard for addressing and controlling
`
`accesses to DRAM. I also provided technical assistance with Micron’s acquisition
`
`of Photobit during 2001 and 2002, including transitioning the manufacture of CIS
`
`products into Micron’s DRAM process technology.
`
`7.
`
`From 1985 to 1993 I worked for EG&G Energy Measurements
`
`and the Lawrence Livermore National Laboratory designing nuclear diagnostic
`
`instrumentation for underground weapon tests at the Nevada test site. During this
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`time I designed over 30 electronic and electro-optic instruments including high-
`
`speed cable and fiber-optic receiver/ transmitters, PLLs, frame- and bit-syncs, data
`
`converters, streak-camera sweep circuits, Pockell’s cell drivers, micro-channel
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`plate gating circuits, and analog oscilloscope electronics.
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`8.
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`I have been teaching electrical engineering since 1991. From
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`1991-1992, I was an adjunct faculty member in the electrical engineering
`
`department of the University of Nevada, Las Vegas.
`
`9.
`
`From 1993 to 2000, I served on the faculty at the University of
`
`Idaho as an Assistant Professor and then as an Associate Professor of Electrical
`
`Engineering.
`
`10.
`
`In 2000, I joined a new electrical and computer engineering
`
`program at Boise State University (“BSU”) where I served as department chair
`
`from 2004 to 2007. At BSU I helped establish graduate programs in electrical and
`
`computer engineering including, in 2006, the university’s second Ph.D. degree.
`
`11.
`
`In 2012, I re-joined the faculty at UNLV where I am currently a
`
`Professor of Electrical and Computer Engineering. Over the course of my career as
`
`a professor, I have advised over 75 graduate students.
`
`12.
`
`I have been recognized for my contributions as an educator in
`
`the field. While at Boise State University, I received the President’s Research and
`
`Scholarship Award (2005), Honored Faculty Member recognition (2003), and
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`Outstanding Department of Electrical Engineering Faculty recognition (2001). In
`
`2007, I received the Frederick Emmons Terman Award (the “Father of Silicon
`
`Valley”). The Terman Award is bestowed annually upon an outstanding young
`
`electrical/computer engineering educator
`
`in recognition of
`
`the educator’s
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`
`
`
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`contributions to the profession. In 2011 I received the IEEE Circuits and Systems
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`Education Award. I have also received the Tau Beta Pi Outstanding Electrical and
`
`Computer Engineering Professor Award the four years I have been at UNLV.
`
`13.
`
`I have more than 30 years of experience doing research and
`
`development in the area of electrical instrumentation in a multitude of areas
`
`including diagnostic electrical and electro-optic instrumentation for scientific
`
`research, integrated electrical/biological circuits and systems, array (memory,
`
`imagers, and displays) circuit design, CMOS analog and digital circuit design,
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`CAD tool development and online tutorials, low-power interconnect and packaging
`
`techniques, design of communication/interface circuits, circuit design for the use
`
`and storage of renewable energy, and power electronics.
`
`14.
`
`I have also performed technical analysis and expert witness
`
`consulting for over 75 companies and laboratories. I have worked as a consultant at
`
`other companies designing memory chips and modules,
`
`including Sun
`
`Microsystems, Oracle Corporation, and Contour Semiconductor. I have worked at
`
`other companies designing CISs, including Aerius Photonics, Lockheed Martin,
`
`and OmniVision Technologies.
`
`15.
`
`I have given more than 50 invited talks at conferences,
`
`companies, and Universities in the areas of integrated circuit design, including:
`
`AMD; Arizona State University; Beijing Jiaotong University; Carleton University;
`
`
`
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`Carnegie Mellon; Columbia University; Dublin City University (Ireland); École
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`Polytechnique de Montréal; Georgia Tech; Gonzaga University; Hong Kong
`
`University of Science and Technology; Indian Institute of Science (Bangalore,
`
`India); Instituto de Informatica (Brazil); Instituto Tecnológico y de Estudios
`
`Superiores de Monterrey; ITESM (Mexico); Iowa State University; Laval
`
`University; Lehigh University; Princeton University; Temple University;
`
`University of Alabama; University of Arkansas; University of Buenos Aires
`
`(Argentina); University of Illinois, Urbana-Champaign; Utah State University;
`
`University of Nevada, Las Vegas; University of Houston; University of Idaho;
`
`University of Nevada, Reno; University of Macau; University of Toronto;
`
`University of Utah; Yonsei University (Seoul, Korea); University of Maryland;
`
`IEEE Electron Devices Conference
`
`(NVMTS);
`
`IEEE Workshop on
`
`Microelectronics and Electron Devices (WMED); the Franklin Institute; National
`
`Semiconductor; AMI semiconductor; Micron Technology; Rendition; Saintgits
`
`College (Kerala, India); Southern Methodist University; Sun Microsystems;
`
`Stanford University; ST Microelectronics (Delhi, India); Tower (Israel); Foveon;
`
`ICySSS keynote; and Xilinx Publications and Patents.
`
`16.
`
`I have authored many books and papers on circuit design. My
`
`published books include CMOS Circuit Design, Layout, and Simulation (Baker, R.
`
`J., Wiley-IEEE, ISBN: 978-0470881323 (3rd ed., 2010)) and CMOS Mixed-Signal
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`
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`Circuit Design (Baker, R. J., Wiley-IEEE, ISBN: 978-0470290262 (2nd ed., 2009)
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`and ISBN: 978-0471227540 (1st ed., 2002)). I have also co-authored DRAM
`
`Circuit Design: Fundamental and High-Speed Topics (Keeth, B., Baker, R. J.,
`
`Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 978-0-470-18475-2 (2008)), DRAM
`
`Circuit Design: A Tutorial (Keeth, B. and Baker, R. J., Wiley-IEEE, ISBN: 0-7803-
`
`6014-1 (2001)), and CMOS Circuit Design, Layout and Simulation (Baker, R. J.,
`
`Li, H.W., and Boyce, D.E., Wiley-IEEE, ISBN: 978-0780334168 (1998)). I have
`
`also contributed as an editor and co-author on several other books on CMOS
`
`circuit design and VLSI.
`
`17.
`
`I am the author and co-author of more than 100 papers and
`
`presentations in the areas of solid-state circuit design and packages. In 2000, I
`
`received the Best Paper Award from the IEEE Power Electronics Society.
`
`18.
`
`I am a named inventor on 144 U.S. patents in integrated circuit
`
`design including Flash memory, DRAM, and CMOS image sensors.
`
`C. Other Relevant Qualifications
`19.
`I currently serve, or have served, on: the IEEE Press Editorial
`
`Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
`
`Microelectronic Systems (2010-present); as the Technical Program Chair of the
`
`2015 IEEE 58th International Midwest Symposium on Circuits and Systems
`
`(MWSCAS 2015); on
`
`the
`
`IEEE Solid-State Circuits Society
`
`(SSCS)
`
`
`
`
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`Administrative Committee (2011-2016); as a Distinguished Lecturer for the SSCS
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`(2012-2015); and as the Technology Editor (2012-2014) and Editor-in-Chief
`
`(2015-present) for the IEEE Solid-State Circuits Magazine. These meetings,
`
`groups, and publications are intended to allow researchers to share and coordinate
`
`research. My active participation in these meetings, groups, and publications
`
`allowed me to see what other researchers in the field have been doing.
`
`20.
`
`In addition to the above, I am an IEEE Fellow and a member of
`
`the honor societies Eta Kappa Nu and Tau Beta Pi.
`
`D. Materials and Other Information Considered
`21.
`I have considered information from various sources in forming
`
`my opinions. A list of materials considered is appended hereto as Appendix 2. I
`
`may review additional documents filed in connection with this proceeding as they
`
`become available.
`
`II. UNDERSTANDING OF THE LAW
`22.
`I have applied the following legal principles provided to me by
`
`counsel in arriving at the opinions set forth in this declaration.
`
`A. Legal Standard for Prior Art
`23.
`I understand that a patent or printed publication (e.g., a
`
`published patent application, technical standard, book, article, etc.) must qualify as
`
`prior art in order to be used to invalidate a patent claim.
`
`
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`24.
`
`I understand that a U.S. or foreign patent qualifies as prior art to
`
`an asserted patent if the prior art patent’s date of issuance is prior to the invention
`
`of the asserted patent. I further understand that a printed publication in the U.S. or
`
`in another country qualifies as prior art to an asserted patent if the date of
`
`publication is prior to the invention of the asserted patent.
`
`25.
`
`I understand that a U.S. or foreign patent qualifies as prior art to
`
`an asserted patent if the date of issuance of the prior art patent is more than one
`
`year before the filing date of the asserted patent. I further understand that a printed
`
`publication qualifies as prior art to an asserted patent if the publication occurs more
`
`than one year before the filing date of the asserted patent.
`
`26.
`
`I understand that a U.S. patent or published patent application
`
`qualifies as prior art to an asserted patent if the filing date of the U.S. patent or
`
`published patent application is prior to the invention of the asserted patent.
`
`27.
`
`I understand that to qualify as prior art, a reference must contain
`
`an enabling disclosure that allows one of ordinary skill in the art to practice the
`
`claims without undue experimentation.
`
`28.
`
`I understand that patents and printed publications that qualify as
`
`prior art can be used to invalidate a patent claim as anticipated or obvious.
`
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`B. Legal Standard for Anticipation
`29.
`I understand that once the claims of a patent have been properly
`
`construed, the second step in determining anticipation of a patent claim requires a
`
`comparison of the properly construed claim language to the prior art on a
`
`limitation-by-limitation basis.
`
`30.
`
`I understand that a prior art reference “anticipates” an asserted
`
`claim, and thus renders the claim invalid, if all elements of the claim are disclosed
`
`in that prior art reference, either explicitly or inherently (i.e., necessarily present or
`
`implied).
`
`31.
`
`I have written this declaration with the understanding that in an
`
`inter partes review anticipation must be shown by a preponderance of the
`
`evidence.
`
`C. Legal Standard for Obviousness
`32.
`I have been instructed by counsel on the law regarding
`
`obviousness, and understand that even if a patent is not anticipated, it is still
`
`invalid if the differences between the claimed subject matter and the prior art are
`
`such that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person of ordinary skill in the pertinent art.
`
`33.
`
`I understand that a person of ordinary skill in the art provides a
`
`reference point from which the prior art and claimed invention should be viewed.
`
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`This reference point prevents a person of ordinary skill from using one's insight or
`
`hindsight in deciding whether a claim is obvious.
`
`34.
`
`I also understand that an obviousness determination includes
`
`the consideration of various factors such as (1) the scope and content of the prior
`
`art, (2) the differences between the prior art and the asserted claims, (3) the level of
`
`ordinary skill in the pertinent art, and (4) the existence of secondary considerations
`
`such as commercial success, long-felt but unresolved needs, failure of others, and
`
`other considerations.
`
`35.
`
`I am informed that secondary indicia of non-obviousness may
`
`include (1) a long felt but unmet need in the prior art that was satisfied by the
`
`invention of the patent; (2) commercial success or lack of commercial success of
`
`processes covered by the patent; (3) unexpected results achieved by the invention;
`
`(4) praise of the invention by others skilled in the art; (5) taking of licenses under
`
`the patent by others; and (6) deliberate copying of the invention. I also understand
`
`that there must be a relationship between any such secondary indicia and the
`
`invention. I further understand that contemporaneous and independent invention by
`
`others is a secondary consideration supporting an obviousness determination.
`
`36.
`
`I understand that an obviousness evaluation can be based on a
`
`combination of multiple prior art references. I understand that the prior art
`
`references themselves or other references may provide a suggestion, motivation, or
`
`
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`reason to combine the prior art references, but other times the nexus linking the
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`prior art references may be simple common sense. I further understand that
`
`obviousness analysis recognizes that market demand, rather than scientific
`
`literature, often drives innovation, and that a motivation to combine references may
`
`be supplied by the direction of the marketplace.
`
`37.
`
`I understand that if a technique has been used to improve one
`
`device, and a person of ordinary skill in the art would recognize that it would
`
`improve similar devices in the same way, using the technique is obvious unless its
`
`actual application is beyond the person’s skill.
`
`38.
`
`I also understand
`
`that practical and common
`
`sense
`
`considerations should guide a proper obviousness analysis, because familiar items
`
`may have obvious uses beyond their primary purposes. I further understand that a
`
`person of ordinary skill in the art looking to overcome a problem will often be able
`
`to fit the teachings of multiple publications together like pieces of a puzzle,
`
`although the pieces do not necessarily have to fit perfectly together. I understand
`
`that obviousness analysis therefore takes into account the inferences and creative
`
`steps that a person of ordinary skill in the art would employ under the
`
`circumstances.
`
`39.
`
`I understand that a particular combination may be proven
`
`obvious by showing that it was obvious to try the combination. For example, when
`
`
`
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`there is a design need or market pressure to solve a problem and there are a finite
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`number of identified, predictable solutions, a person of ordinary skill has good
`
`reason to pursue the known options within his or her technical grasp. Such result,
`
`however, is likely the product of ordinary skill and common sense, and not of
`
`innovation.
`
`40.
`
`I understand
`
`that
`
`the combination of familiar elements
`
`according to known methods may be proven obvious when it does no more than
`
`yield predictable results. When a work is available in one field of endeavor, design
`
`incentives and other market forces can prompt variations of it, either in the same
`
`field or a different one. If a person of ordinary skill can implement a predictable
`
`variation, obviousness likely bars its patentability.
`
`41.
`
`I understand that a person of ordinary skill could have
`
`combined two pieces of prior art or substituted one prior art element for another if
`
`the substitution can be made with predictable results, even if the swapped-in
`
`element is different from the swapped-out element. In other words, the prior art
`
`need not be like two puzzle pieces that must fit together perfectly. The relevant
`
`question is whether prior art techniques are interoperable with respect to one
`
`another, such that a person of skill would view them as a design choice, or whether
`
`a person of skill could apply prior art techniques into a new combined system.
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`42.
`
`It is further my understanding that a proper obviousness
`
`analysis focuses on what was known or obvious to a hypothetical person of
`
`ordinary skill in the art at the time of the invention, not just the patentee.
`
`Accordingly, I understand that any need or problem known in the field of endeavor
`
`at the time of invention and addressed by the patent can provide a reason for
`
`combining the elements in the manner claimed.
`
`43.
`
`I understand that a claim can be obvious in light of a single
`
`reference, without the need to combine references, if the elements of the claim that
`
`are not found explicitly or inherently in the reference can be supplied by the
`
`common sense of one of ordinary skill in the art.
`
`44.
`
`In sum, my understanding is that prior art teachings are
`
`properly combined where a person of ordinary skill in the art at the time of the
`
`invention, having the understanding and knowledge reflected in the prior art and
`
`motivated by the general problem facing the inventor, would have been led to
`
`make the combination of elements recited in the claims. Under this analysis, the
`
`prior art references themselves, or any need or problem known in the field of
`
`endeavor at the time of the invention, can provide a reason for combining the
`
`elements of multiple prior art references in the claimed manner.
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`45.
`
`I have been informed and understand that the obviousness
`
`analysis requires a comparison of the properly construed claim language to the
`
`prior art on a limitation-by-limitation basis.
`
`46.
`
`I have written this declaration with the understanding that in an
`
`inter partes review obviousness must be shown by a preponderance evidence.
`
`D. Legal Standard for Claim Construction
`47.
`I have been instructed by counsel on the law regarding claim
`
`construction and patent claims, and understand that a patent may include two types
`
`of claims, independent claims and dependent claims. An independent claim stands
`
`alone and includes only the limitations it recites. A dependent claim depends on an
`
`independent claim or another dependent claim. I understand that a dependent claim
`
`includes all the limitations that it recites in addition to all of the limitations recited
`
`in the claim(s) from which it depends.
`
`48.
`
`It is my understanding that in proceedings before the USPTO
`
`the claims of an unexpired patent are to be given their broadest reasonable
`
`interpretation in light of the specification from the perspective of one of skill in the
`
`art. It is my understanding that the broadest reasonable interpretation of a claim
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`term may be the same as or broader than an ordinary and customary meaning of a
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`term under the Phillips standard used in district court litigation, but it cannot be
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`narrower.
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`49.
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`In comparing the claims of the ’542 patent to the prior art, I
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`have carefully considered the ’542 patent and its file history in light of the
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`understanding of a person of skill at the time of the alleged invention. I understand
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`that various sources may be relied upon to determine how a person of ordinary
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`skill in the art would have interpreted a claim term. Such sources include the words
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`of the claims themselves, the remainder of the patent’s specification, the
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`prosecution history of the patent (all considered “intrinsic” evidence), and
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`“extrinsic” evidence concerning relevant scientific principles, the meaning of
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`technical terms, and the state of the art.
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`50.
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`I understand that, in construing a claim term, one looks
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`primarily to the intrinsic patent evidence, including the words of the claims
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`themselves, the remainder of the patent specification, and the prosecution history.
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`51.
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`I understand that extrinsic evidence, which is evidence external
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`to the patent and the prosecution history, may also be useful in interpreting patent
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`claims when the intrinsic evidence itself is insufficient.
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`52.
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`I understand that words or terms should be given their ordinary
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`and accepted meaning unless it appears that the inventors were using them to mean
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`something else. In making this determination, the claims, the patent specification,
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`and the prosecution history are of paramount importance. Additionally, the
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`specification and prosecution history must be consulted to confirm whether the
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`patentee has acted as its own lexicographer (i.e., provided its own special meaning
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`to any disputed terms), or intentionally disclaimed, disavowed, or surrendered any
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`claim scope.
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`53.
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`I understand that the claims of a patent define the scope of the
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`rights conferred by the patent. The claims particularly point out and distinctly
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`claim the subject matter which the patentee regards as his invention. Because the
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`patentee is required to define precisely what he claims his invention to be, it is
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`improper to construe claims in a manner different from the plain import of the
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`terms used consistent with the specification. Accordingly, a claim construction
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`analysis must begin and remain centered on the claim language itself. Additionally,
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`the context in which a term is used in the asserted claim can be highly instructive.
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`Likewise, other claims of the patent in question, both asserted and unasserted, can
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`inform the meaning of a claim term. For example, because claim terms are
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`normally used consistently throughout the patent, the usage of a term in one claim
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`can often illuminate the meaning of the same term in other claims. Differences
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`among claims can also be a useful guide in understanding the meaning of particular
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`claim terms.
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`54.
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`I understand that the claims of a patent define the purported
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`invention. I understand that the purpose of claim construction is to understand how
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`one skilled in the art would have understood the claim terms at the time of the
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`purported invention.
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`55.
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`I understand that a person of ordinary skill in the art is deemed
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`to read a claim term not only in the context of the particular claim in which the
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`disputed term appears, but in the context of the entire patent, including the
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`specification. For this reason, the words of the claim must be interpreted in view of
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`the entire specification. The specifica