United States Patent to
`Bormann
`
`[11]
`[45]
`
`4,019,068
`Apr. 19, 1977
`
`icago, Ill
`
`3 * * * *
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`-
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`-
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`-
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`- - -
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`-
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`73l Assi
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`: Motorol
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`., Chi
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`[54] Low Power OUTPUT DISABLE CIRCUIT
`ABSTRACT
`[57]
`FOR RANDOM ACCESS MEMORY
`An output circuit including a latch circuit and a push
`[75] Inventor: Alan Richard Bormann, Tempe,
`pull output driver driven by the latch circuit is con
`Ariz.
`trolled by disable circuit which disables the output
`circuit when a random access memory semiconductor
`otorola, Inc
`[73] Assignee
`chip on which the output circuit is located undergoes
`Sept. 2, 1975
`[22] Filed:
`an unselected memory cycle, i.e., is unselected. The
`[21] Appl. No.: 609,457
`disable circuit includes a bootstrap NOR gate having a.
`-
`series power switching IGFET coupling its load device
`[52] U.S. Cl. ............................... 307/205; 307/209;
`to a voltage supply conductor. The power switching
`307/279; 307/DIG. 4; 307/DIG. 5; 340/173 R IGFET is controlled by the output of the disable circuit
`[51] Int. Cl.” ................. H03K 19/08; H03K 19/34;
`so that the disable circuit shuts off its own power at the
`©
`H03K 3/353; G11C 7/00
`same time it disables the output latch when the random
`-
`[58] Field of Search .......... 307/270, 304, 209, 238,
`access memory chip undergoes an unselected memory
`307/279, 205, DIG.4, DIG. 5; 340/173 R, 173
`cycle. Essentially, the disable circuit operates in such a
`AM manner that it shuts off its own power and also disables
`the output circuit in response to a second input signal,
`---
`th
`lier first signal.
`conditioned on the occurrence of an earlier first signal
`
`[56]
`
`References Cited
`UNITED STATES PATENTS
`3,697,775 10/1972 Kane ................................. 307/209
`3,778,784 12/1973 Karp et al. ..................... 307/238 X
`3,859,637
`1/1975
`Platt et al. ............... 340/173 CP X
`3,906,464 9/1975 Lattin ....................... 307/DIG. 5 X
`Primary Examiner—John S. Heyman
`Assistant Examiner—Larry N. Anagnos
`Attorney, Agent, or Firm—Charles R. Hoffman
`
`
`
`3 Claims, 3 Drawing Figures
`
`SANDISK Exhibit 1003
`Page 1 of 5
`
`

`

`U.S. Patent
`
`April 19, 1977
`
`4,019,068
`
`
`
`*i-----------------------
`|O
`TU DATA OUT 86
`
`72
`
`so 88
`3DATA OUTPUT
`
`-
`
`F|G 2
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`J
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`K
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`M
`
`FIG 3
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`-
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`RAST TY-A
`CASIN
`CAS
`XA B
`
`OE
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`OE'
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`OLD
`
`C
`
`D
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`E
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`OL
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`- * - - - —F
`t
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`GI
`N
`DATA OUT H.L-º
`GO
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`x-y r >74
`ADDRESS < 3
`INPUTS
`
`
`
`76
`7O
`ºs-
`
`78
`
`|/O
`CONTROL
`oCS
`
`STORAGE
`X
`DECODE | ARRAY
`Y-DECODE
`22-0 &–82
`CASIN RASIN
`
`SANDISK Exhibit 1003
`Page 2 of 5
`
`

`

`1
`
`4,019,068
`2
`disable circuit for a random access memory. In this
`embodiment, when the random access memory under
`goes an unselected memory cycle operation, the elec
`tronic circuit disables an output latch circuit of the
`random access memory, and essentially simultaneously
`cuts off power to itself, thereby reducing power dissipa
`tion of the random access memory for an unselected
`memory cycle.
`
`15
`
`20
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a schematic diagram of a preferred embodi
`ment of the invention.
`FIG. 2 is a block diagram of a random access memory
`chip in which the embodiment of FIG. 1 may be uti
`lized.
`FIG. 3 is a timing diagram useful in describing the
`operation of the embodiment of FIG. 1 and FIG. 2.
`
`DESCRIPTION OF THE INVENTION
`FIG. 1 includes, in a presently preferred embodiment
`of the invention, circuit 10 which is a portion of the
`circuitry of a semiconductor integrated circuit random
`access memory 70, as shown in FIG. 2.
`A block diagram of such a semiconductor random
`access memory chip 70 is shown in FIG. 2, which in
`cludes a storage array 72, X decode circuit 76 Y de
`code circuit 78, and input output and control circuitry
`80. A particular memory location in storage array 72 is
`selected by means of address inputs applied to address
`input terminals 74. In one embodiment of the inven
`tion, a particular binary configuration of address inputs
`74 is first multiplexed into corresponding input address
`latch circuit in X decode circuitry 76 in response to a
`control signal on RASIN conductor 82. After the later
`event is completed, a second address control input
`signal CASw, is applied to input conductor 22, and a
`new binary address input configuration on input con
`ductors 74 is thereby multiplexed into the correspond
`ing plurality of additional address input latch circuits in
`Y decode circuit 78. Data stored in the selected storage
`cell is sensed and amplified and routed through input
`output circuitry 80 to provide an output data signal on
`data output conductor 86. In a typical system, a plural
`ity of RAM chips, such as chip 70, are coupled to a
`common address input and a common data output
`conductor, and an additional chip select input disables
`all of the RAM chips except the selected chip, which
`communicates with the common data output conduc
`tor.
`Referring again to FIG. 1, circuitry 10 includes out
`put latch 12 and output disable circuit 14. Output dis
`able circuit 14 includes a bootstrap NOR gate 16, NOR
`gate 20 and inverter 18. Bootstrap NOR gate 16 in
`cludes load MOSFET 38, coupling MOSFET 36, boot
`strap charging MOSFET 34, bootstrap capacitor 32,
`and input MOSFETs 30 and 40. MOSFET 30 is con
`nected between node 28 and ground conductor 26 and
`has its gate connected to CASIN conductor 22. Load
`MOSFET 38 has its gate connected to bootstrap node
`39, its source connected to node 28 and its drain con
`nected to node 37. Bootstrap capacitor 32 is connected
`between node 39 and node 28. Bootstrap charging
`MOSFET 34 is connected between Vop conductor 24
`and node 39, and has its gate connected to Vpp. MOS
`FET 36 is connected between Vpp conductor 24 and
`node 37 and has its gate connected to OL output con
`ductor 60, and functions to electrically isolate the rest
`of bootstrap inverter circuit 16 from Vop conductor 24
`
`LOW POWER OUTPUT DISABLE CIRCUIT FOR
`RANDOM ACCESS MEMORY
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The invention relates to electronic semiconductor
`circuits, and more particularly to circuits which reduce
`power dissipation and semiconductor random access
`memory chips.
`2. Description of the Prior Art.
`MOSFETs (also called IGFETS) have been widely
`utilized, especially in integrated circuit form, to imple
`ment random access memories and other complex
`logic functions.
`Power dissipation is frequently a problem in IGFET
`integrated circuit semiconductor chips because powder
`dissipation in such a chip raises the operating tempera
`ture, which may effect reliability of the MOSFETs on
`the chip. In MOS RAM (random access memory) inte
`grated circuits, especially in dynamic RAMs, the main
`areas of power dissipation are in the column decode
`circuitry, row decode circuitry, sensing circuits, and
`input/output circuits. In memory systems constructed
`from MOS RAM chips packaged in conventional pack
`25
`ages, a fairly large number of chips have their data
`output conductors coupled to a common data bus.
`However, only one chip at a time, referred to as the
`selected chip, can communicate with the common data
`30
`bus. The remaining chips are said to be unselected. The
`chips incorporate circuitry which effectively electri
`cally isolates their data output terminal from any low
`impedance to the respective semiconductor chip in
`response to a chip select input. The chip select input is
`frequently utilized to disable output and data input
`35
`circuitry so that if the chip is unselected during a par
`ticular memory cycle, the data output driver has both
`its load MOSFET and its switch MOSFET turned off so
`that the data output conductor is essentially electrically
`floating, and so that the data input terminal is isolated
`from any storage cell during any memory cycle if the
`chip is unselected.
`SUMMARY OF THE INVENTION
`It is an object of the invention to provide an output
`circuit for a random access memory which reduces the
`power dissipation of a random access memory by inter
`posing a high impedance between the power source
`and said output circuit when said memory chip under
`goes an unselected cycle.
`It is another object of the invention to provide a
`semiconductor circuit which produces an output signal
`in response to a certain combination of input signals
`thereto, which output signal acts upon said circuit to
`55
`reduce current supplied to said circuit, thereby reduc
`ing its power dissipation.
`Briefly described, the invention is an electronic cir
`cuit having an input stage having an input thereof, and
`also having an output stage driven by said input stage.
`The output stage generates an output signal which is
`60
`fed back by means of a voltage conductor to the input
`stage and is connected to a control electrode of a
`switching device connected between the input stage
`and a supply voltage conductor. When a logical zero
`level appears on the output conductor, the switching
`device is turned off, thereby reducing current flow
`through the input stage and reducing power dissipation
`of the electronic circuit. In one embodiment of the
`invention, the electronic circuit is used as an output
`
`40
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`45
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`50
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`65
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`SANDISK Exhibit 1003
`Page 3 of 5
`
`

`

`4,019,068
`3
`4
`under certain circumstances, described hereinafter, to
`The junction common between MOSFETs 52 and 56 is
`reduce power dissipation of output circuit 10 when the
`connected to the gate of MOSFET 90.
`-
`random access memory chip 70 in which output circuit
`The operation of the circuit of FIGS. 1 and 2 is de
`10 is located is not selected, i.e., undergoes an unse
`scribed with reference to the timing diagram of FIG. 3.
`lected memory cycle. NOR gate 20 includes MOSFETs
`The operation of the embodiment of FIG. 1 is de
`42, 46, and 48. Load MOSFET 42 is connected be
`scribed with reference to the waveforms of FIG. 3. FIG.
`tween Vpp conductor 24 and node 44, and has its gate
`3 includes the waveforms of the input waveforms indi
`connected to node 28. Switch MOSFET 46 is con
`cated in FIGS. 1 and 2 and also the waveforms of some
`nected between node 44 and ground conductor 26 and
`of the important internal nodes of the schematic draw
`has its gate connected to the gate of MOSFET 40,
`ing of FIG. 1.
`which is the other switch MOSFET of bootstrap NOR
`The main function of the circuit of FIG. 1 is to dis
`gate circuit 16 and is coupled between node 28 and
`able output latch 12 so that the data out signal on node
`ground conductor 26. MOSFET 48 is the other switch
`86 is effectively electrically open and also to cut off its
`ing MOSFET of NOR gate 20 and is connected be
`own source of power under the condition that the
`tween node 44 and ground conductor 26 and has its
`memory chip 70 is subjected to a “nonselected” cycle.
`15
`gate electrode connected to CASIN input conductor 22.
`The waveform RASIN is the row address control input.
`Node 44 drives the gate of MOSFET 50 which is the
`When this input is activated by undergoing a negative
`output MOSFET of output disable circuit 14 and is
`transition as shown in FIG. 3 the RAM chip is said to be
`connected between OL output conductor 60 and
`selected, for purposes of this discussion. An internal
`ground conductor 26.
`20
`signal XA is derived from RAS, and is utilized by
`circuitry in RAM 70 to strobe the X address inputs into
`Inverter 18 includes load MOSFET 19 connected
`the X address input buffers in X decode section 76.
`between Vpu, and node 15, which is also connected to
`Next, the column address control input signal CASIN
`the gate of MOSFETs 46 and 40. The gate of MOSFET
`undergoes a negative transition which results in the
`19 is connected to XA conductor 82'. Switch MOSFET
`address inputs being multiplexed into a plurality of Y
`25
`17 is connected between node 15 and ground conduc
`input buffers in Y decode circuit 78. Sensing or reading
`tor 26 and has its gate connected to CASIN conductor
`into the selected cell at the intersection of the selected
`22.
`column in the selected row then occurs. However, for
`an unselected memory cycle, no negative transition of
`Output latch 12 includes a cross-coupled latch circuit
`30
`RASw occurs. Instead, only a CASin negative transition
`including MOSFETs 52, 54, 56 and 58. MOSFETs 54
`occurs. This is illustrated in timing diagram of FIG. 3,
`and 58 are coupled in series between ground conductor
`where it is seen that the second #. pulse is not
`26 and OL output conductor 60. Similarly, MOSFETs
`coincident with a RASw pulse. Under these conditions
`52 and 56 are coupled in series between OL output
`it is desirable, in a memory system having a plurality of
`conductor 60 and ground conductor 26. MOSFETs 52
`RAM chips connected to the common data bus, to
`and 54 have their drains connected to OL output con
`deselect or in effect, electrically isolate unselected
`ductor 60 and MOSFETs 56 and 58 have their sources
`RAM chips from the common data output bus. In a
`connected to ground conductor 26.
`typical system, the RASIN address control input will be
`Those skilled in the art will recognize that MOSFETs
`decoded.
`.
`(metal oxide semiconductor field effect transistors), as
`Referring to FIG. 3, the operation of output circuit
`40
`implemented in typical integrated circuits, are bilateral
`10 is described for a typical chip “selected” cycle.
`devices, having a gate and a source and a drain. How
`First, RASIN undergoes negative transition A to a 0
`ever, the source and drain are functionally interchange
`level. This activates circuitry (not shown) which causes
`able, and both in the description and in the claims
`XA to undergo transition B from a logical 0 to a logical
`herein, the terms are utilized merely to indicate inter
`45
`1. This causes MOSFET 19 to turn on. Next, CASw
`connections, rather than function of a particular MOS
`undergoes transition C to a 0 level. This turns
`FET terminal. For example, the terminal of MOSFET
`MOSFET 17 off and MOSFET 19 charges node
`34 which functions as a drain for one part of the circuit
`15 to a logical 1, turning on MOSFETs 40 and 46.
`operation may function as a source for another part of
`MOSFET 30 is also turned off by transition C.
`the circuit operation. For a more complete description
`50
`Since MOSFET 40 is on, node 28 remains at ground,
`of the operation and physics of MOSFETs, see “Physics
`and MOSFET 42 remains off. Thus, node 44, des
`and Technology of Semiconductor Devices”, by A.S.
`ignated by waveform OLD, remains at ground,
`Grove, John Wiley & Sons, Inc., 1967. Those skilled in
`where it was previously discharged by MOSFET 48
`the art will also recognize that the acronym MOSFET is
`when CASw was high. Thus MOSFET 50 remains in
`commonly used synonymously with the term IGFET
`55
`the off condition, and waveform OL at node 60, re
`(insulated gate field effect transistor), even though the
`mains unaffected by disable circuit 14.
`gate may be polycrystalline silicon or some other con
`Output latch 12 is then in a condition so that OL can
`ductive material rather than metal.
`be charged up by MOSFET 64 when OE goes high,
`The gates of MOSFETS 52 and 58 are coupled to
`causing latch 12 to establish a stored logical 1 or logical
`60
`gether and to a source electrode of precharge MOS
`0 in response to an input applied to node 87, which
`receives a signal multiplexed from the bit sense line of
`FET 66, which has its drain connected to Vpp conduc
`tor 24 and its gate connected to OE'. Similarly, MOS
`the selected column of storage array 72. It was assumed
`FETs 54 and 56 have their gates connected together
`during the above operation that MOSFET 36 is on.
`and to the source of MOSFET 68, which has its drain
`MOSFET 36 actually goes on whenever OL is at a
`connected to Von conductor 26 and its gate connected
`logical 1. However, since MOSFET 40 was in an on
`to OE'. The common junction between MOSFETs 54
`condition, node 28 is held at ground regardless of
`and 58 is connected to the gate of MOSFET 88, which,
`whether MOSFET 36 is on or not.
`-
`in combination with MOSFET 90, forms an inverter
`In FIG. 3 the data out waveform indicates the result
`which is coupled/Between Vcc and ground conductor
`of a selected chip sensing a logical 1 or a logical 0 at
`26 and has conductor 96 as its data output conductor.
`transitions G1 or G0, respectively.
`
`35
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`65
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`SANDISK Exhibit 1003
`Page 4 of 5
`
`

`

`4,019,068
`6
`5
`said bootstrap NOR circuit also being coupled to a
`However, if the subject RAM chip is not selected,
`second supply voltage conductor, said bootstrap
`then there is no negative transition of the RASwinput.
`NOR circuit including a first switching MOSFET
`Instead, the first event that occurs is the negative tran
`having its gate coupled to a first address control
`sition H of CASIw from a logical 1 to a logical 0. XA
`input, a second switching MOSFET having its gate
`remains at a logical 0 as indicated by J in FIG. 3. Thus,
`coupled to a second address control input, and a
`MOSFET 19 remains off, and node 15 remains at ap
`bootstrap load circuit coupled between said first
`proximately ground after CASIN undergoes transition
`MOSFET and said first and second switching MOS
`H.
`FETs;
`This causes MOSFETs 40 and 46 to remain in the off
`a second NOR circuit coupled between said first and
`condition. OL, at node 60, will still be at a logical 1
`second supply voltage conductors and having a
`level as a result of being charged to that level during the
`gate of a load MOSFET coupled to an output of
`previous selected memory cycle. Consequently, MOS
`said bootstrap NOR circuit, and having a third
`FET 36 will still be on. Therefore, when CASly under
`switching MOSFET having its gate coupled to said
`goes transition H, and MOSFET 30 is turned off, node
`first address control input and having a fourth
`28 undergoes a transition from approximately ground
`switching MOSFET having a gate coupled to said
`to Von volts. This causes MOSFET 42 to be turned on,
`second address control input;
`and since both MOSFETs 48 and 46 are in the off
`an output MOSFET having a drain coupled to said
`condition, OLD node 44, rises to Von volts, turning
`output latch circuit and to the gate of said first
`MOSFET 50 on (see transition K of the OLD waveform
`MOSFET, and having its source connected to said
`of FIG. 3). This causes OL to be discharged during
`20
`first supply voltage conductor and its gate con
`transition M. This in turn disables output latch 12 and
`nected to an output of said second NOR circuit;
`simultaneously turns MOSFET 36 off, so that disable
`an inverter coupled between said first and second
`circuit 14 dissipates no further power until the occur
`voltage supply conductors and having a second
`rence of a selected memory cycle. Output latch 12 is
`load MOSFET, said second load MOSFET having
`25
`disabled because OL is discharged to ground. Conse
`its gate coupled to circuitry generating a signal,
`quently, regardless of the stored state in latch 12, the
`which holds said second load MOSFET in an off
`output nodes 87 and 58' thereof are discharged to
`condition when said second address control input
`ground, turning off both MOSFETs 88 and 90. As a
`of said electronic memory circuit is not activated,
`result, data out conductor 86 is effectively electrically
`for selecting said electronic memory circuit, said
`30
`open, so that another RAM chip connected to the com
`inverter also including a switching MOSFET hav
`mon data conductor may be selected and may commu
`ing its gate coupled to said first address control
`input, said inverter having its output coupled to
`nicate with the common data bus without being inter
`ferred with by the subject unselected chip.
`said gate of said second switching MOSFET and to
`said gate of said fourth switching MOSFET.
`What is claimed is :
`1. An electronic circuit comprising:
`3. An output circuit for a random access memory
`a bootstrap inverting circuit including a switching
`comprising:
`MOSFET and a load MOSFET coupled in series,
`a first address control input;
`and a bootstrap capacitor charging MOSFET cou
`a second address control input;
`a first voltage conductor and a second voltage con
`pled to the gate of said load MOSFET;
`40
`a series MOSFET coupled in series between a first
`ductor;
`voltage supply conductor and a drain of said load
`a first conductor;
`a latch circuit coupled between said first conductor
`MOSFET;
`and said first voltage conductor;
`feedback circuit means coupled between an output
`first inverting means responsive to said first and sec
`of said bootstrap inverting circuit and a gate of said
`ond address control inputs and coupled between
`series MOSFET for controllably turning said series
`said first and second voltage conductor;
`MOSFET off in response to a signal applied to a
`coupling means coupled between said first inverting
`gate of said switching MOSFET to reduce power
`means and said second voltage conductor for elec
`dissipation of said bootstrap inverter circuit; and
`trically coupling or decoupling said first inverting
`said feedback means including inverting means re
`50
`sponsive to said signal and having an input coupled
`means on said second voltage conductor in re
`to said output of said bootstrap inverting circuit
`sponse to said first conductor;
`second inverting means responsive to said first and
`and having an output coupled to said gate of said
`second address control inputs and to said first in
`Series MOSFET,
`verting means for controlling said first conductor,
`2. In an electronic memory circuit, an output disable
`55
`thereby controlling said electrical coupling and
`circuit for disabling an output latch circuit comprising:
`decoupling.
`a bootstrap NOR circuit coupled in series between a
`first MOSFET and a first supply voltage conductor,
`
`::
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`::
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`:k
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`::
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`*k
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`10
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`15
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`35
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`45
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`60
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`65
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`SANDISK Exhibit 1003
`Page 5 of 5
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