`
`11111111111111101111111111!Iplpollig111111111111111110111111
`
`(12) United States Patent
`Lee et al.
`
`(to) Patent No.:
`(45) Date of Patent:
`
`US 7,006,019 B2
`Feb. 28, 2006
`
`(54) RATE-7/8 MAXIMUM TRANSITION RUN
`CODE ENCODING AND DECODING
`METHOD AND APPARATUS
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(75)
`
`Inventors: Jun Lee, Yongin-si (KR); Joo-hyun
`Lee, Seoul (KR); Jae-jin Lee, Seoul
`(KR); Byung-kyu Lee, Seoul (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Gyeonggi-do (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 115 days.
`
`(21) Appl. No.: 10/973,831
`
`(22) Filed:
`
`Oct. 27, 2004
`
`(65)
`
`Prior Publication Data
`
`US 2005/0116843 Al
`
`Jun. 2, 2005
`
`(30)
`
`Foreign Application Priority Data
`
`Oct. 27, 2003
`
`(KR)
`
`
`
` 10-2003-0075227
`
`(51) Int. Cl.
`H03M 7/00
`
`(2006.01)
`
`(52) U.S. Cl.
`
` 341/59; 341/50; 341/58
`
`(58) Field of Classification Search
`
` 341/50,
`341/58, 59
`See application file for complete search history.
`
`7/1988 Iketani et al.
`4,760,378 A *
`6,032,284 A * 2/2000 Bliss
`6,032,287 A * 3/2000 Kallas
`6,400,288 B1 *
`6/2002 Fredrickson et al.
`6,476,737 B1 * 11/2002 Caroselli et al.
`
`341/59
`341/59
`2/69
`341/59
`341/59
`
`* cited by examiner
`
`Primary Examiner—Lam T. Mai
`(74) Attorney, Agent, or Firm—Sughrue Mion, PLLC
`
`(57)
`
`ABSTRACT
`
`A rate 7/8 MTR code encoding/decoding method and appa-
`ratus. The encoding method includes: generating a rate-7/8
`MTR code for inputting 7-bit data and outputting a prede-
`termined 8-bit codeword; checking whether codewords sat-
`isfy a predetermined constraint condition by connecting the
`8-bit codeword and a subsequent 8-bit codeword; and if the
`codewords do not violate the constraint condition, not con-
`verting the codewords. The decoding method includes:
`checking whether the codewords satisfy a predetermined
`MTR constraint condition by connecting a current 8-bit
`codeword c(k) and a subsequent 8-bit codeword c(k+1); if
`the codewords violate the constraint condition, converting
`the codewords, and if the codewords do not violate the
`constraint condition, not converting the codewords; and
`decoding each converted 8-bit codeword into 7-bit data
`using a predetermined MTR code. Data is reliably repro-
`duced with high write density, and large amounts of data are
`stored in and reproduced from a magnetic recording infor-
`mation storage medium.
`
`14 Claims, 7 Drawing Sheets
`
`INPUT
`
`100
`
`7/8
`ENCODER
`
`Ck+1
`
`C
`
`110
`FIRST MTR
`VIOLATION CHECKING
`& CONVERTING UNIT
`
`Ck=nk
`
`/ 120
`PARALLEL—
`TO—SERIAL
`CONVERTER
`
`1/(1+D)
`PREDECODER
`
`z 30
`WRITE
`CHANNEL
`READ
`CHANNEL
`
`Z 20
`
`1
`
`160
`
`/ 150
`VITERBI
`SERIAL—TO
`DECODER
`WITH
`—PARALLEL ---
`CONVERTER
`COMBINED
`TRELLIS
`
`/ 140
`FOURTH
`ORDER
`PARTIAL
`RESPONSE
`EQUALIZER
`
`C k
`
`k+1
`
`_DJ
`
`/ 170
`SECOND MIR
`VIOLATION
`CHECKING &
`CONVERTING
`UNIT
`
`/ 180
`
`7/8
`DECODER
`
`OUTPUT
`
`L
`
`LSI Corp. Exhibit 1026
`Page 1
`
`

`

`Waled ' S 11
`
`L JO 1 lamIS
`
`ZS 6-10`900`L Sa
`
`J
`
`EQUALIZER
`RESPONSE
`PARTIAL
`ORDER
`FOURTH
`
`z 140
`
`CHANNEL
`
`READ
`
`CHANNEL
`
`WRITE
`
`z 30
`
`1
`
`20
`
`Z____
`150
`
`DECODER
`VITERBI
`
`TRELLIS
`COMBINED
`
`WITH
`
`CONVERTER
`—PARALLEL
`SERIAL—TO
`
`r 160
`
`n k+1
`
`....-
`
`Ck
`
`CONVERTING
`CHECKING &
`VIOLATION
`SECOND MTR
`170
`
`UNIT
`
`2i
`
`L
`
`DECODER
`
`7/8
`
`180
`
`OUTPUT
`
`PREDECODER
`
`1/(1+D)
`
`z 130
`
`_z10
`
`CONVERTER
`TO—SERIAL
`PARALLEL—
`z120
`
`nk
`
`—
`
`FIG. 1
`
`& CONVERTING UNIT
`VIOLATION CHECKING
`
`FIRST MTR
`110
`
`r
`
`6 k
`
` C k+1
`
`ENCODER
`
`7/8
`
`
`
`z 100
`
`r
`
`r
`
`INPUT
`
`LSI Corp. Exhibit 1026
`Page 2
`
`

`

`U.S. Patent
`
`Feb. 28, 2006
`
`Sheet 2 of 7
`
`US 7,006,019 B2
`
`FIG. 2
`
`Source
`
`Codeword
`
`Source
`
`Codeword
`
`Source
`
`Codeword
`
`Source
`
`Codeword
`
`0000000
`
`00000010
`
`0100000
`
`00110101
`
`1000000
`
`10000010
`
`1100000
`
`10110101
`
`0000001
`
`00000100
`
`0100001
`
`00110110
`
`1000001
`
`10000100
`
`1100001
`
`10110110
`
`0000010
`
`00000101
`
`0100010
`
`01000001
`
`1000010
`
`10000101
`
`1100010
`
`00000011
`
`0000011
`
`00000110
`
`0100011
`
`01000010
`
`1000011
`
`10000110
`
`1100011
`
`00001011
`
`0000100
`
`00001000
`
`0100100
`
`01000100
`
`1000100
`
`10001000
`
`1100100
`
`00010011
`
`0000101
`
`00001001
`
`0100101
`
`01000101
`
`1000101
`
`10001001
`
`1100101
`
`00100011
`
`0000110
`
`00001010
`
`0100110
`
`01000110
`
`1000110
`
`10001010
`
`1100110
`
`00101011
`
`0000111
`
`00001100
`
`0100111
`
`01001000
`
`1000111
`
`10001100
`
`1100111
`
`00110011
`
`1001000
`
`0001000
`
`00001101
`
`0101000
`
`01001001
`
`10001101
`
`1101000
`
`01000011
`
`0001001
`
`00010000
`
`0101001
`
`01001010
`
`1001001
`
`10010000
`
`1101001
`
`01001011
`
`0001010
`
`00010001
`
`0101010
`
`01001100
`
`1001010
`
`10010001
`
`1101010
`
`01010011
`
`0001011
`
`00010010
`
`0101011
`
`01001101
`
`1001011
`
`10010010
`
`1101011
`
`01100011
`
`0001100
`
`00010100 1 0101100 01010000 1001100 10010100 1101100 01101011
`
`0001101 00010101 0101101 01010001
`
`1001101
`
`10010101
`
`1101101
`
`10000011
`
`0001110 00010110 0101110 01010010 1001110 10010110 1101110 10001011
`
`0001111 00011000 0101111 01010100 1001111
`
`10011000 1101111 10010011
`
`0010000 00011001 0110000 01010101 1010000 10011001
`
`1110000 10100011
`
`0010001 00011010 0110001 01010110 1010001
`
`10011010 1110001 10101011
`
`0010010 00100001 0110010 01011000 1010010 10100001
`
`1110010 10110011
`
`0010011 00100010 0110011 01011001
`
`1010011
`
`10100010 1110011 11010001
`
`0010100 00100100 0110100 01011010 1010100 10100100 1110100 11010010
`
`0010101 00100101 0110101 01100001
`
`1010101
`
`10100101
`
`1110101
`
`11010011
`
`0010110 00100110 0110110 01100010 1010110 10100110 1110110 11010100
`
`0010111 00101000 0110111 01100100 1010111
`
`10101000 1110111 11010101
`
`0011000 00101001 0111000 01100101 1011000 10101001
`
`1111000 11010110
`
`0011001 00101010 0111001 = 01100110 1011001
`
`10101010 1111001 11011000
`
`0011010 00101100 0111010 01101000 1011010 10101100 1111010 11011001
`
`0011011 00101101 0111011 01101001
`
`1011011
`
`10101101
`
`1111011 11011010
`
`0011100 00110000 0111100 01101010 1011100 10110000 1111100 00011011
`
`0011101 00110001 0111101 01101100 1011101
`
`10110001
`
`1111101 01011011
`
`0011110 00110010 0111110 01101101 1011110 10110010 1111110 10011011
`
`0011111 00110100 1 0111111
`
`10000001
`
`1011111
`
`10110100 1 1111111 11011011
`
`LSI Corp. Exhibit 1026
`Page 3
`
`

`

`U.S. Patent
`
`Feb. 28, 2006
`
`Sheet 3 of 7
`
`US 7,006,019 B2
`
`FIG. 3
`
`Cic
`
`Ck+i
`
`x 7 X6 x 5 x 4 x 3 x2
`
`v
`xo Y7 Y6 Y5 Y41 Y3
`
`Y2 YI Yo
`
`Encoding
`
`Decoding
`
`= xi + xo +y7 +y6 +y5 +y4
`= xi xo Y7- Y6 - Y4
`
`Z0 = X0 •y 7 Y6 Y4
`
`Z1 = X i - y 7 - y6 • Y4
`
`IF zo = 0 I_ IF zi =
`
`IF zo =I IFz =1
`
`x o
`
`Y7 }
`
`Y6
`
`1
`
`X0
`
`Y4
`
`0
`
`xo
`Y7 }
`
`0
`
`X0
`
`Y4
`
`I
`
`LSI Corp. Exhibit 1026
`Page 4
`
`

`

`U.S. Patent
`
`Feb. 28, 2006
`
`Sheet 4 of 7
`
`US 7,006,019 B2
`
`FIG. 4
`
`(a) j=2
`
`(b) j=3
`
`LSI Corp. Exhibit 1026
`Page 5
`
`

`

`U.S. Patent
`US. Patent
`
`Feb. 28, 2006
`Feb. 28, 2006
`
`Sheet 5 of 7
`Sheet 5 0f 7
`
`US 7,006,019 B2
`US 7,006,019 B2
`
`.\Q0.
`
`s!
`
`xiv/A’
`
`“1““
`
`
`.’oA.i..o..o.
`
`
`.\‘.\/\‘§/‘.\.\.sT-as.\{gs
`~»~/\/WI,”Ifu«AWA0A“Aox
`
`31%..”.§§i§é§¢§H-
`§w§@p~xfi$stm:\~
`
`
`;#9o.\’lAQ.‘oliAQ‘V’HmO/\\\lo.
`
`¢|\\v\‘\\\"‘4""++X“.§a\%.fi.m-H
`‘.‘‘11++
`
`“I
`
`’i
`
`d
`
`P
`
`O
`
`•
`I
`I
`I +
`I
`1
`1
`1
`I
`I
`I +
`I
`+ +
`+
`1 + +
`I
`+
`+
`1
`I
`1 +
`I +
`+
`1 +
`1
`
`+lll
`
`•
`+ +
`+ +
`I
`I
`I +
`+ +
`1
`I
`+
`+
`1
`I
`
`+
`+
`+
`+ + +
`+
`+
`I
`+
`+
`I
`
`LSI Corp. Exhibit 1026
`
`Page 6
`
`LSI Corp. Exhibit 1026
`Page 6
`
`

`

`U.S. Patent
`
`Feb. 28, 2006
`
`Sheet 6 of 7
`
`US 7,006,019 B2
`
`FIG. 6
`
`as
`
`I.
`
`...... ass•a•r.
`
`- - -
`
`10" .
`
`-1
`10
`
`O
`
`-4
`
`I
`
`••••• 819 code+EEPR4ML
`-e- 718 code+EEPR4ML
`-.4- 718 code+EEPR4ML with k3 trellis
`-IN- 718 code+EEPR4ML with combined trellis
`-6
`10
`0
`10
`
`E
`b
`
`IND (dB)
`
`15
`
`FIG. 7
`
`10'
`
`101
`
`-2
`
`a. wO1
`
`2.02629,6
`
`.......
`
`2St•
`
`10-5 --e-- 819 code+PR(12321)ML
`-e- 718 code+PR(12321)ML
`-.4- 718 code+PR(12321) with k3 trellis
`-al- 718 code+PR(12321) with combined trellis
`10
`10
`15
`20
`EbiNo (dB)
`
`. .
`....
`
`
`
`..
`-:.,
`
`1
`25
`
`27
`
`LSI Corp. Exhibit 1026
`Page 7
`
`

`

`U.S. Patent
`
`Feb. 28, 2006
`
`Sheet 7 of 7
`
`US 7,006,019 B2
`
`FIG. 8
`
`e
`10
`
`101
`
`-2
`W 10
`0-
`
`ti
`
`L• lit
`
`• 96,
`
`...
`
` 104
`
`.....
`
`10s --e-• 8/9 code+PR(12321)ML
`—0-- 718 code+PR(12321)ML
`—A— 718 code+PR(12321)ML with j=3 trellis
`—m— 7/8 code+PR(12321)ML with combined trellis
`10e
`10
`15
`20
`
`EbINO (dB)
`
`25
`
`LSI Corp. Exhibit 1026
`Page 8
`
`

`

`US 7,006,019 B2
`
`1
`RATE-7/8 MAXIMUM TRANSITION RUN
`CODE ENCODING AND DECODING
`METHOD AND APPARATUS
`
`BACKGROUND OF THE INVENTION
`
`5
`
`2
`technology will now be
`A rate-4/5 MTR coding
`described. In a rate-4/5 MTR code building method, C)
`codewords including a `111' pattern are removed from all
`codewords composed of 5 bits, C) by removing codewords
`including a `11' pattern at a beginning part or an ending part,
`a condition j=2 can be satisfied when a code sequence is
`composed, and C) a codeword `00000' is removed so as not
`to allow a codeword where k=c to be generated.
`According to the method, since the number of acceptable
`10 codewords is 16, a rate-4/5 code can be built, and the highest
`acceptable value of k in the code is 8 as shown in Table. 2.
`
`This application claims the priority of Korean Patent
`Application No. 2003-75227, filed on Oct. 27, 2003, in the
`Korean Intellectual Property Office, the disclosure of which
`is incorporated herein in its entirety by reference.
`1. Field of the Invention
`The present invention relates to coding and signal pro-
`cessing for a high density magnetic recording system, and
`more particularly, to a maximum transition run (MTR) code
`encoding and decoding method and apparatus suitable for a
`high density recording system.
`2. Description of the Related Art
`Conventional codes include a general modulation code
`and a relatively low rate maximum transition run (MTR)
`code. Examples of general modulation codes used for hard
`disc drives of magnetic recording systems include a rate-8/9
`code and a rate-16/17 code. In the rate-8/9 code and the
`rate-16/17 code, since the number of consecutive data tran-
`sitions increases and recording density increases, a decrease
`in data detection performance is caused, and an increase in
`recording density is limited.
`To solve these problems, recent development efforts have
`focused on MTR coding technologies. In a conventional
`MTR code, to allow improvement of detection performance
`in a high density write channel, code technologies where the
`number of consecutive data transitions is equal to or less
`than 2 have been developed. However, an increase in a code
`rate is limited.
`An MTR coding technology will be described in brief. A
`run-length limited (RLL) modulation code is most fre-
`quently used in magnetic or optical recording/reproducing
`systems. In the RLL code, a (d, k) constraint condition
`allows a generation interval of transition in a modulated
`non-return-to-zero
`inversion (NRZI) waveform
`to be
`between at least (d+1) bits and at most (k+1) bits by
`allowing the number of consecutive `Os' between any two
`ls' to be between at least d and at most k. The (d, k) code
`allows inter-symbol interference (ISI) to decrease and sim-
`plifies timing recovery.
`The MTR code dramatically improves a detection perfor-
`mance as compared with a conventional recording (0, k)
`code by improving a minimum distance characteristic for
`recorded data in a high density magnetic recording system.
`By preventing 3 or more consecutive recording transitions
`from being generated, 4/5, 5/6, and 6/7 coding technologies
`have been developed. These codes have relatively high code
`rates while having detection performance gains similar to a
`gain of a (1, 7) code. Here, if the maximum number of
`acceptable transitions (j) is 2, a capacity of the MTR code is 55
`obtained according to a k value as shown in Table. 1.
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`TABLE 2
`
`Rate-4/5 MTR (j = 2; k = 8) code table
`
`00001.-1
`00010.-1
`00100.1
`00101.-1
`
`00110.-1
`01000.-1
`10000,-1
`01010,-1
`
`01100.1
`01101.-1
`10000.1
`10001.-1
`
`10010.-1
`10100.]
`10101,1
`10110.]
`
`A rate-5/6 MTR code conversion table is shown in Table.
`3.
`
`TABLE 3
`
`Conversion table of a rate-5/6 MTR (j = 2; k = 6) code
`
`"STATE-0"
`Conversion Table.J
`
`"STATE-1"
`Conversion Table.-1
`
`Input.]
`
`Output.]
`
`Input.]
`
`Output.]
`
`00000.-1
`00001.1
`00010.-1
`00011.-1
`00100.-1
`00101.1
`00110.1
`00111,1
`01000.-1
`01001.1
`01010.--1
`01011.]
`01100.-1
`01110.1
`01111,-1
`10000.]
`10001.1
`10010.1
`10011,-1
`10100.]
`10101.1
`10110.-1
`11000,-1
`11001.-1
`11010.-1
`11011.,J
`11100.-1
`11101.-1
`11110.-1
`11111.,J
`
`000000.]
`000001.1
`000010.-1
`000001._1
`000100.]
`000101.1
`000110.J
`100101.]
`001000.-1
`001001.1
`001010.]
`100100._1
`001100.-1
`001101.J
`100010.]
`100000._1
`010000.1
`010001.1
`010100.]
`010101._1
`010110.-1
`101101.-1
`011000,1
`011001,-1
`011010.-1
`101100.-1
`101000._1
`101010.-1
`110100.-1
`110101.J
`
`00000,-1
`00001.-1
`00010.-1
`00011.--1
`00100.-1
`00101.-1
`00110.-1
`00111.]
`01000,-1
`01001.-1
`01010,-1
`01011.--1
`01100.1
`01110.1
`01111.]
`10000.1
`10001.-1
`10010.-1
`10011.]
`10100.1
`10101.-1
`10110.1
`11000.]
`11001.-1
`11010.1
`11011.-1
`11100.1
`11101.--1
`11110.1
`11111.-1
`
`000000,-1
`000001.-1
`000010.-1
`000001.1
`000100.-1
`000101.-1
`000110.-1
`100101.1
`001000,1
`001001.J
`001010.J
`100100.1
`001100.J
`001101.J
`100010.J
`100000.1
`010000.-1
`010001.-1
`010100,-1
`010101.1
`010110.1
`101101.J
`011000.]
`011001._1
`011010.J
`101100.-1
`101000.1
`101010,1
`110010.1
`110110.-1
`
`TABLE 1
`
`Capacity of an MTR (j = 2) code
`
`K
`
`4
`5
`6
`7
`
`Capacity
`
`0.8376
`0.8579
`0.8680
`0.8732
`
`k
`
`8
`9
`10
`
`Capacity
`
`0.8760
`0.8774
`0.8782
`0.8791
`
`Table. 3 shows a rate-5/6 MTR (j=2) code. The rate-5/6
`MTR j=2) code is converted using conversion tables divided
`into two states, and an encoding and decoding method is as
`follows: C) To allocate a code to each of 25 (32) possible
`input data, each of "STATE-0" and "STATE-1" includes 30
`codes. 5-bit input data is encoded by selecting one of two
`conversion states. The last two codewords of "STATE-0"
`and "STATE-1" are different from each other, and state
`selection is determined according to whether the least sig-
`nificant bit of an encoded previous codeword is `0' or `1'. In
`other words, if the least significant bit of the previous
`
`60
`
`65
`
`LSI Corp. Exhibit 1026
`Page 9
`
`

`

`US 7,006,019 B2
`
`3
`codeword is `0', input data is converted to a codeword of
`"STATE-0", and if the least significant bit of the previous
`codeword is `1', input data is converted to a codeword of
`"STATE-1". C) When "STATE-1" is selected, if input data
`is `11110'or `11111', a least significant bit of a previous
`codeword is converted to `0' to satisfy a j=2 constraint
`condition. ® If an encoded 6-bit output is `000000' and a
`most significant bit of a subsequent codeword is `0', the last
`two bits of a current codeword are converted to `1'. ® If a
`least significant bit of a previous codeword is `0' and the first
`5 bits of a current codeword are `0', the first 2 bits of the
`current codeword are converted to `1'. ®
`If 7 or more
`consecutive Os span between a last portion of a previous
`codeword and a first portion of a current codeword and the
`condition of the item ® is not satisfied, the last two bits of
`the previous codeword are converted to `1'. Accordingly, the
`highest acceptable value of k in the code is 6. C) When
`decoding is performed, if the last two bits of a codeword are
`l', the bits are converted to `00', and if the first 5 bits of a
`codeword are `11000', the bits are converted to `00000'.
`Also, if the first 3 bits of a current codeword are `HO' and
`the last 2 bits are `10', a least significant bit `0' of a previous
`codeword is converted to `1'. Likewise, after a conversion
`process corresponding to each condition is performed, an
`input corresponding to each codeword is decoded using the
`code table.
`A rate-6/7 MTR code building method includes the fol-
`lowing steps: ® Codewords including a `111' pattern
`among all codewords composed of 7 bits are removed. C) If
`a k-constraint condition is not considered, the number of
`valid codewords not including `11' at the first 2 bits or last
`2 bits is 57. Therefore, to build codewords for 6-bit inputs,
`at least 7 (26-57) additional codewords are necessary. C) To
`build 64 codewords, 9 codewords, each beginning with `110'
`and satisfying a j=2 MTR condition at the other 4 bits, that
`is, '1100000', '1100001', `1100010', `1100100', `1100101',
``1100110', `1101000', `1101001', and `1101010', are con-
`sidered. ® When the 9 additional codewords are used, if a
`least significant bit of a previous codeword is `0', the MTR
`constraint condition is satisfied. However, if the least sig-
`nificant bit of the previous codeword is l', to satisfy a j=2
`condition, the last 3 bits of the previous codeword and the
`first 3 bits `110' of a current codeword are converted as
`follows:
`. . 011,001 . . .
`. . . 001,110 . . .
`. . 011,010 . . .
`. . . 101,110 . . .
`® So as not to generate a codeword where k=c among
`66 available codewords, a codeword `0000000' is removed.
`Here, since the longest length of consecutively generated
``Os' is `1000000,0000001', a maximum run-length is 12 bits.
`C) To reduce the k-condition more, codewords are con-
`verted as follows:
`. . 011,000 . . .
`. . . 000,000 . . .
`If the codewords are converted as shown above, since the
`longest length of consecutively generated `Os' is `1000000,
`001 . . . ' or
`. . . 100,0000001', k becomes 8. ® A decoding
`process of an encoded code sequence is achieved by per-
`forming these steps in reverse order.
`According to the code built according to the above
`method, the number of available codewords is 65. Accord-
`ingly, a rate-6/7 code table can be built by selecting 64
`codewords out of the 65 codewords listed in Table 4, and the
`highest acceptable value of k in the code is 8.
`
`4
`
`TABLE 4
`
`5
`
`10
`
`15
`
`20
`
`Rate-6/7 MTR (j = 2; k = 8) code table
`
`0001000J
`0000001.J
`0000010.J
`0001001,J
`0000100,J
`0000101.J
`0000110.J
`0001010,J
`0011000.]
`0010001.J
`0010010.J
`0011001.]
`0010100.-1
`0010101.]
`0010110.J
`0011010,1
`
`0101000,J
`0100001.J
`0100010.J
`0101001.]
`0100100.]
`0100101.J
`0100110.-1
`0101010,J
`0110001.J
`0010000.J
`0100000.-1
`0110000.J
`1000000.-1
`1010000.J
`1100000.-1
`0110010.J
`
`1001000.]
`1000001.J
`1000010.J
`1001001J
`1000100.J
`1000101.J
`1000110.J
`1001010J
`1011000,J
`1010001.J
`1010010 .J
`1011001,J
`1010100.]
`1010101.J
`1010110.J
`1011010._1
`
`1101000.J
`1100001J
`1100010.J
`1101001J
`1100100J
`1100101J
`1100110.-1
`1101010.J
`0001100.]
`0001101J
`0101100.1
`0101101._I
`1001100.]
`1001101.J
`0110100.J
`0110101,1
`
`SUMMARY OF THE INVENTION
`
`The present invention provides a rate-7/8 MTR code
`encoding/decoding method and apparatus for limiting the
`25 number of data transitions to be 2 or less in each codeword
`and allowing the number of data transitions to be at most 3
`at necessary boundaries when codewords are consecutively
`input, in order to achieve a relatively higher code rate than
`conventional MTR codes where the number of data transi-
`30 tions is 2 or less while improving detection performance
`compared to conventional general modulation codes.
`According to an exemplary embodiment of the present
`invention, there is provided a rate-7/8 MTR code encoding
`method comprising: generating a rate-7/8 MTR code for
`35 inputting 7-bit data and outputting a predetermined 8-bit
`codeword; checking whether codewords satisfy a predeter-
`mined constraint condition by connecting the 8-bit code-
`word and a subsequent 8-bit codeword; and converting the
`codewords if the codewords violate the constraint condition
`40 and not converting the codewords if the codewords do not
`violate the constraint condition. The rate-7/8 MTR code
`comprises: 98 codewords remaining after excluding
``00000000',
`00000001',
``00100000',
``01000000',
``01100000', `10000000', and `10100000' from 105 code-
`45 words each including no more than one `1' at the first two
`bits thereof and no more than one `1' at the last two bits
`thereof so that an MTR constraint condition (j=2) indicating
`allowable consecutive data transitions is satisfied when
`codewords are consecutively input, among 256 8-bit code-
`so words; and 30 codewords obtained by excluding the code-
`word `11010000' and 13 codewords beginning with `1100'
`from 44 codewords beginning with `HO' or ending with
``OH'.
`The checking of whether the codewords satisfy the pre-
`55 determined constraint condition comprises: when a code-
`word is connected to one of the 128 codewords and it is
`assumed that c(k) represents a current codeword to be
`checked to determine whether or not the constraint condition
`is violated and c(k+1) represents a subsequent codeword,
`60 determining whether the last 2 bits (x1, x0) of the current
`codeword and the first 4 bits (y7, y6, y5, y4) of the subsequent
`codeword violate the MTR constraint condition. The con-
`verting of the codewords comprises: when it is assumed that
`z0 indicates a parameter for determining whether the num-
`65 ber of consecutive `O's is equal to or less than 7 and zl
`indicates a parameter for determining whether codewords
`satisfy a constraint condition (j=3), calculating z0 and zl
`
`LSI Corp. Exhibit 1026
`Page 10
`
`

`

`US 7,006,019 B2
`
`6
`bits thereof and no more than one `1' at the last two bits
`thereof so that an MTR constraint condition (j=2) indicating
`allowable consecutive data transitions is satisfied when
`codewords are consecutively input, among 256 8-bit code-
`5 words; and 30 codewords obtained by excluding the code-
`word `11010000' and 13 codewords beginning with `1100'
`from 44 codewords beginning with `110'or ending with
``011'.
`The checking of whether the codewords satisfy the pre-
`10 determined MTR constraint condition comprises: when a
`codeword is connected to one of the 128 codewords and it
`is assumed that c(k) represents a current codeword to be
`checked to determine whether or not the constraint condition
`is violated and c(k+1) represents a subsequent codeword,
`15 determining whether the last 2 bits (x1, x0) of the current
`codeword and the first 4 bits (y7, y6, y5, y4) of the subsequent
`codeword violate the MTR constraint condition. The con-
`verting or not converting the codewords comprises: when it
`is assumed that z0 indicates a parameter for determining
`20 whether the number of consecutive `O's is equal to or less
`than 7 and z1 indicates a parameter for determining whether
`codewords satisfy a constraint condition (j=3), calculating z0
`and z1 using z0=xo *Y7*Y6'3'4, zi=x,:y7.y6.y4; when z0=0,
`converting x0, y7, and y6 to 0 to satisfy k=7; and when z1=1,
`25 converting x0 and y4 to 1 so that j does not exceed 3.
`The currently input codeword is equalized by an output of
`a reproducing channel, and the equalized result is decoded
`by input to a Viterbi decoder having a trellis obtained by
`combining a j=2 trellis and a j=3 trellis. The combined trellis
`30 is a modified j =3 trellis allowing 3 consecutive bits from a
`beginning bit of a boundary between connected codewords
`to satisfy a j=3 condition.
`In the rate-7/8 MTR code decoding method, the fourth bit
`(x4) through the LSB (x0) of the current codeword are
`35 decoded using the j=2 trellis, and to apply the j=3 trellis to
`the first two bits y7 and y6 of the subsequent codeword, a
`trellis corresponding to y7 is obtained by calculating the
`following additional branch metrics in the j=2 trellis
`
`5
`using zo=xi+xo+y7+y,+y,+y„, zi=xi•xo•y7.y,•y, (here,
`+indicates a modular-2 add operation); when z0=0, convert-
`ing x0, y7, and y6 to 1 to satisfy k=7; and when z1=1,
`converting x0 and y4 to 0 so that j does not exceed 3.
`According to another exemplary embodiment of the
`present invention, there is provided a rate-7/8 MTR code
`encoding apparatus comprising: a 7/8 encoder generating a
`rate-7/8 MTR code for inputting 7-bit data and outputting a
`predetermined 8-bit codeword; and an MTR violation
`checking & converting unit checking whether codewords
`satisfy a predetermined constraint condition by connecting
`the 8-bit codeword and a subsequent 8-bit codeword, con-
`verting specific bits of the codewords if the codewords
`violate the constraint condition, and not converting the
`codewords if the codewords do not violate the constraint
`condition. The rate-7/8 MTR code comprises: 98 codewords
`remaining after excluding
``00000000',
``00000001',
``00100000', `01000000', `01100000', `10000000', and
``10100000' from 105 codewords each including no more
`than one `1' at the first two bits thereof and no more than one
``1' at the last two bits thereof so that an MTR constraint
`condition (j=2) indicating allowable consecutive data tran-
`sitions is satisfied when codewords are consecutively input,
`among 256 8-bit codewords; and 30 codewords obtained by
`excluding the codeword `11010000' and 13 codewords
`beginning with `1100' from 44 codewords beginning with
``110'or ending with `011'.
`When a codeword is connected to one of the 128 code-
`words and it is assumed that c(k) represents a current
`codeword to be checked to determine whether or not the
`constraint condition is violated and c(k+1) represents a
`subsequent codeword, checking of the MTR constraint
`condition in the MTR violation checking & converting unit
`is achieved by determining whether the last 2 bits (x1, x0) of
`the current codeword and the first 4 bits (y7, y6, y5, y4) of the
`subsequent codeword violate the MTR constraint condition,
`and when it is assumed that z0 indicates a parameter for
`determining whether the number of consecutive O's is equal
`to or less than 7 and z1 indicates a parameter for determining
`whether codewords satisfy a constraint condition (j=3), the 40
`codeword conversion in the MTR violation checking &
`converting unit is achieved by calculating z0 and z1 using
`z0=xi +x0+y7+y6+y,+y,, =xi • x0.y7.y6. y, (here, +indicates
`a modular-2 add operation), converting x0, y7, and y6 to 1 to
`satisfy k=7 when z0=0, and converting x0 and y4 to 0 so that
`j does not exceed 3 when z1=1.
`The rate-7/8 MTR code encoding apparatus can further
`comprise: a parallel-to-serial converter converting parallel
`codewords of the MTR violation checking & converting unit
`to serial data; and a precoder changing a signal level of the 50
`serial data in order to record the serial data in a channel.
`According to another exemplary embodiment of the
`present invention, there is provided a rate-7/8 MTR code
`decoding method comprising: when it is assumed that c(k)
`represents a currently input 8-bit codeword and c(k+1) 55
`represents a subsequently input 8-bit codeword, checking
`whether the codewords satisfy a predetermined MTR con-
`straint condition by connecting c(k) and c(k+1); if the
`codewords violate the MTR constraint condition, converting
`the codewords, and if the codewords do not violate the MTR
`constraint condition, not converting the codewords; and
`decoding each converted 8-bit codeword into 7-bit data
`using a predetermined MTR code. The rate-7/8 MTR code
`comprises: 98 codewords remaining after excluding
``00000000',
``00000001',
``00100000',
``01000000',
``01100000', `10000000', and `10100000' from 105 code-
`words each including no more than one `1' at the first two
`
`45
`
`BM(ak=-Fllak_1=-1, ak_2=41, ak_3=-1, ak_4=-1)
`
`BM(ak=-11ak_1=41, ak_2=-1, ak_3=41, ak_4=41)
`
`a trellis corresponding to y6 is obtained by calculating the
`following additional branch metrics in the j =2 trellis
`
`BM(ak=-Fllak_1=-1, ak_2=41, ak_3=-1, ak_4=-1)
`
`BM(ak=-Fllak_1=41, ak_2=-1, ak_3=41, ak_4=-1)
`
`BM(ak=-1Iak_1=-1, ak_2=41, ak_3=-1, ak_4=41)
`
`BM(ak=-11ak_1=41, ak,=-1, ctk_3=-F1, ak_4=41)
`
`and a trellis corresponding to y5 is obtained by calculating
`the following additional branch metrics in the j=2 trellis
`
`BM(ak=-Fllak_1=41, ak_2=-1, ak_3-F1, ak_4=-1)
`
`BM(ak=-1Iak_1-1, ak,-+1, ak_3-1, ak_4=41)
`
`According to another aspect of the present invention,
`there is provided a rate-7/8 MTR code decoding apparatus
`60 comprising: an MTR violation checking & converting unit,
`when it is assumed that c(k) represents a currently input 8-bit
`codeword and c(k+1) represents a subsequently input 8-bit
`codeword, checking whether the codewords satisfy a pre-
`determined MTR constraint condition by connecting c(k)
`65 and c(k+1), and if the codewords violate the MTR constraint
`condition, converting the codewords, and if the codewords
`do not violate the MTR constraint condition, not converting
`
`LSI Corp. Exhibit 1026
`Page 11
`
`

`

`US 7,006,019 B2
`
`8
`FIG. 6 is a graph used to compare BER performances in
`a linear horizontal magnetic write channel;
`FIG. 7 is a graph used to compare BER performances in
`a linear vertical magnetic write channel; and
`FIG. 8 is a graph used to compare BER performances in
`a non-linear horizontal magnetic write channel.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`5
`
`7
`the codewords; and a 7/8 decoder decoding each 8-bit
`codeword output from the MTR violation checking & con-
`verting unit into 7-bit data using a predetermined MTR code.
`The rate-7/8 MTR code comprises: 98 codewords remaining
`after excluding `00000000', 00000001', `00100000',
``01000000', `01100000', `10000000', and `10100000' from
`105 codewords each including no more than one `1' at the
`first two bits thereof and no more than one `1' at the last two
`bits thereof so that an MTR constraint condition (j=2)
`indicating allowable consecutive data transitions is satisfied to
`when codewords are consecutively input, among 256 8-bit
`codewords; and 30 codewords obtained by excluding the
`codeword `11010000' and 13 codewords beginning with
``1100' from 44 codewords beginning with `110'or ending
`with `011'.
`When a codeword is connected to one of the 128 code-
`words and it is assumed that c(k) represents a current
`codeword to be checked to determine whether or not the
`constraint condition is violated and c(k+1) represents a
`subsequent codeword, checking of the MTR constraint
`condition in the MTR violation checking & converting unit
`is achieved by determining whether the last 2 bits (x1, xo) of
`c(k) and the first 4 bits (y7, y6, y5, y4) of c(k+1) violate the
`MTR constraint condition. When it is assumed that zo
`indicates a parameter for determining whether the number of
`consecutive O's is equal to or less than 7 and z1 indicates a
`parameter for determining whether codewords satisfy a
`constraint condition (j=3), the codeword conversion in the
`MTR violation checking & converting unit is achieved by
`calculating zo and z1 using zo=xo*Y7*Y6*Y4, zi=xi*Y7*Y6*Y4,
`converting xo, y7, and y6 to 0 to satisfy k=7 when zo=0, and
`converting xo and y4 to 1 so that j does not exceed 3 when
`z1=1.
`The rate-7/8 MTR code decoding apparatus can further
`comprise: a fourth order partial response equalizer equaliz-
`ing data received through a channel to compensate a repro-
`ducing characteristic of the channel with respect to a cur-
`rently input 8-bit codeword and a subsequent 8-bit
`codeword; a Viterbi decoder including a trellis obtained by
`combining a j=2 trellis and a j=3 trellis, which is a modified
`j=3 trellis allowing consecutive 3 bits from a beginning bit
`of a boundary between connected codewords to satisfy a j=3
`condition, and Viterbi decoding the equalized result using
`the combined trellis; and a serial-to-parallel converter con-
`verting serial data of the Viterbi decoder to parallel data.
`According to another exemplary embodiment of the
`present invention, there is provided a computer readable
`medium having recorded thereon a computer readable pro-
`gram for performing a method described above.
`
`30
`
`Hereinafter, the present invention will now be described
`more fully with reference to the accompanying drawings, in
`which embodiments of the invention are shown.
`FIG. 1 is a block diagram of a rate-7/8 MTR encoding and
`is decoding apparatus according to an embodiment of the
`present invention.
`Referring to FIG. 1, a rate-7/8 MTR encoding apparatus
`10 includes a 7/8 encoder 100, a first MTR violation
`checking & converting unit 110, a parallel-to-serial con-
`20 verter 120, and a precoder 130.
`The 7/8 encoder 100 generates a rate 7/8 MTR code for
`outputting a predetermined 8-bit codeword from 7-bit data.
`The first MTR violation checking & converting unit 110
`checks whether codewords satisfy a predetermined con-
`25 straint condition by connecting the 8-bit codeword and a
`subsequent 8-bit codeword, converts specific bits of the
`codewords if the codewords violate the MTR constraint
`condition, and does not convert the codewords if the code-
`words do not violate the constraint condit