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` Paper 87
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` Entered: July 31, 2018
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`Trials@uspto.gov
`571-272-7822
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`v.
`R2 SEMICONDUCTOR, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00705
`Case IPR2017-00706
`Case IPR2017-01123
`Patent 8,233,250 B2
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`Before JAMESON LEE, JEAN R. HOMERE, and JENNIFER S. BISK,
`Administrative Patent Judges.
`
`BISK, Administrative Patent Judge.
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`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`Case IPR2017-00705
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`Patent 8,233,250 B2
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`INTRODUCTION
`I.
`Intel Corporation (“Petitioner”) filed three petitions requesting inter
`partes review of U.S. Patent No. 8,233,250 B2 (Ex. 1001, “the ’250
`patent”). IPR2017-00705, Paper 4 (“Pet.”); IPR2017-00706, Paper 4 (“’706
`Pet.”); IPR2017-01123, Paper 4 (“’1123 Pet.”). In each case we instituted a
`trial on all challenged claims resulting in review of all claims, 1–31, of the
`’250 patent.1 IPR2017-00705, Paper 10 (“Inst. Dec.”); IPR2017-00706,
`Paper 10 (“’706 Inst. Dec.”); IPR2017-01123, Paper 10 (“’1123 Inst. Dec.”).
`Patent Owner filed a Patent Owner Response in each case. IPR2017-
`00705, Paper 35 (“PO Resp.”); IPR2017-00706, Paper 35 (“’706 PO
`Resp.”); IPR2017-01123, Paper 35 (“’1123 PO Resp.”). Similarly,
`Petitioner filed a Reply in each case. IPR2017-00705, Paper 62 (“Reply”);
`IPR2017-00706, Paper 62 (“’706 Reply”); IPR2017-01123, Paper 58
`(“’1123 Reply”).2
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`1 Claims 1–4, 7–9, 13–17, 20–22, and 29 were reviewed in IPR2017-00705,
`claims 10–12, 23–26, 28, and 31 were reviewed in IPR2017-00706, and
`claims 5, 6, 18, 19, 27, and 30 were reviewed in IPR2017-01123.
`2 Both parties also filed in each case a Motion to Exclude Evidence, each of
`which was fully briefed. IPR2017-00705, Papers 70, 71, 73, 74, 77, 78;
`IPR2017-00706, Papers 71, 72, 74, 75, 78, 79; IPR2017-01123, Papers 71,
`72, 74, 75, 78, 79. Subsequently, the parties withdrew each of these
`motions. IPR2017-00705, Paper 83; IPR2017-00706, Paper 84; IPR2017-
`01123, Paper 84.
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`In each case, Patent Owner filed a Contingent Motion to Amend, each
`of which was fully briefed.3 IPR2017-00705, Papers 30, 49, 58, 69;
`IPR2017-00706, Papers 66, 49, 58, 70; IPR2017-01123, Papers 30, 49, 58,
`69.
`
`A transcript of the consolidated oral hearing held on February 8, 2018,
`has been entered into the record as Paper 844 (“Tr.”).
`Because of the substantial overlap in substance, we exercise our
`discretion and consolidate pursuant to 35 U.S.C. § 315(d), for purposes of
`this Final Written Decision only, the three proceedings.5 For the reasons
`that follow, Petitioner has demonstrated by a preponderance of the evidence
`that claims 1–31 of the ’250 patent are unpatentable.
`
`A. Related Matters
`The parties indicate that the ’250 patent is involved in R2
`Semiconductor, Inc. v. Intel Corp. et al., Civil Action No. 2:16-cv-01011
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`3 Upon authorization, Patent Owner filed a corrected motion to amend in
`IPR2017-00706 and Petitioner filed a surreply in all three cases.
`4 For purposes of this Decision, unless otherwise indicated, a citation to
`“Paper XX” or “Ex. XXXX” will refer to documents filed in IPR2017-
`00705. Similarly, “’706 Paper XX” or “’706 Ex. XXXX” will refer to
`documents filed in IPR2017-00706 and “’1123 Paper XX” or “’1123 Ex.
`XXXX” will refer to documents filed in IPR2017-01123. Moreover, for
`efficiency and clarity, unless there is a relevant difference between the cases,
`we will cite only to documents in IPR2017-00705.
`5 The parties are authorized to file a consolidated request for rehearing in the
`three cases.
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`(E.D. Tex.) and Certain Integrated Circuits with Voltage Regulators and
`Products Containing Same, Investigation No. 337-TA-1024 (USITC). Pet.
`3; Paper 7, 1–2. Petitioner has also challenged the ’250 patent in 3
`additional petitions (IPR2017-00707, -00708, and -01124). Pet. 3; Paper 7,
`1–2.
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`B. The ’250 Patent
`The ’250 patent relates to voltage regulators, which are “universally
`used to convert the battery voltage to the desired fixed value to be supplied
`to the integrated circuit, and to ensure that value remains constant as the
`battery ages and the current used by the integrated circuit changes.” Ex.
`1001, 1:11–24. The ’250 patent describes two types of voltage regulators –
`linear or switched—“switched regulator[s],” in particular,
`convert[] a DC input voltage to a time-varying voltage or current,
`and then make[] use of rectifying or switching elements and
`passive components such as inductors and capacitors, in
`conjunction with a control circuit, to re-convert this time-varying
`signal to a DC voltage at a fixed value differing from the input
`voltage.
`Id. at 1:25–36. According to the ’250 patent, “switched mode converters are
`used for many electronic applications, particularly those where energy
`efficiency and/or battery life are of critical importance.” Id. at 1:57–61. A
`conventional switched voltage regulator, as described in the ’250 patent, is
`shown in Figure 2 below:
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`Figure 2 depicts a conventional switched mode regulator having transistor
`Qseries and transistor Qshunt connected at common switching node Vsw.
`As shown in Figure 2 above, the ’250 patent explains that the
`transistors are alternately turned on and off such that current Iout flows from
`source terminal Vin, through operating transistor Qseries/Qshunt, and through
`inductor Lout to charge up capacitor Cout. Id. at 2:2–36.6 According to the
`’250 patent, the intermittent switching of the transistors causes rapid
`switching in the capacitive load and “voltage spikes will occur in any
`
`6 The ’250 patent explains that “[w]hen the series switch 301 is rapidly
`turned off, this parasitic inductor tries to maintain the same output current,
`causing the voltage Vhi to increase rapidly in the absence of any preventive
`measures . . . [T]he parasitic inductance may interact with parasitic
`capacitances to form a high frequency resonant circuit, which will create a
`persistent ringing condition as a result of the initial rapid voltage transition.”
`Ex. 1001, 16:5–13.
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`converter that has fast switching transitions” caused by physical inductances
`present in any realistic packaged device, including the parasitic inductance
`of the various components of the circuit. Id. at 15:42–65, 16:31–37. In
`addition, according to the Specification, “most switched mode regulators
`require large valued (and physically large and thick) external inductors and
`capacitors to operate.” Id. at 1:62–64.
`The ’250 patent describes “a need for a DC-DC converter that is
`simultaneously compact (including optimally fabrication of all active and
`passive components on a single semiconductor die), low in cost, and highly
`efficient even at small ratios of output to supply voltage and low output
`current.” Id. at 6:66–7:3. In addition, according to the ’250 patent, “[i]t is
`desirable to provide spike protection circuitry for the . . . elements of any
`DC-DC converter employing fast switching transitions.” Id. at 16:43–46.
`To this end, the ’250 patent describes coupling spike protection
`circuitry to the regulator circuitry (e.g. DC to DC converter) such that the
`spike protection circuit protects “switching elements of a converter from
`transient voltages to allow fast low-loss switching operations without
`degradation of reliability.” Id. at 6:66–67, 7:4–7. The voltage regulator
`with the protection circuit, as described in the ’250 patent, is shown in
`Figure 19 below:
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`Figure 19 shows a voltage regulator including a spike protection circuitry.
`As depicted in Figure 19, the ’250 patent describes a
`regulator/switching circuitry wired to generate a regulated voltage from
`power supply Vhi to power supply Vloc, both connected to common node Vsw.
`Id. at 7:11–13. In addition, spike protection circuitry 1910 including resistor
`Rsp and capacitor Csp is coupled to the regulator circuitry as a way to absorb
`voltage spikes and ringing caused by parasitic inductances Lint, Lpar, pk and
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`Lpar, bd. Id. at 18:10–12.7 Thus, according to the Specification, the optimal
`resistance value typically matches closely the characteristic impedance of a
`lumped-element approximation to a transmission line containing a charge-
`storage circuit and a parasitic inductance associated with the regulator
`circuit. Id. at 17:53–67. The ’250 patent states that dissipative element Rsp
`can be realized as polysilicon transistors, thin film metallic resistors, or any
`other convenient resistive element. Id. at 18:59–61.
`
`C. Illustrative Claim
`Of the challenged claims, claims 1, 13, 26, 27, 28, 29, 30, and 31 are
`independent. Claim 1 is illustrative and is reproduced below with disputed
`limitations emphasized:
`1. A voltage regulator, comprising:
`regulator circuitry generating a regulated voltage from a first
`power supply and a second power supply;
`voltage-spike protection circuitry for voltage-spike-protecting
`the regulator circuitry, comprising a dissipative element
`and a charge-storage circuit; wherein
`a value of resistance of the dissipative element is based on a
`characteristic
`impedance
`of
`a
`lumped-element
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`7 According to the ’250 patent, the ringing might also cause a loss in
`efficiency if the ringing is poorly timed with the opening or closing of one of
`the switches. It is, therefore, important to incorporate a dissipative element
`in the spike protection impedance, represented schematically by Rsp to
`minimize undesired ringing in the spike protection circuit. Ex. 1001, 17:24–
`29.
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`approximation of a transmission line, wherein the
`transmission line comprises the charge-storage circuit and
`a parasitic inductance associated with generation of the
`regulator circuitry.
`Ex. 1001, 20:31–42.
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`D. Asserted Grounds of Unpatentability
`Petitioner asserts that claims 1–4, 7–17, 20–26, and 29 are
`unpatentable under § 103(a)8 as obvious over Hibino9 and McMurray,10
`claims 28 and 31 are obvious over Hibino, and claims 5, 6, 18, 19, 27, and
`30 are obvious over Hibino, McMurray, and Wong.11 Pet. 28–72; ’706 Pet.
`28–74; ’1123 Pet. 28–72.
`
`
`8 Because the claims at issue have a filing date prior to March 16, 2013, the
`effective date of the Leahy-Smith America Invents Act, Pub. L. No. 112-29,
`125 Stat. 284 (2011) (“AIA”), we apply the pre-AIA version of 35 U.S.C.
`§§ 102, 103, and 112 in this Decision.
`9 International Publication No. WO2009/113298 A1 (published Sept. 17,
`2009) (“Hibino”). Ex. 1004. In this Decision, all citations are to Exhibit
`1005, which contains a certified English translation of Hibino.
`10 William McMurray, “Optimum Snubbers for Power Semiconductors,”
`IEEE Transactions on Industry Applications, Vol. IA-8, No. 5 (Sept./Oct.
`1972) (“McMurray”). Ex. 1003.
`11 U.S. Patent No. 5,485,292 (issued Jan. 16, 1996) (“Wong”). IPR2017-
`01123, Ex. 1430.
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`II. DISCUSSION
`A. Claim Construction
`In an inter partes review, a claim in an unexpired patent shall be given
`its broadest reasonable construction in light of the specification of the patent
`in which it appears. 37 C.F.R. § 42.100(b). Under the broadest reasonable
`construction standard, claim terms are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in the
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007). Only terms that are in controversy need to be
`construed, and then only to the extent necessary to resolve the controversy.
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999).
`“dissipative element”
`1.
`During the pre-institution stage of these proceedings, the parties
`disagreed regarding the broadest reasonable interpretation of the term
`“dissipative element.” Pet. 23–27; Prelim. Resp. 18–28. For purposes of the
`Institution Decision, we agreed with Petitioner and found the term
`“dissipative element” to be written in means-plus-function format with a
`function of dissipating energy12 and a corresponding structure of a resistor.
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`12 Both Petitioner and Patent Owner agree that, if construed as requiring
`means-plus-function treatment, the function of “dissipative element” would
`be to dissipate energy. Pet. 22, Prelim. Resp. 22.
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`Inst. Dec. 9–13. For purposes of analyzing patentability of the challenged
`claims, Patent Owner does not challenge this construction. PO Resp. 17.
`We, therefore, adopt the analysis and construction of the term “dissipative
`element” from the Institution Decision. Inst. Dec. 9–13.
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`“voltage spike protection circuitry”
`2.
`Patent Owner asserts that the terms “voltage spike protection circuitry
`for voltage-spike protecting the regulator circuitry”13 and “voltage-spike-
`protecting the regulator circuitry with voltage spike protection circuitry”14
`“do not have a plain and ordinary meaning.” PO Resp. 18; Tr. 33:14–39:23.
`Accordingly, Patent Owner proposes that to properly capture the scope of
`the claims as reflected in the Specification, these terms should be construed
`“to require that the voltage-spike protecting circuitry is on the same
`integrated circuit as the switches they protect.” PO Resp. 18 n.18.
`Arguing that Patent Owner’s narrower construction would
`“improperly limit the claims to certain embodiments,” Petitioner notes that
`the claims explicitly define “voltage spike protection circuitry” simply as
`“circuitry that protects the regulator circuitry from voltage spikes.” Reply 3
`
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`13 As recited by independent claims 1 and 27. Ex. 1001, 20:34–35, 22:31–
`32. Claim 29, similarly recites “voltage spike protection circuitry . . . for
`voltage-spike-protecting the regulatory circuitry.” Id. at 22:63–65.
`14 As recited by independent claims 13, 26, and 30. Ex. 1001, 21:19–20,
`22:17–19, 23:11–12.
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`(citing Ex. 1001, claims 1, 13, 26, 28, 29, and 31). Petitioner adds that none
`of the claims include language requiring that voltage spike protection
`circuitry to be “located on the same integrated circuit” as the regulator
`circuitry. Id. at 4. Petitioner, therefore, asserts that the broadest reasonable
`construction of the term “voltage spike protection circuitry” is coextensive
`with the definition in the claims—“circuitry that protects the regulator
`circuitry from spikes in voltage.” Id.
`Notwithstanding Patent Owner’s arguments to the contrary, as
`discussed below, we agree with Petitioner that the broadest reasonable
`construction of the voltage spike protection circuitry terms, as used in the
`’250 patent, does not limit the location of voltage spike protection circuitry
`to the same chip or integrated circuit as the regulator circuitry it is designed
`to protect.
`Patent Owner notes that every disclosed embodiment in the ’250
`patent shows both the protection circuitry and the regulator circuitry on the
`same integrated circuit. PO Resp. 19–23. Specifically, Patent Owner points
`to the embodiments shown in Figures 12, 18, 19, 20, and 22. Id. (citing Ex.
`1001, Figs. 12, 19, 20, 22, 10:43–46, 16:55–56). Petitioner does not dispute
`that all the embodiments discussed in the Specification include the voltage
`spike protection circuitry on the same chip or integrated circuit as the
`regulator circuitry that it protects. See Reply 3–4. Petitioner, however,
`points out that each of these embodiments is identified as an “example” or
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`an “embodiment.” Id. (citing Ex. 1001, 10:42; 16:52, 18:15–16, 19:35,
`19:47–48). Based on this language, Petitioner argues that “[i]t is improper
`to read limitations from the embodiments in the specification into the
`claims.” Id. at 4 (citing Hill-Rom Servs. v. Stryker Corp., 755 F.3d 1367,
`1371 (Fed. Cir. 2014)). We agree that it would be improper to read this
`limitation from the Specification into the claims.
`Further, Patent Owner asserts that because the Specification employs
`very fast switching times using small transistors in the integrated circuits,
`the circuitries must be located on the same integrated circuit. PO Resp. 19–
`20, 23–24. Specifically, Patent Owner points to the Specification’s
`acknowledgement that the consumer market demands creation of the
`“thinnest and smallest devices possible.” Id. at 19 (quoting Ex. 1201, 3:38–
`40). Patent Owner further notes the disclosure that increased switching
`frequency and the resulting benefit of lower-valued inductors and capacitors
`allows for “use of planar geometries that can be integrated on printed-circuit
`boards or fabricated in integrated circuits.” Id. at 18–19 (quoting Ex. 1001,
`3:58–65). According to Patent Owner, it is this act of achieving very fast
`switching times using advanced transistors on integrated circuits that causes
`the problem of voltage spiking that the ’250 patent addresses. Id. at 19
`(citing Ex. 1001, 5:49–50, 5:60–63, 6:56–65). Petitioner does not dispute
`that the ’250 patent teaches the benefits of small devices and fast switching
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`times, but argues that “these passages say nothing about the location of the
`spike protection circuitry.” Reply 4.
`We agree with Patent Owner that the ’250 patent describes the
`specific problem it is trying to solve in terms that imply single chip
`implementation. For example, the Specification states that “there exists a
`need for a DC-DC converter that is simultaneously compact (including
`optimally fabrication of all active and passive components on a single
`semiconductor die), low in cost, and highly efficient” that is protected from
`voltage spikes. Ex. 1001, 6:66–7:7. Dr. Pedram supports this understanding
`of the ’250 patent, explaining that “[b]y moving the switching transistors on-
`chip, one can ‘reduce[] the overall size of the voltage regulator’—that is, the
`size of the inductors and capacitors thereon.” Ex. 2008 ¶ 34 (citing Ex.
`1001, 6:66–7:3, 1:62–64). We are, nonetheless, unpersuaded that such
`description is sufficient to require Patent Owner’s proposed claim
`construction of the cited term. The claims are written in broad language and
`do not recite the specific problem to be solved or the need to be satisfied.
`Additionally, Patent Owner notes that “in the only section dedicated
`to voltage spike protection,” the two circuits are placed on the same
`integrated circuit. PO Resp. 20 (quoting Ex. 1001, 15:51–57 (describing
`“several physical inductances present in any realistic packaged device,
`including . . . the parasitic inductance of the traces and/or wirebonds
`connecting the supply leads or bumps to the contact pads on the integrated
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`circuit containing the converter”)). Similarly, Patent Owner asserts that the
`’250 patent “disclaims voltage spike protection circuits that are not on the
`same integrated circuit as the regulatory circuitry,” by stating “[i]t should be
`noted that inclusion of an off-chip capacitor does not appreciably affect the
`size of the spikes.” PO Resp. 24 (quoting Ex. 1001, 16:29–30). Petitioner
`argues that this is not a disavowal of non-integrated-circuit implementation,
`but instead that it “suggests a potential disadvantage.” Reply 4–5 (citing
`Epistar Corp. v. Int’l Trade Comm’n, 566 F.3d 1321, 1335 (Fed. Cir. 2009)).
`Petitioner adds that “in full context, the passage refers only to a specific
`‘example,’ not all voltage spike protection circuits.” Id. at 5 (citing Ex.
`1001, 16:13–30; Ex. 1045 ¶¶ 20–21). We agree with Petitioner that,
`although it may suggest a potential disadvantage of a non-integrated-circuit
`implementation, this language does not rise to disavowal of non-integrated
`circuits.
` We read the Specification, as a whole, as touting the benefit of
`voltage spike protection circuitry as being more effective in affecting
`voltage spikes when implemented on the same chip as the regulator
`circuitry. Ex. 1001, 16:29–30 (“It should be noted that inclusion of an off-
`chip capacitor does not appreciably affect the size of the spikes.”).
`Petitioner’s arguments are not inconsistent with this understanding. Reply 4
`(“At most, this passage suggests a potential disadvantage associated with
`non-integration.”). However, the claims are not limited to the most effective
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`implementation of the voltage spike protection circuitry. Therefore, this
`particular benefit does not limit the broadest reasonable interpretation of the
`claims.
`In summary, Patent Owner’s argument is that the ’250 patent
`(1) discloses that the problem to be solved with voltage spiking occurs on
`compact, fast-switching converters, (2) suggests that implementing the
`voltage spike protection circuitry on a separate chip from the regulator
`circuitry would be less efficient, and (3) describes multiple embodiments
`showing only single chip implementation. Despite our agreement with much
`of this representation of what the ’250 patent discloses, we do not agree that
`such disclosures limit the scope of the claims. Nothing in the ’250 patent
`defines voltage spike protection circuitry to be implemented on the same
`integrated circuit or the same chip as the regulator circuitry. It is not
`inconsistent with the Specification for the claim term to read on both
`implementations. We, therefore, conclude that Petitioner’s proposed
`construction is properly the broadest reasonable construction of the term.
`See Smith, 871 F.3d at 1383. Consistent with the record before us, we
`construe voltage spike protection circuitry to be “circuitry that protects the
`regulator circuitry from spikes in voltage.”
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`B. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art, various factors
`may be considered, including the “type of problems encountered in the art;
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`prior art solutions to those problems; rapidity with which innovations are
`made; sophistication of the technology; and educational level of active
`workers in the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`(internal quotation and citation omitted).
`In our Institution Decision, we summarized the parties contentions,
`notably that Petitioner proposes that the person of ordinary skill “would have
`a Bachelor of Science degree in Electrical Engineering and two years of
`graduate work or work experience in power electronics circuit design and
`chip design, or equivalent experience” and Patent Owner proposes that such
`person would have “three years of work or research experience in the fields
`of power electronics or high-speed mixed-signal IC design,” or “a Master’s
`degree in electrical engineering and two years of work or research
`experience in the fields of power electronics or high-speed mixed-signal IC
`design.” Inst. Dec. 13–14 (citing Ex. 1002 ¶ 57; Ex. 2001 ¶ 92). We
`adopted Patent Owner’s proposed level because we did not “observe a
`meaningful difference[] between the parties’ assessments,” found either
`assessment to be “consistent with the level of ordinary skill in the art at the
`time of the invention as reflected in the prior art,” and found the Decision
`“supported by either assessment.” Id. at 14 (citing Okajima v. Bourdeau,
`261 F.3d 1350, 1355 (Fed. Cir. 2001)).
`Post-institution, neither party further addresses the proper level of
`ordinary skill in the art. See PO Resp., Reply. Thus, for purposes of this
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`Decision, we continue to adopt Patent Owner’s proposed level of ordinary
`skill in the art.
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`C. Obviousness over Hibino and McMurray
`Petitioner asserts that claims 1–4, 7–17, 20–26, and 29 are
`unpatentable under 35 U.S.C. § 103(a) as obvious over the combined
`teachings of Hibino and McMurray. Pet. 28–72; ’706 Pet. 28–72. Patent
`Owner disagrees. PO Resp. 59–84; ’706 PO Resp. 63–90. As discussed
`below, Petitioner has made a persuasive showing as to this assertion.
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`Overview of Hibino
`1.
`Hibino describes a power converter system for converting AC or DC
`power to AC power having a predetermined voltage and frequency,
`including a “snubber circuit.”15 Ex. 1005, Abstract. Figure 4 of Hibino is
`reproduced below.
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`15 The function of a snubber circuit is analogous to that of a voltage spike
`protection circuit. See Ex. 1005 ¶ 5.
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`Figure 4 shows a power converter with a snubber circuit.
`Figure 4 depicts power converter 400 containing snubber circuit 300
`for each switching device 130. Id. ¶ 76. Snubber circuit 300 includes
`capacitor 301 and a resister (unlabeled) and is used as a protection circuit to
`reduce any surge voltage generated by an inductance of a wiring when a
`switching device is turned on or off. Id. at 5, 99.
`
`Hibino Qualifies as Prior Art
`2.
`Hibino was published September 17, 2009. Ex. 1005, (43). Thus,
`Petitioner asserts that it is prior art under 35 U.S.C. § 102(a). Pet. 5. Patent
`Owner, however, argues that Hibino is not prior art to the ’250 patent
`because the inventors of the ’250 patent, David Fisher and Lawrence Burns,
`conceived of the claimed inventions at least as early as September 14, 2009,
`and thereafter “exercised reasonable diligence to reduce their invention to
`practice.” PO Resp. 26–59; ’706 PO Resp. 27–63; ’1123 PO Resp. 28–58.
`Petitioner argues in response that Patent Owner has failed to demonstrate
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`both conception (Reply 5–11) and reduction to practice (id. at 11–12). For
`the reasons discussed below, we agree with Petitioner that Patent Owner has
`not met its burden to overcome Hibino’s filing date. Specifically, we find
`that Patent Owner has not sufficiently shown conception of the claimed
`“value of resistance of the dissipative element is based on a characteristic
`impedance of a lumped-element approximation of a transmission line” (“the
`resistance value limitation”)16.
`Patent Owner bears the burden to establish the facts necessary to
`overcome Hibino’s filing date. In re Magnum Oil Tools Int’l, Ltd. 829 F.3d
`1364, 1375–76 (Fed. Cir. 2016) (“[I]n the context of establishing conception
`and reduction to practice for the purposes of establishing a priority date, the
`burden of production can shift from the patent challenger to the patentee . . .
`because . . . a patentee bears the burden of establishing that its claimed
`invention is entitled to an earlier priority date than an asserted prior art
`reference.”) (internal citations and quotations omitted). To prove
`conception, Patent Owner is require to show “formation in the mind of the
`inventor, of a definite and permanent idea of the complete and operative
`invention, as it is hereafter to be applied in practice.” Dawson v. Dawson,
`710 F.3d 1347, 1352 (Fed. Cir. 2013) (internal citations and quotations
`omitted). Moreover, “conception must encompass all limitations of the
`
`
`16 Petitioner refers to the resistance value limitation as the “based on” or
`“matches” limitations. Reply 6.
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`claimed invention.” Brown v. Barbacid, 276 F.3d 1327, 1336 (Fed. Cir.
`2002). “The conception analysis necessarily turns on the inventor’s ability
`to describe his invention with particularity. Until he can do so, he cannot
`prove possession of the complete mental picture of the invention.”
`Burroughs Wellcome Co. v. Barr Labs., Inc., 40 F.3d 1223, 1228 (Fed. Cir.
`1994).
`Proof of conception must be by “corroborating evidence which shows
`that the inventor disclosed to others his ‘completed thought expressed in
`such clear terms as to enable those skilled in the art’ to make the invention.”
`Coleman v. Dines, 754 F.2d 353, 359 (Fed. Cir. 1985) (citing Field v.
`Knowles, 183 F.2d 593, 601 (CCPA 1950)); see also Mahurkar v. C.R. Bard,
`Inc., 79 F.3d 1572, 1577 (Fed. Cir. 1996) (corroboration requirement “arose
`out of a concern that inventors testifying in patent infringement cases would
`be tempted to remember facts favorable to their case by the lure of
`protecting their patent or defeating another’s patent”). The sufficiency of
`corroboration is determined according to a “rule of reason.” Price v.
`Symsek, 988 F.2d 1187, 1195 (Fed. Cir. 1993). This, however, does not
`dispense with the requirement that some independent evidence provide
`corroboration. Coleman, 754 F.2d at 360. The requirement of
`“independent” corroboration requires evidence other than the inventor’s
`testimony. In re NTP, Inc., 654 F.3d 1279, 1291–92 (Fed. Cir. 2011).
`
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`To show conception prior to Hibino’s priority date, Patent Owner
`provides testimony from Mr. Fisher that he and Mr. Burns designed an
`“A101 chip” incorporating the claimed voltage spike protection circuitry.
`PO Resp. 30–33 (citing Ex. 2015); ’706 PO Resp. 31–34 (citing ’706 Ex.
`2115); ’1123 PO Resp. 32–35 (citing ’1123 Ex. 2415). According to Patent
`Owner, the final design of this chip was completed, recorded in schematics,
`and sent to a manufacturer by September 15, 2009. PO Resp. 30; Ex. 2015
`¶ 70; ’706 PO Resp. 32; ’706 Ex. 2115 ¶ 70; ’1123 PO Resp. 33; ’1123 Ex.
`2415 ¶ 70. As proof, Patent Owner proffers several A101 chip schematics
`(Exs. 2016–2020; ’706 Exs. 2116–2120; ’1123 Exs. 2416–2420). PO Resp.
`33–57; ’706 PO Resp. 34–60; ’1123 PO Resp. 35–56.
`Specifically, to show conception of claim 1’s resistance value
`limitation, Patent Owner points to the schematic of Exhibit 2016. Id. at 46.
`According to Patent Owner, this schematic “shows that the parasitic
`inductance associated with the regulatory circuitry that is located between
`the supply and regulator circuitry.” Id. The third page of Exhibit 2016 is
`reproduced below.
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`According to Patent Owner, page 3 of Exhibit 2016 shows “a close-up
`of the inductances” of the “coretech_pkg” created using the system design
`program “Cadence” at least as early as September 14, 2009. Id. at 46–48;
`Ex. 2015 ¶¶ 51–54. Patent Owner explains that this schematic “shows the
`parasitic inductances associated with each switching block segment,”
`including “the elements labelled as L500, L502, L503, L505, L506, L508,
`L509, L511, L1001, L1002, L1003, L1004, L1024, L1009, L1011, L1012,
`L1020, L1018, L1019, L1023, L1021, L1022” from each switching block
`
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`segment. Ex. 2015 ¶ 55; PO Resp. 46. Patent Owner a
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